SC16C554DBIA68 ,SC16C554B/554DB; 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOsFeatures■ 4 channel UART■ 5 V, 3.3 V and 2.5 V operation■ Industrial temperature range (- 40 °C to ..
SC16C554DBIA68 ,SC16C554B/554DB; 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOsFeatures and benefits 4 channel UART 5 V, 3.3 V and 2.5 V operation Industrial temperature range ..
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SC16C554BIB80-SC16C554DBIA68
SC16C554B/554DB; 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
General descriptionThe SC16C554B/554DB is a 4-channel Universal Asynchronous Receiver and
Transmitter (QUART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 5 Mbit/s. It comes with an Intel® or Motorola® interface.
The SC16C554B/554DB is pin compatible with the ST16C554 and TL16C554 and it will
power-up to be functionally equivalent to the 16C454. Programming of control registers
enables the added featuresof the SC16C554B/554DB. Someof these added features are
the 16-byte receive and transmit FIFOs, four receive trigger levels. The
SC16C554B/554DB also provides DMA mode data transfers through FIFO trigger levels
and the TXRDY and RXRDY signals. On-board status registers provide the user with error
indications, operational status, and modem interface control. System interrupts may be
tailored to meet user requirements. An internal loop-back capability allows on-board
diagnostics.
The SC16C554B/554DB operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature
range, and is available in plastic PLCC68, LQFP64, and LQFP80 packages.
Features 4 channel UART5V , 3.3 V and 2.5 V operation Industrial temperature range (−40 °C to +85 °C) The SC16C554B is pin and software compatible with the industry-standard
ST16C454/554, ST68C454/554, ST16C554, TL16C554 The SC16C554DB is pin and software compatible with ST16C554D, and software
compatible with ST16C454/554, ST16C554, TL16C554 Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5V5 V tolerant inputs 16-byte transmit FIFO 16-byte receive FIFO with error flags Programmable auto-RTS and auto-CTS In auto-CTS mode, CTS controls transmitter In auto-RTS mode, RxFIFO contents and threshold control RTS Automatic hardware flow control (RTS/CTS) Software selectable Baud Rate Generator Four selectable Receive FIFO interrupt trigger levels Standard modem interface
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte
FIFOs
Philips Semiconductors SC16C554B/554DB Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break) Transmit, Receive, Line Status, and Data Set interrupts independently controlled Fully programmable character formatting: 5, 6, 7, or 8-bit characters Even, Odd, or No-Parity formats 1, 11 ⁄2, or 2-stop bit Baud generation (DC to 5 Mbit/s) False start-bit detection Complete status reporting capabilities 3-state output TTL drive capabilities for bi-directional data bus and control bus Line break generation and detection Internal diagnostic capabilities: Loop-back controls for communications link fault isolation Prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, CD).
Ordering information
Table 1: Ordering informationSC16C554DBIA68 PLCC68 plastic leaded chip carrier; 68 leads SOT188-2
SC16C554DBIB64 LQFP64 plastic low profile quad flat package; 64 leads; body 10×10× 1.4 mm SOT314-2
SC16C554BIB64 LQFP64 plastic low profile quad flat package; 64 leads; body 10×10× 1.4 mm SOT314-2
SC16C554BIB80 LQFP80 plastic low profile quad flat package; 80 leads; body 12×12× 1.4 mm SOT315-1
Philips Semiconductors SC16C554B/554DB Block diagram
Philips Semiconductors SC16C554B/554DB
Philips Semiconductors SC16C554B/554DB Pinning information
5.1 Pinning
5.1.1 PLCC68
Philips Semiconductors SC16C554B/554DB
Philips Semiconductors SC16C554B/554DB
5.1.2 LQFP64
Philips Semiconductors SC16C554B/554DB
5.1.3 LQFP80
Philips Semiconductors SC16C554B/554DB
5.2 Pin description
Table 2: Pin description
Philips Semiconductors SC16C554B/554DB
Table 2: Pin description …continued
Philips Semiconductors SC16C554B/554DB
Table 2: Pin description …continued
Philips Semiconductors SC16C554B/554DB
Table 2: Pin description …continued
Philips Semiconductors SC16C554B/554DB Functional descriptionThe SC16C554B/554DB provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessaryfor converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character. Data integrity is insured by attaching a parity bit to the data character. The
paritybitis checkedby the receiverfor any transmissionbit errors. The electronic circuitry
to provide all these functions is fairly complex, especially when manufactured on a single
integrated silicon chip. The SC16C554B/554DB represents such an integration with
greatly enhanced features. The SC16C554B/554DB is fabricated with an advanced
CMOS process to achieve low drain power and high speed requirements.
The SC16C554B/554DB is an upward solution that provides 16 bytes of transmit and
receive FIFO memory, instead of none in the 16C454. The SC16C554B/554DB is
designedto work with high speed modems and shared network environments that require
fast data processing time. Increased performance is realized in the SC16C554B/554DB
by the larger transmit and receive FIFOs. This allows the external processor to handle
more networking tasks within a given time. In addition, the four selectable levels of FIFO
trigger interrupt is uniquely provided for maximum data throughput performance,
especially when operating in a multi-channel environment. The combination of the above
greatly reduces the bandwidth requirement of the external controlling CPU, increases
performance, and reduces power consumption.
The SC16C554B/554DBAI68 combines the package interface modes of the 16C454/554
and 68C454/554 seriesona single integrated chip. The16 mode interfaceis designedto
operate with the Intel-type of microprocessor bus, while the 68 mode is intended to
operate with Motorola and other popular microprocessors. Following a reset, the
SC16C554B/554DBAI68 is downward compatible with the 16C454/554 or the
68C454/554, dependent on the state of the interface mode selection pin, 16/68.
The SC16C554B/554DB is capable of operation to 1.5 Mbit/s with a 24 MHz crystal andto5 Mbit/s withan external clock input(at 3.3V and5V;at 2.5V the maximum speed
is 3 Mbit/s).
The rich feature set of the SC16C554B/554DB is available through internal registers.
Selectable receive FIFO trigger levels, selectable TX and RX baud rates, and modem
interface controls are all standard features. In the 16 mode, INTSEL and MCR[3] can be
configured to provide a software controlled or continuous interrupt capability. Due to pin
limitations of the 64-pin package, this feature is offered by two different LQFP64
packages. The SC16C554DB operates in the continuous interrupt enable mode by
bonding INTSEL to VCC internally. The SC16C554B operates in conjunction with MCR[3]
by bonding INTSEL to GND internally.
Philips Semiconductors SC16C554B/554DB
6.1 Interface optionsTwo user interface modes are selectablefor the PLCC68 package. These interface modes
are designatedas the ‘16 mode’ and the ‘68 mode’. This nomenclature correspondsto the
early 16C454/554 and 68C454/554 package interfaces respectively.
6.1.1 The 16 mode interfaceThe 16 mode configures the package interface pins for connection as a standard series (Intel) device and operates similar to the standard CPU interface available on
the 16C454/554. In the 16 mode (pin 16/68 = logic 1), each UART is selected with
individual chip select (CSx) pins, as shown in Table3.
6.1.2 The 68 mode interfaceThe 68 mode configures the package interface pins for connection with Motorola, and
other popular microprocessor bus types. The interface operates similar to the
68C454/554. In this mode, the SC16C554B/554DB decodes two additional addresses,to A4, to select one of the four UART ports. The A3to A4 address decode function is
used only when in the 68 mode (16/68 = logic 0), and is shown in Table4.
Table 3: Serial port channel selection, 16 mode interface1111 none
0111A
1011B
1101C
1110D
Table 4: Serial port channel selection, 68 mode interface n/a n/a none
000A
001B
010C
011D
Philips Semiconductors SC16C554B/554DB
6.2 Internal registersThe SC16C554B/554DB provides 12 internal registers for monitoring and control. These
registers are shown in Table 5. These registers function as data holding registers
(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register
(FCR), line status and control registers (LCR/LSR), modem status and control registers
(MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user
accessible scratchpad register (SPR). Register functions are more fully described in the
following paragraphs.
[1] These registers are accessible only when LCR[7] is a logic0.
[2] These registers are accessible only when LCR[7] is a logic1.
6.3 FIFO operationThe 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register
(FCR) bit 0. With SC16C554B devices, the user can set the receive trigger level, but not
the transmit trigger level. The receiver FIFO section includesa time-out functionto ensure
data is delivered to the external CPU. An interrupt is generated whenever the Receive
Holding Register (RHR) has not been read following the loading of a character or the
receive trigger level has not been reached.
Table 5: Internal registers decoding
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1] 0 0 Receive Holding Register Transmit Holding Register 0 1 Interrupt Enable Register Interrupt Enable Register 1 0 Interrupt Status Register FIFO Control Register 1 1 Line Control Register Line Control Register 0 0 Modem Control Register Modem Control Register 0 1 Line Status Register n/a 1 0 Modem Status Register n/a 1 1 Scratchpad Register Scratchpad Register
Baud rate register set (DLL/DLM)[2] 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 1 MSB of Divisor Latch MSB of Divisor Latch
Table 6: Flow control mechanism 4 1 8 4 8 12 8 14 14 10
Philips Semiconductors SC16C554B/554DB
6.4 Autoflow control (see Figure7)Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input
must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes
active when the receiver needs more data and notifies the sending serial device. When
RTSis connectedto CTS, data transmission does not occur unless the receiver FIFO has
space for the data; thus, overrun errors are eliminated using UART 1 and UART 2 from a
SC16C554B/554DB with the autoflow control enabled. If not, overrun errors occur when
the transmit data rate exceeds the receiver FIFO read latency.
6.4.1 Auto-RTS (see Figure7)Auto-RTS data flow control originates in the receiver timing and control block (see block
diagramsin Figure1 and Figure2) andis linkedto the programmed receiver FIFO trigger
level. When the receiver FIFO level reachesa trigger levelof1,4,or8 (see Figure9), RTS
is de-asserted. With trigger levels of 1, 4, and 8, the sending UART may send an
additional byte after the trigger levelis reached (assuming the sending UART has another
byte to send) because it may not recognize the de-assertion of RTS until after it has
begun sending the additional byte. RTS is automatically reasserted once the RX FIFO is
emptied by reading the receiver buffer register. When the trigger level is 14 (see
Figure 10), RTS is de-asserted after the first data bit of the 16th character is present on
the RX line. RTS is reasserted when the RX FIFO has at least one available byte space.
6.4.2 Auto-CTS (see Figure7)The transmitter circuitry checks CTS before sending the next data byte. When CTS is
active,it sends the next byte.To stop the transmitter from sending the following byte, CTS
must be released before the middle of the last stop bit that is currently being sent (see
Figure8). The auto-CTS function reduces interruptsto the host system. When flow control
is enabled, CTS level changes do not trigger host interrupts because the device
automatically controls its own transmitter. Without auto-CTS, the transmitter sends any
data present in the transmit FIFO and a receiver overrun error may result.
Philips Semiconductors SC16C554B/554DB
6.4.3 Enabling autoflow control and auto-CTSAutoflow control is enabled by setting MCR[5] and MCR[1].
6.4.4 Auto-CTS and auto-RTS functional timingThe receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in
Figure 9 and Figure 10.
Table 7: Enabling autoflow control and auto-CTS 1 auto RTS and CTS 0 auto CTS X disable
Philips Semiconductors SC16C554B/554DB
6.5 Hardware/software and time-out interruptsFollowinga reset,if the transmitter interruptis enabled, the SC16C554B/554DB will issue interruptto indicate that the Transmit Holding Registeris empty. This interrupt mustbe
serviced prior to continuing operations. The LSR register provides the current singular
highest priority interrupt only. Only after servicing the higher pending interrupt will the
lower priority interrupt(s)be reflectedin the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the
SC16C554B/554DB FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The time-out
counter is reset at the center of each stop bit received or each time the receive holding
register (RHR) is read. The actual time-out value is 4 character time.
In the 16 mode for the PLCC68 package, the system/board designer can optionally
provide software controlled 3-state interrupt operation. This is accomplished by INTSEL
and MCR[3]. When INTSEL interface pin is left open or made a logic 0, MCR[3] controls
the 3-state interrupt outputs, INTAto INTD. When INTSEL is a logic 1, MCR[3] has no
effect on the INTAto INTD outputs, and the package operates with interrupt outputs
enabled continuously.
6.6 Programmable baud rate generatorThe SC16C554B/554DB supports high speed modem technologies that have increased
input data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate. 128.0 kbit/s ISDN modem that supports data compression may needan input data rate
of 460.8 kbit/s.
Philips Semiconductors SC16C554B/554DBA single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generatoris capable
of accepting an input clock up to 80 MHz (for 3.3 V and 5 V operation), as required for
supportinga5 Mbit/s data rate. The SC16C554B/554DB canbe configuredfor internalor
external clock operation. For internal clock oscillator operation, an industry standard
microprocessor crystal (parallel resonant/22 pF to 33 pF load) is connected externally
between the XT AL1 and XTAL2 pins (see Figure 11). Alternatively, an external clock can
be connected to the XTAL1 pin to clock the internal baud rate generator for standard or
custom rates (see Table 8).
Programming the Baud Rate Generator registers DLM (MSB) and DLL (LSB) provides a
user capability for selecting the desired final baud rate.
Table 8: Baud rate generator programming table using a 7.3728 MHz clock200 2304 900 09 00
1200 384 180 01 80
2400 192 C0 00 C0
4800 96 60 00 60
9600 48 30 00 30
19.2k 24 18 00 18
38.4k 12 0C 00 0C
76.8k 6 06 00 06
153.6k 3 03 00 03
230.4k 2 02 00 02
460.8k 1 01 00 01
Philips Semiconductors SC16C554B/554DB
6.7 DMA operationThe SC16C554B/554DB FIFO trigger level provides additional flexibility to the user for
block mode operation. LSR[5:6] providean indication when the transmitteris emptyor has
an empty location(s). The user can optionally operate the transmit and receive FIFOs in
the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA
mode is de-activated (DMA Mode 0), the SC16C554B/554DB activates the interrupt
output pin for each data transmit or receive operation. When DMA mode is activated
(DMA Mode 1), the user takes the advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the preset trigger level. In this
mode, the SC16C554B/554DB sets the interrupt output pin when the characters in the
receive FIFOs are above the receive trigger level.
6.8 Loop-back modeThe internal loop-back capability allows on-board diagnostics.In the loop-back mode, the
normal modem interface pins are disconnected and reconfigured for loop-back internally.
MCR[0:3] register bits are used for controlling loop-back diagnostic testing. In the
loop-back mode, OP1 and OP2 in the MCR register (bits 2:3) control the modem RI and
CD inputs, respectively. MCR signals DTR and RTS (bits 0:1) are used to control the
modem DSR and CTS inputs, respectively. The transmitter output (TX) and the receiver
input (RX) are disconnected from their associated interface pins, and instead are
connected together internally (see Figure 12). The CTS, DSR, CD, and RI are
disconnected from their normal modem control input pins, and instead are connected
internally to RTS, DTR, OP2 and OP1. Loop-back test data is entered into the transmit
holding register via the user data bus interface, D0to D7. The transmit UART serializes
the data and passes the serial data to the receive UART via the internal loop-back
connection. The receive UART converts the serial data back into parallel data thatis then
made available at the user data interface D0to D7. The user optionally compares the
received data to the initial transmitted data for verifying error-free operation of the UART
TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read using
lower four bitsof the Modem Status Register (MSR[0:3]) insteadof the four Modem Status
Register bits 4:7. The interrupts are still controlled by the IER.
Philips Semiconductors SC16C554B/554DB
Philips Semiconductors SC16C554B/554DB
Philips Semiconductors SC16C554B/554DB Register descriptionsTable 9 details the assigned bit functions for the SC16C554B/554DB internal registers.
The assigned bit functions are more fully defined in Section 7.1 through Section 7.10.
[1] The value shown represents the register’s initialized HEX value; X= not applicable.
[2] These registers are accessible only when LCR[7]=0.
[3] The Special Register set is accessible only when LCR[7] is set to a logic1.
Table 9: SC16C554B/554DB internal registers
General Register set[2]
Special Register set[3]
Philips Semiconductors SC16C554B/554DB
7.1 Transmit (THR) and Receive (RHR) Holding RegistersThe serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writingto the THR transfers the contentsof the data bus (D7to D0)to the
THR, providing that the THRor TSRis empty. The THR empty flagin the LSR register will
be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.
Note that a write operation can be performed when the THR empty flag is set
(logic0= FIFO full; logic1= at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C554B/554DB and receive FIFO by reading the
RHR register. The receive section provides a mechanism to prevent false starts. On the
falling edge of a start or false start bit, an internal receiver counter starts counting clocks
at the 16× clock rate. After 71 ⁄2 clocks, the start bit time should be shifted to the center of
the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTAto INTD output pins in the 16 mode, or on wire-OR IRQ output pin in the mode.
Table 10: Interrupt Enable Register bits description7:4 IER[7:4] Reserved; set to ‘0’. IER[3] Modem Status Interrupt.
Logic 0 = Disable the modem status register interrupt (normal default
condition).
Logic 1 = Enable the modem status register interrupt. IER[2] Receive Line Status interrupt.
Logic0= Disable the receiver line status interrupt (normal default condition).
Logic 1 = Enable the receiver line status interrupt. IER[1] Transmit Holding Register interrupt. This interrupt will be issued whenever the
THR is empty, and is associated with LSR[1].
Logic 0 = Disable the transmitter empty interrupt (normal default condition).
Logic 1 = Enable the transmitter empty interrupt. IER[0] Receive Holding Register interrupt. This interrupt willbe issued when the FIFO
has reached the programmed trigger level, or is cleared when the FIFO drops
below the trigger level in the FIFO mode of operation.
Logic 0 = Disable the receiver ready interrupt (normal default condition).
Logic 1 = Enable the receiver ready interrupt.
Philips Semiconductors SC16C554B/554DB
7.2.1 IER versus Receive FIFO interrupt mode operationWhen the receive FIFO (FCR[0]= logic 1), and receive interrupts (IER[0]= logic 1) are
enabled, the receive interrupts and register status will reflect the following:
The receive data available interrupts are issued to the external CPU when the FIFO
has reached the programmed trigger level. It will be cleared when the FIFO drops
below the programmed trigger level.
FIFO status will also be reflected in the user accessible ISR register when the FIFO
trigger level is reached. Both the ISR register status bit and the interrupt will be
cleared when the FIFO drops below the trigger level.
The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the FIFO is empty.
7.2.2 IER versus Receive/Transmit FIFO polled mode operationWhen FCR[0]= logic 1, resetting IER[0:3] enables the SC16C554B/554DB in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the
LSR, either or both can be used in the polled mode by selecting respective transmit or
receive control bit(s).
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1:4] will provide the type of errors encountered, if any.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will indicate any FIFO data errors.
7.3 FIFO Control Register (FCR)This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
7.3.1 DMA mode
7.3.1.1 Mode 0 (FCR bit 3 = 0)Set and enable the interruptfor each single transmitor receive operation, andis similarto
the 16C454 mode. T ransmit Ready (TXRDY) will go to a logic 0 whenever an empty
transmit space is available in the Transmit Holding Register (THR). Receive Ready
(RXRDY) willgotoa logic0 whenever the Receive Holding Register (RHR)is loaded with
a character.
7.3.1.2 Mode 1 (FCR bit 3 = 1)Set and enable the interruptina block mode operation. The transmit interruptis set when
there are oneor more FIFO locations empty. The receive interruptis set when the receive
FIFO fills to the programmed trigger level. However, the FIFO continues to fill regardless
of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the
FIFO fill level is above the programmed trigger level.
Philips Semiconductors SC16C554B/554DB
7.3.2 FIFO mode
Table 11: FIFO Control Register bits description7:6 FCR[7:6] RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt. interruptis generated when the numberof charactersin the FIFO equals
the programmed trigger level. However, the FIFO will continue to be loaded
until it is full. Refer to Table 12.
5:4 FCR[5:4] Not used; initialized to logic0. FCR[3] DMA mode select.
Logic 0 = Set DMA mode ‘0’ (normal default condition).
Logic 1 = Set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C554B/554DB is in the16C450 mode (FIFOs disabled; FCR[0]= logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0]= logic1; FCR[3]= logic0), and when there areno
characters in the transmit FIFO or transmit holding register, the TXRDY pin
willbea logic0. Once active, the TXRDYpin willgotoa logic1 after the first
character is loaded into the transmit holding register.
Receive operation in mode ‘0’: When the SC16C554B/554DB is inmode‘0’ (FCR[0]= logic0),orin the FIFO mode (FCR[0]= logic1; FCR[3]=
logic 0) and there is at least one character in the receive FIFO, the RXRDY
pin will be a logic 0. Once active, the RXRDY pin will go to a logic 1 when
there are no more characters in the receiver.
Transmit operation in mode ‘1’: When the SC16C554B/554DB is in FIFOmode (FCR[0] = logic 1; FCR[3]= logic 1), the TXRDY pin will be a logic1
when the transmit FIFO is completely full. It will be a logic 0 if one or more
FIFO locations are empty.
Receive operation in mode ‘1’: When the SC16C554B/554DB is in FIFOmode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-out has occurred, the RXRDY pin will go to a
logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO. FCR[2] XMIT FIFO reset.
Logic 0 = No FIFO transmit reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO. FCR[1] RCVR FIFO reset.
Logic 0 = No FIFO receive reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO. FCR[0] FIFO enable.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO.
This bit must be a ‘1’
when other FCR bits are written to, or they will not be programmed.
