SC16C554BIB64 ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOsfeatures are the 16-byte receive and transmit FIFOs, four receive trigger levels. The SC16C554B/554 ..
SC16C554BIB80 ,SC16C554B/554DB; 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOsfeatures arethe 16-byte receive and transmit FIFOs, four receive trigger levels. TheSC16C554B/554DB ..
SC16C554BIBS ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOsLimiting values”.SC16C554B/554DBNXP Semiconductors5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) w ..
SC16C554DBIA68 ,SC16C554B/554DB; 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOsFeatures■ 4 channel UART■ 5 V, 3.3 V and 2.5 V operation■ Industrial temperature range (- 40 °C to ..
SC16C554DBIA68 ,SC16C554B/554DB; 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOsFeatures and benefits 4 channel UART 5 V, 3.3 V and 2.5 V operation Industrial temperature range ..
SC16C554DIA68 ,Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoderSC16C554/554DQuad UART with 16-byte FIFO and infrared (IrDA)encoder/decoderRev. 05 — 10 May 2004 Pr ..
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SC16C554BIB64-SC16C554BIBS-SC16C554DBIA68
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
1. General descriptionThe SC16C554B/554DB is a 4-channel Universal Asynchronous Receiver and
Transmitter (QUART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 5 Mbit/s. It comes with an Intel (16 mode) or Motorola (68 mode) interface.
The SC16C554B/554DB is pin compatible with the ST16C554 and TL16C554 and it will
power-up to be functionally equivalent to the 16C454. Programming of control registers
enables the added features of the SC16C554B/554DB. Some of these added features are
the 16-byte receive and transmit FIFOs, four receive trigger levels. The
SC16C554B/554DB also provides DMA mode data transfers through FIFO trigger levels
and the TXRDY and RXRDY signals. (TXRDY and RXRDY signals are not available in the
HVQFN48 package.) On-board status registers provide the user with error indications,
operational status, and modem interface control. System interrupts may be tailored to
meet user requirements. An internal loopback capability allows on-board diagnostics.
The SC16C554B/554DB operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature
range, and is available in plastic PLCC68, LQFP64, LQFP80, and HVQFN48 packages.
On the HVQFN48 package only, channel C has all the modem pins. Channels A and B
have only RTSn and CTSn pins and channel D does not have any modem pin.
2. Features and benefits 4 channel UART5 V, 3.3 V and 2.5 V operation Industrial temperature range (−40 °C to +85 °C) The SC16C554B is pin and software compatible with the industry-standard
ST16C454/554, ST68C454/554, ST16C554, TL16C554 The SC16C554DB is pin and software compatible with ST16C554D, and software
compatible with ST16C454/554, ST16C554, TL16C554 Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5V5 V tolerant on input only pins1 16-byte transmit FIFO 16-byte receive FIFO with error flags Programmable auto-RTS and auto-CTS In auto-CTS mode, CTS controls transmitter In auto-RTS mode, RX FIFO contents and threshold control RTS
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte
FIFOs
Rev. 4 — 8 June 2010 Product data sheet For data bus pins D7 to D0, see Table 24 “Limiting values”.
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Automatic hardware flow control (RTS/CTS) Software selectable baud rate generator Four selectable Receive FIFO interrupt trigger levels Standard modem interface Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break) Transmit, Receive, Line Status, and Data Set interrupts independently controlled Fully programmable character formatting: 5-bit, 6-bit, 7-bit, or 8-bit characters Even, odd, or no-parity formats 1, 11 ∨2, or 2-stop bit Baud generation (DC to 5 Mbit/s) False start-bit detection Complete status reporting capabilities 3-state output TTL drive capabilities for bidirectional data bus and control bus Line break generation and detection Internal diagnostic capabilities: Loopback controls for communications link fault isolation Prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, CD).
3. Ordering informationTable 1. Ordering informationSC16C554BIB64 LQFP64 plastic low profile quad flat package; 64 leads; body 10×10× 1.4 mm SOT314-2
SC16C554BIB80 LQFP80 plastic low profile quad flat package; 80 leads; body 12×12× 1.4 mm SOT315-1
SC16C554BIBM LQFP64 plastic low profile quad flat package; 64 leads; body 7×7× 1.4 mm SOT414-1
SC16C554BIBS HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; terminals; body 6×6× 0.85 mm
SOT778-3
SC16C554DBIA68 PLCC68 plastic leaded chip carrier; 68 leads SOT188-2
SC16C554DBIB64 LQFP64 plastic low profile quad flat package; 64 leads; body 10×10× 1.4 mm SOT314-2
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
4. Block diagramNXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
5. Pinning information
5.1 Pinning
5.1.1 PLCC68NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOsNXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
5.1.2 LQFP64NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
5.1.3 LQFP80NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
5.1.4 HVQFN48NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
5.2 Pin descriptionTable 2. Pin description16/68 31 - - 14 I
16/68 Interface type select (input with internal
pull-up). This input provides the 16 (Intel) or 68 (Motorola) bus interface type select. The functions of
IOR, IOW, INTAto INTD, and CSAto CSD are
re-assigned with the logic state of this pin. When this
pin is a logic 1, the 16 mode interface (16C554) is
selected. When this pin is a logic 0, the 68 mode
interface (68C554) is selected. When this pin is a
logic 0, IOW is re-assigned to R/W, RESET is
re-assigned to RESET, IOR is not used, and
INTAto INTD are connected in a wire-OR configuration.
The wire-OR outputs are connected internally to the
open-drain IRQ signal output. This pin is not available
on 64-pin packages which operate in the 16 mode only. 34 24 48 17 I
Address 0 select bit. Internal registers address selection in 16 and 68 modes. 33 23 47 16 I
Address 1 select bit. Internal registers address selection in 16 and 68 modes. 32 22 46 15 I
Address 2 select bit. Internal registers address selection in 16 and 68 modes. 20 - - 9 I
Address3to Address 4 select bits. When the 68 mode is selected, these pins are used to address or
select individual UARTs (providing CS is a logic 0). In
the 16 mode, these pins are re-assigned as chip
selects, see CSB and CSC. 50 - - 31 I
CDA 964 19 - I
Carrier Detect (active LOW). These inputs are associated with individual UART channels A through D.
A logic 0 on this pin indicates that a carrier has been
detected by the modem for that channel.
CDB 27 18 42 - I
CDC 43 31 59 24 I
CDD 61 49 2 - I 16 - - 5 I
Chip Select (active LOW). In the 68 mode, this pin functions as a multiple channel chip enable. In this
case, all four UARTs (Ato D) are enabled when the CS
pin is a logic 0. An individual UART channel is selected
by the data contents of address bits A3to A4. when the mode is selected (68-pin devices), this pin functions
as CSA (see definition under CSA, CSB).
CSA 16 7 28 5 I
Chip Select A, B, C, D (active LOW). This function is associated with the 16 mode only, and for individual
channels ‘A’ through ‘D’. When in 16 mode, these pins
enable data transfers between the user CPU and the
SC16C554B/554DB for the channel(s) addressed.
Individual UART sections (A, B, C, D) are addressed by
providing a logic 0 on the respective CSAto CSD pin.
When the 68 mode is selected, the functions of these
pins are re-assigned. 68 mode functions are described
under their respective name/pin headings.
CSB 20 11 33 9 I
CSC 50 38 68 31 I
CSD 54 42 73 35 I
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOsCTSA 11 2 23 1 I
Clear to Send (active LOW). These inputs are associated with individual UART channels Ato D. A
logic 0 on the CTSn pin indicates the modem or data
set is ready to accept transmit data from the
SC16C554B/554DB. Status can be tested by reading
MSR[4]. This pin only affects the transmit or receive
operations when auto-CTS function is enabled via
MCR[5] for hardware flow control operation.
CTSB 25 16 38 12 I
CTSC 45 33 63 26 I
CTSD 59 47 78 - I 66 53 7 39 I/O
Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from
the controlling CPU. D0 is the least significant bit and
the first data bit in a transmit or receive serial data
stream. 67 54 8 40 I/O 68 55 9 41 I/O 1 56 11 42 I/O 2 57 12 43 I/O 3 58 13 44 I/O 4 59 14 45 I/O 5 60 15 46 I/O
DSRA 10 1 22 - I
Data Set Ready (active LOW). These inputs are associated with individual UART channels, A through
D. A logic 0 on this pin indicates the modem or data set
is powered-on and is ready for data exchange with the
UART. This pin has no effect on the UART’s transmit or
receive operation.
DSRB 26 17 39 - I
DSRC 44 32 62 25 I
DSRD 60 48 79 - I
DTRA 12 3 24 - O
Data Terminal Ready (active LOW). These outputs are associated with individual UART channels, A
through D. A logic 0 on this pin indicates that the
SC16C554B/554DB is powered-on and ready. This pin
can be controlled via the Modem Control Register.
Writing a logic 1 to MCR[0] will set the DTRn output to
logic 0, enabling the modem. This pin will be a logic1
after writing a logic 0 to MCR[0], or after a reset. This
pin has no effect on the UART’s transmit or receive
operation.
DTRB 24 15 37 - O
DTRC 46 34 64 27 O
DTRD 58 46 77 - O
GND 6, 23,
40,57
14, 28,
45, 61
16, 36,
56, 76
21, 37, [1] I
Signal and power ground.INTA 15 6 27 4 O
Interrupt A, B, C, D (active HIGH). This function is associated with the 16 mode only. These pins provide
individual channel interrupts INTAto INTD.
INTAto INTD are enabled when MCR[3] is set to a
logic 1, interrupts are enabled in the Interrupt Enable
Register (IER), and when an interrupt condition exists.
Interrupt conditions include: receiver errors, available
receiver buffer data, transmit buffer empty, or when a
modem status flag is detected. When the 68 mode is
selected, the functions of these pins are re-assigned. mode functions are described under their respective
name/pin headings.
INTB 21 12 34 10 O
INTC 49 37 67 30 O
INTD 55 43 74 36 O
Table 2. Pin description …continued
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOsINTSEL 65 - 6 - I
Interrupt Select (active HIGH, with internal
pull-down). This function is associated with the mode only. When the 16 mode is selected, this pin
can be used in conjunction with MCR[3] to enable or
disable the 3-state interrupts, INTAto INTD, or override
MCR[3] and force continuous interrupts. Interrupt
outputs are enabled continuously by making this pin a
logic 1. Making this pin a logic 0 allows MCR[3] to
control the 3-state interrupt output. In this mode,
MCR[3] is set to a logic 1 to enable the 3-state outputs.
This pin is disabled in the 68 mode. Due to pin
limitations on the 64-pin packages, this pin is not
available. To cover this limitation, the
SC16C554DBIB64 version operates in the continuous
interrupt enable mode by bonding this pin to VCC
internally. The SC16C554BIB64 operates with MCR[3]
control by bonding this pin to GND. The INTSEL pin is
not available on the HVQFN48 package.
IOR 52 40 70 33 I
Input/Output Read strobe (active LOW). This function is associated with the 16 mode only. A logic0
transition on this pin will load the contents of an internal
register defined by address bits A0to A2 onto the
SC16C554B/554DB data bus (D0to D7) for access by
external CPU. This pin is disabled in the 68 mode.
IOW 18 9 31 7 I
Input/Output Write strobe (active LOW). This function is associated with the 16 mode only. A logic0
transition on this pin will transfer the contents of the
data bus (D0to D7) from the external CPU to an
internal register that is defined by address bits to A2. When the 68 mode is selected, this pin
functions as R/W (see definition under R/W).
IRQ 15 - - 4 O
Interrupt Request or Interrupt ‘A’. This function is associated with the 68 mode only. In the 68 mode,
interrupts from UART channels Ato D are wire-ORed
internally to function as a single IRQ interrupt. This pin
transitions to a logic 0 (if enabled by the Interrupt
Enable Register) whenever a UART channel(s)
requires service. Individual channel interrupt status can
be determined by addressing each channel through its
associated internal register, using CS and A3to A4. In
the 68 mode, and external pull-up resistor must be
connected between this pin and VCC. The function of
this pin changes to INTA when operating in the mode (see definition under INTA).
n.c. 21, 49,
52, 54,
55, 65 1, 10,
20, 21,
30, 40,
41, 49,
52, 60,
61, 71, - not connected
Table 2. Pin description …continued
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOsRESET
(RESET) 27 53 20 I
Reset. In the 16 mode, a logic 1 on this pin will reset
the internal registers and all the outputs. The UART
transmitter output and the receiver input will be
disabled during reset time. (See Section 7.10
“SC16C554B/554DB external reset conditions” for
initialization details.) When 16/68 is a logic0
(68 mode), this pin functions similarly, bus as an
inverted reset interface signal, RESET.
RIA 863 18 - I
Ring Indicator (active LOW). These inputs are associated with individual UART channels, Ato D. A
logic 0 on this pin indicates the modem has received a
ringing signal from the telephone line. A logic1
transition on this input pin will generate an interrupt.
RIB 28 19 43 - I
RIC 42 30 58 23 I
RID 62 50 3 - I
RTSA 14 5 26 3 O
Request to Send (active LOW). These outputs are associated with individual UART channels, Ato D. A
logic 0 on the RTSn pin indicates the transmitter has
data ready and waiting to send. Writing a logic 1 in the
Modem Control Register MCR[1] will set this pin to a
logic 0, indicating data is available. After a reset this pin
will be set to a logic 1. This pin only affects the transmit
and receive operations when auto-RTS function is
enabled via MCR[5] for hardware flow control
operation.
RTSB 22 13 35 11 O
RTSC 48 36 66 29 O
RTSD 56 44 75 - O
R/W 18 - - 7 I
Read/Write strobe. This function is associated with the mode only. This pin provides the combined functions
for Read or Write strobes.
Logic1= Read from UART register selected by CS and to A4.
Logic0= Write to UART register selected by CS and to A4.
RXA 7 62 17 48 I
Receive data input RXAto RXD. These inputs are associated with individual serial channel data to the
SC16C554B/554DB. The RXn signal will be a logic1
during reset, idle (no data), or when the transmitter is
disabled. During the local Loopback mode, the RXn
input pin is disabled and TX data is connected to the
UART RX input internally.
RXB 29 20 44 13 I
RXC 41 29 57 22 I
RXD 63 51 4 38 I
RXRDY 38 - 54 - O
Receive Ready (active LOW). RXRDY contains the wire-ORed status of all four receive channel FIFOs,
RXRDYAto RXRDYD. A logic 0 indicates receive data
ready status, that is, the RHR is full, or the FIFO has
one or more RX characters available for unloading.
This pin goes to a logic 1 when the FIFO/RHR is empty,
or when there are no more characters available in
either the FIFO or RHR. Individual channel RX status is
read by examining individual internal registers via CS
and A0to A4 pin functions. The RXRDY pin is not
available on the HVQFN48 package.
Table 2. Pin description …continued
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs[1] HVQFN48 package die supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
TXA 17 8 29 6 O
Transmit data A, B, C, D. These outputs are associated with individual serial transmit channel data
from the SC16C554B/554DB. The TX signal will be a
logic 1 during reset, idle (no data), or when the
transmitter is disabled. During the local Loopback
mode, the TXn output pin is disabled and TX data is
internally connected to the UART RX input.
TXB 19 10 32 8 O
TXC 51 39 69 32 O
TXD 53 41 72 34 O
TXRDY 39 - 55 - O
Transmit Ready (active LOW). TXRDY contains the wire-ORed status of all four transmit channel FIFOs,
TXRDYAto TXRDYD. A logic 0 indicates a buffer ready
status, that is, at least one location is empty and
available in one of the TX channels (Ato D). This pin
goes to a logic 1 when all four channels have no more
empty locations in the TX FIFO or THR. Individual
channel TX status can be read by examining individual
internal registers via CS and A0to A4 pin functions.
The TXRDY pin is not available on the HVQFN48
package.
VCC 13, 30,
47, 64
4, 21,
35, 52
5, 25,
45, 65
2, 28 I
Power supply inputs.XTAL1 35 25 50 18 I
Crystal or external clock input. Functions as a crystal input or as an external clock input. A crystal can be
connected between this pin and XTAL2 to form an
internal oscillator circuit (see Figure 13). Alternatively,
an external clock can be connected to this pin to
provide custom data rates. (See Section 6.6
“Programmable baud rate generator”.)
XTAL2 36 26 51 19 O
Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal oscillator output or buffered
clock output.
Table 2. Pin description …continued
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
6. Functional descriptionThe SC16C554B/554DB provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character. Data integrity is insured by attaching a parity bit to the data character. The
parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry
to provide all these functions is fairly complex, especially when manufactured on a single
integrated silicon chip. The SC16C554B/554DB represents such an integration with
greatly enhanced features. The SC16C554B/554DB is fabricated with an advanced
CMOS process to achieve low drain power and high speed requirements.
The SC16C554B/554DB is an upward solution that provides 16 bytes of transmit and
receive FIFO memory, instead of none in the 16C454. The SC16C554B/554DB is
designed to work with high speed modems and shared network environments that require
fast data processing time. Increased performance is realized in the SC16C554B/554DB
by the larger transmit and receive FIFOs. This allows the external processor to handle
more networking tasks within a given time. In addition, the four selectable levels of FIFO
trigger interrupt is uniquely provided for maximum data throughput performance,
especially when operating in a multi-channel environment. The combination of the above
greatly reduces the bandwidth requirement of the external controlling CPU, increases
performance, and reduces power consumption.
The SC16C554B/554DBAI68 combines the package interface modes of the 16C454/554
and 68C454/554 series on a single integrated chip. The 16 mode interface is designed to
operate with the Intel-type of microprocessor bus, while the 68 mode is intended to
operate with Motorola and other popular microprocessors. Following a reset, the
SC16C554B/554DBAI68 is downward compatible with the 16C454/554 or the
68C454/554, dependent on the state of the interface mode selection pin, 16/68.
The SC16C554B/554DB is capable of operation to 1.5 Mbit/s with a 24 MHz crystal and
up to 5 Mbit/s with an external clock input (at 3.3 V and 5 V; at 2.5 V the maximum speed
is 3 Mbit/s).
The rich feature set of the SC16C554B/554DB is available through internal registers.
Selectable receive FIFO trigger levels, selectable transmit and receive baud rates, and
modem interface controls are all standard features. In the 16 mode, INTSEL and MCR[3]
can be configured to provide a software controlled or continuous interrupt capability. Due
to pin limitations of the 64-pin package, this feature is offered by two different LQFP64
packages. The SC16C554DB operates in the continuous interrupt enable mode by
bonding INTSEL to VCC internally. The SC16C554B operates in conjunction with MCR[3]
by bonding INTSEL to GND internally.
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
6.1 Interface optionsTwo user interface modes are selectable for the PLCC68 package. These interface
modes are designated as the ‘16 mode’ and the ‘68 mode’. This nomenclature
corresponds to the early 16C454/554 and 68C454/554 package interfaces respectively.
6.1.1 The 16 mode interfaceThe 16 mode configures the package interface pins for connection as a standard series (Intel) device and operates similar to the standard CPU interface available on
the 16C454/554. In the 16 mode (pin 16/68 = logic 1), each UART is selected with
individual chip select (CSn) pins, as shown in Table3.
6.1.2 The 68 mode interfaceThe 68 mode configures the package interface pins for connection with Motorola, and
other popular microprocessor bus types. The interface operates similar to the
68C454/554. In this mode, the SC16C554B/554DB decodes two additional addresses, to A4, to select one of the four UART ports. The A3to A4 address decode function is
used only when in the 68 mode (16/68 = logic 0), and is shown in Table4.
Table 3. Serial port channel selection, 16 mode interface 11none 11A 11B 01C 10D
Table 4. Serial port channel selection, 68 mode interface n/a n/a none 0A 1B 0C 1D
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
6.2 Internal registersThe SC16C554B/554DB provides 12 internal registers for monitoring and control. These
registers are shown in Table 5. These registers function as data holding registers
(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO Control Register
(FCR), line status and control registers (LCR/LSR), modem status and control registers
(MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user
accessible Scratchpad Register (SPR). Register functions are more fully described in the
following paragraphs.
[1] These registers are accessible only when LCR[7] is a logic0.
[2] These registers are accessible only when LCR[7] is a logic1.
6.3 FIFO operationThe 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register
(FCR) bit 0. With SC16C554B devices, the user can set the receive trigger level, but not
the transmit trigger level. The receiver FIFO section includes a time-out function to ensure
data is delivered to the external CPU. An interrupt is generated whenever the Receive
Holding Register (RHR) has not been read following the loading of a character or the
receive trigger level has not been reached.
Table 5. Internal registers decoding
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)[1]000Receive Holding Register Transmit Holding Register
001Interrupt Enable Register Interrupt Enable Register
010Interrupt Status Register FIFO Control Register
011Line Control Register Line Control Register
100Modem Control Register Modem Control Register
101Line Status Register n/a
110Modem Status Register n/a
111Scratchpad Register Scratchpad Register
Baud rate register set (DLL/DLM)[2]000LSB of Divisor Latch LSB of Divisor Latch
001MSB of Divisor Latch MSB of Divisor Latch
Table 6. Flow control mechanism 4 1 8 4 12 8 14 14 10
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
6.4 Autoflow control (see Figure9)Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input
must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes
active when the receiver needs more data and notifies the sending serial device. When
RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has
space for the data; thus, overrun errors are eliminated using UART 1 and UART 2 from a
SC16C554B/554DB with the autoflow control enabled. If not, overrun errors occur when
the transmit data rate exceeds the receiver FIFO read latency.
6.4.1 Auto-RTS (see Figure9)Auto-RTS data flow control originates in the receiver timing and control block (see block
diagrams in Figure1 and Figure 2) and is linked to the programmed receiver FIFO trigger
level. When the receiver FIFO level reaches a trigger level of 1, 4, or 8 (see Figure 11),
RTS is de-asserted. With trigger levels of 1, 4, and 8, the sending UART may send an
additional byte after the trigger level is reached (assuming the sending UART has another
byte to send) because it may not recognize the de-assertion of RTS until after it has
begun sending the additional byte. RTS is automatically reasserted once the RX FIFO is
emptied by reading the receiver buffer register. When the trigger level is 14 (see
Figure 12), RTS is de-asserted after the first data bit of the 16th character is present on
the RX line. RTS is reasserted when the RX FIFO has at least one available byte space.
Remark: Auto-RTS is not supported in channel D of the HVQFN48 package, therefore
MCR[5] of channel D should not be written.
6.4.2 Auto-CTS (see Figure9)The transmitter circuitry checks CTS before sending the next data byte. When CTS is
active, it sends the next byte. To stop the transmitter from sending the following byte, CTS
must be released before the middle of the last stop bit that is currently being sent (see
Figure 10). The auto-CTS function reduces interrupts to the host system. When flow
control is enabled, CTS level changes do not trigger host interrupts because the device
automatically controls its own transmitter. Without auto-CTS, the transmitter sends any
data present in the transmit FIFO and a receiver overrun error may result.
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
Remark: Auto-CTS is not supported in channel D of the HVQFN48 package, therefore
MCR[5] of channel D should not be written.
6.4.3 Enabling autoflow control and auto-CTSAutoflow control is enabled by setting MCR[5] and MCR[1].
6.4.4 Auto-CTS and auto-RTS functional timingThe receiver FIFO trigger level can be set to 1 byte, 4 bytes, 8 bytes, or 14 bytes. These
are described in Figure 11 and Figure 12.
Table 7. Enabling autoflow control and auto-CTS 1 auto RTS and CTS 0 auto CTS X disable
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
6.5 Hardware/software and time-out interruptsFollowing a reset, if the transmitter interrupt is enabled, the SC16C554B/554DB will issue
an interrupt to indicate that the Transmit Holding Register is empty. This interrupt must be
serviced prior to continuing operations. The LSR register provides the current singular
highest priority interrupt only. Only after servicing the higher pending interrupt will the
lower priority interrupt(s) be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the
SC16C554B/554DB FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time-Out will not occur if the receive FIFO is empty. The time-out
counter is reset at the center of each stop bit received or each time the Receive Holding
Register (RHR) is read. The actual time-out value is 4 character time.
In the 16 mode for the PLCC68 package, the system/board designer can optionally
provide software controlled 3-state interrupt operation. This is accomplished by INTSEL
and MCR[3]. When INTSEL interface pin is left open or made a logic 0, MCR[3] controls
the 3-state interrupt outputs, INTAto INTD. When INTSEL is a logic 1, MCR[3] has no
effect on the INTAto INTD outputs, and the package operates with interrupt outputs
enabled continuously.
6.6 Programmable baud rate generatorThe SC16C554B/554DB supports high speed modem technologies that have increased
input data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate. 128.0 kbit/s ISDN modem that supports data compression may need an input data rate
of 460.8 kbit/s.
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOsA single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is capable
of accepting an input clock up to 80 MHz (for 3.3 V and 5 V operation), as required for
supporting a 5 Mbit/s data rate. The SC16C554B/554DB can be configured for internal or
external clock operation. For internal clock oscillator operation, an industry standard
microprocessor crystal (parallel resonant/22 pF to 33 pF load) is connected externally
between the XTAL1 and XTAL2 pins (see Figure 13). Alternatively, an external clock can
be connected to the XTAL1 pin to clock the internal baud rate generator for standard or
custom rates (see Table8).
Programming the Baud Rate Generator registers DLM (MSB) and DLL (LSB) provides a
user capability for selecting the desired final baud rate.
Table 8. Baud rate generator programming table using a 7.3728 MHz clock200 2304 900 09 00
1200 384 180 01 80
2400 192 C0 00 C0
4800 96 60 00 60
9600 48 30 00 30
19.2k 24 18 00 18
38.4k 12 0C 00 0C
76.8k 6 06 00 06
153.6k 3 03 00 03
230.4k 2 02 00 02
460.8k 1 01 00 01
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
6.7 DMA operationThe SC16C554B/554DB FIFO trigger level provides additional flexibility to the user for
block mode operation. LSR[6:5] provide an indication when the transmitter is empty or has
an empty location(s). The user can optionally operate the transmit and receive FIFOs in
the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA
mode is de-activated (DMA Mode 0), the SC16C554B/554DB activates the interrupt
output pin for each data transmit or receive operation. When DMA mode is activated
(DMA Mode 1), the user takes the advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the preset trigger level. In this
mode, the SC16C554B/554DB sets the interrupt output pin when the characters in the
receive FIFOs are above the receive trigger level.
Remark: DMA operation is not supported in the HVQFN48 package.
6.8 Loopback modeThe internal loopback capability allows on-board diagnostics. In the Loopback mode, the
normal modem interface pins are disconnected and reconfigured for loopback internally.
MCR[3:0] register bits are used for controlling loopback diagnostic testing. In the
Loopback mode, OP2 and OP1 in the MCR register (bits 3:2) control the modem RI and
CD inputs, respectively. MCR signals RTS and DTR (bits 1:0) are used to control the
modem CTS and DSR inputs, respectively. The transmitter output (TX) and the receiver
input (RX) are disconnected from their associated interface pins, and instead are
connected together internally (see Figure 14). The CTS, DSR, CD, and RI are
disconnected from their normal modem control input pins, and instead are connected
internally to RTS, DTR, OP2 and OP1. Loopback test data is entered into the Transmit
Holding Register via the user data bus interface, D0to D7. The transmit UART serializes
the data and passes the serial data to the receive UART via the internal loopback
connection. The receive UART converts the serial data back into parallel data that is then
made available at the user data interface D0to D7. The user optionally compares the
received data to the initial transmitted data for verifying error-free operation of the UART
TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read using
lower four bits of the Modem Status Register (MSR[3:0]) instead of the four Modem Status
Register bits 7:4. The interrupts are still controlled by the IER.
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOsNXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOsNXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOsNXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
7. Register descriptionsTable 9 details the assigned bit functions for the SC16C554B/554DB internal registers.
The assigned bit functions are more fully defined in Section 7.1 through Section 7.10.
[1] The value shown represents the register’s initialized hexadecimal value; X= not applicable.
[2] These registers are accessible only when LCR[7]=0.
[3] This function is not supported in the HVQFN48 package.
[4] Autoflow control is not supported by channel D of the HVQFN48 package, and this bit should not be written on channelD.
[5] The Special Register set is accessible only when LCR[7] is set to a logic1.
Table 9. SC16C554B/554DB internal registers
General Register set[2]
Special Register set[5]
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7to D0) to the
THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will
be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.
Note that a write operation can be performed when the THR empty flag is set
(logic0= FIFO full; logic1= at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C554B/554DB and receive FIFO by reading the
RHR register. The receive section provides a mechanism to prevent false starts. On the
falling edge of a start or false start bit, an internal receiver counter starts counting clocks at
the 16× clock rate. After 71 ∨2 clocks, the start bit time should be shifted to the center of the
start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTAto INTD output pins in the 16 mode, or on wire-OR IRQ output pin in the mode.
Table 10. Interrupt Enable Register bits description7:4 IER[7:4] Reserved; set to ‘0’. IER[3] Modem status interrupt.
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt IER[2] Receive line status interrupt.
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt IER[1] Transmit Holding Register interrupt. This interrupt will be issued whenever the THR is empty, and is associated with LSR[1].
logic 0 = disable the transmitter empty interrupt (normal default condition)
logic 1 = enable the transmitter empty interrupt IER[0] Receive Holding Register interrupt. This interrupt will be issued when the FIFO has reached the programmed trigger level, or is cleared when the FIFO drops
below the trigger level in the FIFO mode of operation.
logic 0 = disable the receiver ready interrupt (normal default condition)
logic 1 = enable the receiver ready interrupt
NXP Semiconductors SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
7.2.1 IER versus Receive FIFO interrupt mode operationWhen the receive FIFO (FCR[0]= logic 1), and receive interrupts (IER[0]= logic 1) are
enabled, the receive interrupts and register status will reflect the following:
The receive data available interrupts are issued to the external CPU when the FIFO
has reached the programmed trigger level. It will be cleared when the FIFO drops
below the programmed trigger level.
FIFO status will also be reflected in the user accessible ISR register when the FIFO
trigger level is reached. Both the ISR register status bit and the interrupt will be
cleared when the FIFO drops below the trigger level.
The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the FIFO is empty.
7.2.2 IER versus Receive/Transmit FIFO polled mode operationWhen FCR[0]= logic 1, resetting IER[3:0] enables the SC16C554B/554DB in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the
LSR, either or both can be used in the polled mode by selecting respective transmit or
receive control bit(s).
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[4:1] will provide the type of errors encountered, if any.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and Transmit Shift Register are
empty.
LSR[7] will indicate any FIFO data errors.
7.3 FIFO Control Register (FCR)This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
7.3.1 DMA mode
7.3.1.1 Mode 0 (FCR bit 3 = 0)Set and enable the interrupt for each single transmit or receive operation, and is similar to
the 16C454 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty
transmit space is available in the Transmit Holding Register (THR). Receive Ready
(RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with
a character.
7.3.1.2 Mode 1 (FCR bit 3 = 1)Set and enable the interrupt in a block mode operation. The transmit interrupt is set when
there are one or more FIFO locations empty. The receive interrupt is set when the receive
FIFO fills to the programmed trigger level. However, the FIFO continues to fill regardless
of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the
FIFO fill level is above the programmed trigger level.
