SC16C550BIA44 ,5 V, 3.3 V and 2.5 V UART with 16-byte FIFOsLimiting values”.SC16C550BNXP Semiconductors5 V, 3.3 V and 2.5 V UART with 16-byte FIFOsn Fully pro ..
SC16C550BIB48 ,5 V, 3.3 V and 2.5 V UART with 16-byte FIFOsSC16C550B5 V, 3.3 V and 2.5 V UART with 16-byte FIFOsRev. 05 — 1 October 2008 Product data sheet1.
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SC16C550BIA44-SC16C550BIB48
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
General descriptionThe SC16C550Bisa Universal Asynchronous Receiver and Transmitter (UART) usedfor
serial data communications. Its principal function is to convert parallel data into serial
data, and vice versa. The UART can handle serial data rates up to 3 Mbit/s.
The SC16C550Bis pin compatible with the ST16C550, TL16C550 and PC16C550, andit
will power-uptobe functionally equivalentto the 16C450. The SC16C550B also provides
DMA mode data transfers through FIFO trigger levels and the TXRDY and RXRDY signals
(TXRDY and RXRDY are not supported in the HVQFN32 package). On-board status
registers provide the user with error indications, operational status, and modem interface
control. System interrupts may be tailored to meet user requirements. An internal
loopback capability allows on-board diagnostics.
The SC16C550B operates at 5V , 3.3 V and 2.5 V, and the Industrial temperature range,
and is available in plastic HVQFN32, DIP40, PLCC44 and LQFP48 packages.
Features5V , 3.3 V and 2.5 V operation Industrial temperature range After reset, all registers are identical to the typical 16C450 register set Capable of running with all existing generic 16C450 software Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,
PC16C450/550 Upto3 Mbit/s transmit/receive operationat5V,2 Mbit/sat 3.3V, and1 Mbit/sat 2.5V5 V tolerant on input only pins1 16 byte transmit FIFO 16 byte receive FIFO with error flags Programmable auto-RTS and auto-CTS In auto-CTS mode, CTS controls transmitter In auto-RTS mode, RX FIFO contents and threshold control RTS Automatic hardware flow control Software selectable baud rate generator Four selectable Receive FIFO interrupt trigger levels Standard modem interface Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break) Independent receiver clock input Transmit, Receive, Line Status, and Data Set interrupts independently controlled
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Rev. 05 — 1 October 2008 Product data sheet For data bus pins D7 to D0, see Table 24 “Limiting values”.
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Fully programmable character formatting: 5, 6, 7, or 8-bit characters Even, odd, or no-parity formats 1, 11 ⁄2, or 2-stop bit Baud generation (up to 3 Mbit/s) False start-bit detection Complete status reporting capabilities 3-state output TTL drive capabilities for bidirectional data bus and control bus Line break generation and detection Internal diagnostic capabilities: Loopback controls for communications link fault isolation Prioritized interrupt system controls Modem control functions (CTS, RI, DCD, DSR, DTR, RTS)
Ordering information
Table 1. Ordering informationIndustrial: VDD= 2.5 V, 3.3 V or 5V±10 %; Tamb= −40 °C to +85 °C.
SC16C550BIA44 PLCC44 plastic leaded chip carrier; 44 leads SOT187-2
SC16C550BIBS HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; terminals; body 5×5× 0.85 mm
SOT617-1
SC16C550BIB48 LQFP48 plastic low profile quad flat package; 48 leads; body 7×7× 1.4 mm SOT313-2
SC16C550BIN40 DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Block diagram
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Pinning information
5.1 Pinning
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
5.2 Pin description
Table 2. Pin description 31 28 28 19 I
Register select. A2to A0 are used during read and write
operations to select the UART register to read from or
writeto. Referto Table3for register addresses and referto
AS description. 30 27 27 18 29 26 26 17 28 24 25 - I
Address strobe. When AS is active (LOW), A0, A1, and
A2 and CS0, CS1, and CS2 drive the internal select logic
directly; when AS is HIGH, the register select and chip
select signals are heldatthe logic levels they werein when
the LOW-to-HIGH transition of AS occurred.
BAUDOUT 17 12 15 - O
Baud out. BAUDOUT is a 16× clock signal for the
transmitter section of the UART. The clock rate is
established by the reference oscillator frequency divideda divisor specifiedinthe baud generator divisor latches.
BAUDOUT may also be used for the receiver section by
tying this output to RCLK. In HVQFN32 package
BAUDOUT and RCLK are bonded internally.
CS0[2] 14 9 12 - I
Chip select. When CS0 and CS1 are HIGH and CS2 is
LOW, these three inputs select the UART. When any of
these inputs are inactive, the UART remains inactive (refer AS description).
CS1[2] 15 10 13 -
CS2[2] 16 11 14 -[2] --- 8
CTS[2] 40 38 36 24 I
Clearto send. CTSisa modem status signal.Its condition
can be checked by reading bit 4 (CTS) of the Modem
Status Register.Bit0 (CTS)ofthe Modem Status Register
indicates that CTS has changed states since the last read
from the Modem Status Register. If the modem status
interrupt is enabled when CTS changes levels and the
auto-CTS mode is not enabled, an interrupt is generated.
This pin has no effect on the UART’s transmit or receive
operation.
D7 to D0 9, 8, 7,
6, 5, 4,
3, 2
4, 3, 2,
47, 46,
45, 44,
8, 7,
6, 5,
4, 3,
2, 1
5, 4, 3, 1,
32, 31,
30, 29
I/O
Data bus. Eight data lines with 3-state outputs provide abidirectional path for data, control and status information
between the UART and the CPU.
DCD[2] 42 40 38 26 I
Data carrier detect. DCD is a modem status signal. Its
condition can be checked by reading bit 7 (DCD) of the
Modem Status Register.Bit3 (DCD)of the Modem Status
Register indicates that DCD has changed states since the
last read from the Modem Status Register. If the modem
status interrupt is enabled when DCD changes levels, an
interrupt is generated.
DDIS 26 22 23 - O
Driver disable. DDIS is active (LOW) when the CPU is
reading data. When inactive (HIGH), DDIS can disable an
external transceiver.
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOsDSR[2] 41 39 37 25 I
Data set ready. DSR is a modem status signal. Its
condition can be checked by reading bit 5 (DSR) of the
Modem Status Register. Bit 1 (DSR) of the Modem Status
Register indicates DSR has changed levels since the last
read from the Modem Status Register.Ifthe modem status
interruptis enabled when DSR changes levels,an interrupt
is generated.
DTR 37 33 33 22 O
Data terminal ready. When active (LOW), DTR informs a
modem or data set that the UART is ready to establish
communication. DTRis placedin the active levelby setting
the DTRbitof the Modem Control Register. DTRis placed
in the inactive level either as a result of a Master Reset,
during loopback mode operation, or clearing the DTR bit.
INT 33 30 30 20 O
Interrupt. When active (HIGH), INT informs the CPU thatthe UART has an interrupt to be serviced. Four conditions
that cause an interrupt to be issued are: a receiver error,
received data that is available or timed out (FIFO mode
only), an empty Transmitter Holding Register or an
enabled modem status interrupt. INTis reset (deactivated)
either when the interrupt is serviced or as a result of a
Master Reset.
n.c. 1, 12,
23, 346, 13,
21, 25,
36, 37, 2, 15, 16 - not connected
OUT1 38 34 34 - O
Outputs 1 and 2. These are user-designated outputterminals that are set to the active (LOW) level by setting
respective Modem Control Register (MCR) bits (OUT1 and
OUT2). OUT1 and OUT2 are set to inactive the (HIGH)
level as a result of Master Reset, during loopback mode
operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of
the MCR.
OUT2 35 31 31 -
RCLK 10 5 9 - I
Receiver clock. RCLK is the 16× baud rate clock for the
receiver section of the UART. In the HVQFN32 package,
BAUDOUT and RCLK are bonded internally.
IOR 25 20 22 - I
Read inputs. When either IOR or IOR is active (LOW or
HIGH, respectively) while the UART is selected, the CPU
is allowed to read status information or data from a
selected UART register. Only one of these inputs is
required for the transfer of data during a read operation;
the other input should be tied to its inactive level (that is,
IOR tied LOW or IOR tied HIGH).
IOR[2] 24 19 21 14
RESET 39 35 35 23 I
Master reset. When active (HIGH), RESET clears mostUART registers and sets the levels of various output
signals.
Table 2. Pin description …continued
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs[2] 43 41 39 27 I
Ring indicator. RI is a modem status signal. Its condition
can be checked by reading bit 6 (RI) of the Modem Status
Register. Bit 2 (ΔRI) of the Modem Status Register
indicates thatRI has changed froma LOWtoa HIGH level
since the last read from the Modem Status Register. If the
modem status interrupt is enabled when this transition
occurs, an interrupt is generated.
RTS 36 32 32 21 O
Request to send. When active, RTS informs the modem
or data set that the UART is ready to receive data. RTS is
set to the active level by setting the RTS Modem Control
Registerbit andis settothe inactive (HIGH) level eitheras
a result of a Master Reset or during loopback mode
operations or by clearing bit 1 (RTS) of the MCR. This pin
has no effect on the UART’s transmit or receive operation.
RXRDY 322929 - O
Receiver ready. Receiver Direct Memory Access (DMA)signaling is available with RXRDY. When operating in the
FIFO mode, one of two types of DMA signaling can be
selected using the FIFO Control Register bit 3 (FCR[3]).
When operatinginthe 16C450 mode, only DMA mode0is
allowed. Mode 0 supports single-transfer DMA in which a
transfer is made between CPU bus cycles. Mode1
supports multi-transfer DMAin which multiple transfers are
made continuously until the receiver FIFO has been
emptied. In DMA mode 0 (FCR[0]= 0 or FCR[0]=1,
FCR[3]= 0), when there is at least one character in the
receiver FIFO or Receiver Holding Register, RXRDY is
active (LOW). When RXRDY has been activebut there are charactersin the FIFOor holding register, RXRDY goes
inactive (HIGH).In DMA mode1 (FCR[0]=1, FCR[3]=1),
when the trigger level or the time-out has been reached,
RXRDY goes active (LOW); when it has been active but
there are no more characters in the FIFO or holding
register, it goes inactive (HIGH). This function does not
exist in the HVQFN32 package. 11 7 10 6 I
Serial data input.RXis serial data input froma connected
communications device. 13 8 11 7 O
Serial data output.TXis composite serial data outputtoa
connected communication device.TXissetto the marking
(HIGH) level as a result of Master Reset.
TXRDY 272324 - O
Transmitter ready. Transmitter DMA signalingis available
with TXRDY. When operating in the FIFO mode, one of
two typesof DMA signaling canbe selected using FCR[3].
When operatinginthe 16C450 mode, only DMA mode0is
allowed. Mode 0 supports single-transfer DMA in which a
transfer is made between CPU bus cycles. Mode 1
supports multi-transfer DMAin which multiple transfers are
made continuously until the transmit FIFO has been filled.
This function does not exist in the HVQFN32 package.
VDD 44 42 40 28 power
2.5 V, 3.3 V or 5 V supply voltage.VSS 22 18 20 9, 13[1] power
Ground voltage.
Table 2. Pin description …continued
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs[1] HVQFN32 packagedie supply groundis connectedto boththe VSSpin andthe exposed center pad. The VSSpin mustbe connectedto
supply groundfor proper device operation.For enhanced thermal, electrical, and board-level performance,the exposed pad needstobe
soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the Printed-Circuit Board (PCB) in the thermal pad region.
[2] This pin has a pull-up resistor.
[3] In Sleep mode, XTAL2 is left floating.
Functional descriptionThe SC16C550B provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessaryfor converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character (character orientated protocol). Data integrityis insuredby attachinga paritybit
to the data character. The parity bit is checked by the receiver for any transmission bit
errors. The SC16C550B is fabricated with an advanced CMOS process to achieve low
drain power and high speed requirements.
The SC16C550B is an upward solution that provides 16 bytes of transmit and receive
FIFO memory, instead of none in the 16C450. The SC16C550B is designed to work with
high speed modems and shared network environments that require fast data processing
time. Increased performance is realized in the SC16C550B by the larger transmit and
receive FIFOs. This allows the external processorto handle more networking tasks within
a given time. In addition, the four selectable levels of FIFO trigger interrupt are provided
for maximum data throughput performance, especially when operating in a multi-channel
environment. The combinationof the above greatly reduces the bandwidth requirementof
the external controlling CPU, increases performance, and reduces power consumption.
The SC16C550Bis capableof operationupto3 Mbit/s witha48 MHz external clock input
(at 5 V).
IOW 211719 - I
Write inputs. When either IOW or IOW is active (LOW or
HIGH, respectively) and while the UART is selected, the
CPU is allowed to write control words or data into a
selected UART register. Only one of these inputs is
requiredto transfer data duringa write operation; the other
input should be tied to its inactive level (that is, IOW tied
LOW or IOW tied HIGH).
IOW[2] 20 16 18 12
XTAL1 18 14 16 10 I
Crystal connection or External clock input.XTAL2[3] 19 15 17 11 O
Crystal connectionor the inversionof XTAL1if XTAL1
is driven.
Table 2. Pin description …continued
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
6.1 Internal registersThe SC16C550B provides12 internal registersfor monitoring and control. These registers
are shown in Table 3. These registers function as data holding registers (THR/RHR),
interrupt status and control registers (IER/ISR),a FIFO Control Register (FCR), line status
and control registers (LCR/LSR), modem status and control registers (MCR/MSR),
programmable data rate (clock) control registers (DLL/DLM), and a user accessible
scratchpad register (SPR). Register functions are more fully described in the following
paragraphs.
[1] These registers are accessible only when LCR[7] is a logic 0.
[2] These registers are accessible only when LCR[7] is a logic 1.
6.2 FIFO operationThe 16-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
bit0 (FCR[0]). With 16C550 devices, the user can set the receive trigger level, but not the
transmit trigger level. The receiver FIFO section includes a time-out function to ensure
data is delivered to the external CPU. An interrupt is generated whenever the Receive
Holding Register (RHR) has not been read following the loading of a character or the
receive trigger level has not been reached.
Table 3. Internal registers decoding
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR/LSR, SPR)[1] 0 0 Receive Holding Register Transmit Holding Register 0 1 Interrupt Enable Register Interrupt Enable Register 1 0 Interrupt Status Register FIFO Control Register 1 1 Line Control Register Line Control Register 0 0 Modem Control Register Modem Control Register 0 1 Line Status Register n/a 1 0 Modem Status Register n/a 1 1 Scratchpad Register Scratchpad Register
Baud rate register set (DLL/DLM)[2] 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 1 MSB of Divisor Latch MSB of Divisor Latch
Table 4. Flow control mechanism 1 0 4 0 8 0 14 14 0
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
6.3 Autoflow controlAutoflow control is comprised of auto-CTS and auto-RTS (see Figure 6). With auto-CTS,
the CTS input must be active before the transmitter FIFO can emit data. With auto-RTS,
RTS becomes active when the receiver needs more data and notifies the sending serial
device. When RTS is connected to CTS, data transmission does not occur unless the
receiver FIFO has space for the data; thus, overrun errors are eliminated using UART1
and UART 2 from a SC16C550B with the autoflow control enabled. If not, overrun errors
occur when the transmit data rate exceeds the receiver FIFO read latency.
6.3.1 Auto-RTSAuto-RTS data flow control originates in the receiver timing and control block (refer to
Figure 1 “Block diagram of SC16C550B”) and is linked to the programmed receiver FIFO
trigger level (see Figure 6). When the receiver FIFO level reaches a trigger level of 1, 4, 8 (see Figure 8), RTS is de-asserted. With trigger levels of 1, 4, and 8, the sending
UART may send an additional byte after the trigger level is reached (assuming the
sending UART has another byteto send) becauseit may not recognize the de-assertionof
RTS until after it has begun sending the additional byte. RTS is automatically reasserted
once the RX FIFOis emptiedby reading the receiver buffer register. When the trigger level
is 14 (see Figure 9), RTS is de-asserted after the first data bit of the 16th character is
present on the RX line. RTS is reasserted when the RX FIFO has at least one available
byte space.
6.3.2 Auto-CTSThe transmitter circuitry checks CTS before sending the next data byte (see Figure6).
When CTS is active, it sends the next byte. To stop the transmitter from sending the
following byte, CTS mustbe released before the middleof the last stopbit thatis currently
being sent (see Figure 7). The auto-CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts because
the device automatically controls its own transmitter. Without auto-CTS, the transmitter
sends any data present in the transmit FIFO and a receiver overrun error may result.
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
6.3.3 Enabling autoflow control and auto-CTSAutoflow control is enabled by setting MCR[5] and MCR[1].
6.3.4 Auto-CTS and auto-RTS functional timingThe receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in
Figure 8 and Figure9.
Table 5. Enabling autoflow control and auto-CTS 1 auto RTS and CTS 0 auto CTS X disable
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
6.4 Hardware/software and time-out interruptsFollowing a reset, the transmitter interrupt is enabled, the SC16C550B will issue an
interrupt to indicate that the Transmit Holding Register is empty. This interrupt must be
serviced prior to continuing operations. The ISR register provides the current singular
highest priority interrupt only. Only after servicing the higher pending interrupt will the
lower priority be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC16C550B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive
Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the
centerof each stopbit receivedor each time the Receive Holding Register (RHR)is read.
The actual time-out value is 4 character time, including data information length, start bit,
parity bit, and the size of stop bit, that is, 1×, 1.5×, or 2× bit times.
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
6.5 Programmable baud rate generatorThe SC16C550B supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s modem
that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s
ISDN modem that supports data compression may needan input data rateof 460.8 kbit/s.
The SC16C550B can support a standard data rate of 921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable baud rate generatoris capableof
accepting an input clock up to 48 MHz, as required for supporting a 3 Mbit/s data rate.
The SC16C550B can be configured for internal or external clock operation. For internal
clock oscillator operation, an industry standard microprocessor crystal is connected
externally between the XTAL1 and XTAL2 pins (see Figure 10). Alternatively, an external
clock can be connected to the XTAL1 pin to clock the internal baud rate generator for
standard or custom rates (see Table6).
The generator divides the input 16× clock by any divisor from 1 to (216− 1). The
SC16C550B divides the basic crystal or external clock by 16. The frequency of the
BAUDOUT output pin is exactly 16× (16 times) the selected baud rate
(BAUDOUT=16× baud rate). Customized baud rates can be achieved by selecting the
proper divisor values for the MSB and LSB sections of the baud rate generator.
Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a
user capability for selecting the desired final baud rate. The examples inT able 6 shows
selectable baud rates when using a 1.8432 MHz crystal.
For custom baud rates, the divisor value can be calculated using the following equation:
(1)
divisor in decimal() XTAL1 clock frequency
serial data rate 16× ----------------------------------------------------------------=
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
6.6 DMA operationThe SC16C550B FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output
pins.T able 7 andT able 8 show this.
Remark: DMA operation is not supported in the HVQFN32 package.
Table 6. Baud rates using 1.8432 MHz or 3.072 MHz crystal
Table 7. Effect of DMA mode on state of RXRDY pin= FIFO empty 0-to-1 transition when FIFO empties= at least 1 byte in FIFO 1-to-0 transition when FIFO reaches trigger level, time-out occurs
Table 8. Effect of DMA mode on state of TXRDY pin= at least 1 byte in FIFO 1= FIFO is full= FIFO empty 0= FIFO is empty
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
6.7 Loopback modeThe internal loopback capability allows on-board diagnostics. In the loopback mode, the
normal modem interface pins are disconnected and reconfigured for loopback internally.
MCR[3:0] register bits are usedfor controlling loopback diagnostic testing.In the loopback
mode, OUT1 (bit2) and OUT2 (bit3)in the MCR register control the modemRI and DCD
inputs, respectively. MCR signals DTR and RTS (bits 0:1) are used to control the modem
CTS and DSR inputs, respectively. The transmitter output (TX) and the receiver input (RX)
are disconnected from their associated interface pins, and instead are connected together
internally (see Figure 11). The inputs CTS, DSR, DCD, and RI are disconnected from
their normal modem control input pins, and instead are connected internallyto DTR, RTS,
OUT1 and OUT2. Loopback test data is entered into the transmit holding register via the
user data bus interface, D0to D7. The transmit UART serializes the data and passes the
serial data to the receive UART via the internal loopback connection. The receive UART
converts the serial data back into parallel data thatis then made availableat the user data
interface D0to D7. The user optionally compares the received data to the initial
transmitted data for verifying error-free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can onlybe read using the
lower four bitsof the Modem Status Register (MSR[3:0]) insteadof the four Modem Status
Register bits 7:4. The interrupts are still controlled by the IER.
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Register descriptionsTable 9 details the assigned bit functions for the twelve SC16C550B internal registers.
The assigned bit functions are more fully defined in Section 7.1 through Section 7.10.
[1] The value shown represents the register’s initialized hexadecimal value; X= not applicable.
[2] These registers are accessible only when LCR[7] is set to a logic0.
[3] These functions are not supported in the HVQFN32 package, and should not be written.
[4] OUT2 pin is not supported in the HVQFN32 package.
[5] The Special Register set is accessible only when LCR[7] is set to a logic 1.
Table 9. SC16C550B internal registers
General Register Set[2]
Special Register Set[5]
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)The serial transmitter section consists of an 8-bit Transmit Holding Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D[7:0]) to the
THR, providing that the THRor TSRis empty. The THR empty flagin the LSR register will
be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.
Note that a write operation can be performed when the THR empty flag is set
(logic0= FIFO full; logic1= at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C550B and receive FIFO by reading the RHR
register. The receive section provides a mechanism to prevent false starts. On the falling
edge of a start or false start bit, an internal receiver counter starts counting clocks at the
16× clock rate. After 71 ⁄2 clocks, the start bit time should be shifted to the center of the
start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INT output pin.
Table 10. Interrupt Enable Register bits description7:4 IER[7:4] not used IER[3] Modem Status Interrupt.
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt IER[2] Receive Line Status interrupt. This interrupt will be issued whenever a fully
assembled receive character is transferred from RSR to the RHR/FIFO, that is,
data ready, LSR[0].
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt IER[1] Transmit Holding Register interrupt. This interrupt will be issued whenever the
THR is empty, and is associated with LSR[1].
logic 0 = disable the transmitter empty interrupt (normal default condition)
logic 1 = enable the transmitter empty interrupt IER[0] Receive Holding Register interrupt. This interrupt will be issued when the FIFO
has reached the programmed trigger level, or is cleared when the FIFO drops
below the trigger level in the FIFO mode of operation.
logic 0 = disable the receiver ready interrupt (normal default condition)
logic 1 = enable the receiver ready interrupt
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
7.2.1 IER versus Receive FIFO interrupt mode operationWhen the receive FIFO (FCR[0]= logic 1), and receive interrupts (IER[0]= logic 1) are
enabled, the receive interrupts and register status will reflect the following:
The receive data available interrupts are issued to the external CPU when the FIFO
has reached the programmed trigger level. It will be cleared when the FIFO drops
below the programmed trigger level.
FIFO status will also be reflected in the user accessible ISR register when the FIFO
trigger level is reached. Both the ISR register status bit and the interrupt will be
cleared when the FIFO drops below the trigger level.
The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the FIFO is empty.
7.2.2 IER versus Receive/Transmit FIFO polled mode operationWhen FCR[0]= logic 1, resetting IER[0:3] enables the SC16C550B in the FIFO polled
mode of operation. Since the receiver and transmitter have separate bits in the LSR,
either or both can be used in the polled mode by selecting respective transmit or receive
control bit(s).
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1:4] will provide the type of errors encountered, if any.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will indicate any FIFO data errors.
7.3 FIFO Control Register (FCR)This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
7.3.1 DMA mode(DMA mode does not exist in the HVQFN32 package; see Table9.)
7.3.1.1 Mode 0 (FCR bit 3 = 0)Set and enable the interruptfor each single transmitor receive operation, andis similarto
the 16C450 mode. T ransmit Ready (TXRDY) will go to a logic 0 whenever an empty
transmit space is available in the Transmit Holding Register (THR). Receive Ready
(RXRDY) willgotoa logic0 whenever the Receive Holding Register (RHR)is loaded with
a character.
7.3.1.2 Mode 1 (FCR bit 3 = 1)Set and enable the interruptina block mode operation. The transmit interruptis set when
the transmit FIFO is empty. The receive interrupt is set when the receive FIFO fills to the
programmed trigger level. However, the FIFO continues to fill regardless of the
programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill
level is above the programmed trigger level.
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
7.3.2 FIFO mode
Table 11. FIFO Control Register bits description7:6 FCR[7] (MSB),
FCR[6] (LSB)
RX trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to Table 12.
5:4 FCR[5] (MSB),
FCR[4] (LSB)
not used; set to 00 FCR[3] DMA mode select.
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C550B is in the16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0]= logic1; FCR[3]= logic0), and when there are
no characters in the transmit FIFO or transmit holding register, the
TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a
logic1 after the first characteris loaded into the transmit holding register.
Receive operation in mode ‘0’: When the SC16C550B is in 16C450mode,orinthe FIFO mode (FCR[0]= logic1; FCR[3]= logic0) and there
is at least one character in the receive FIFO, the RXRDY pin will be a
logic0. Once active,the RXRDYpin willgotoa logic1 when there areno
more characters in the receiver.
Transmit operation in mode ‘1’: When the SC16C550B is in FIFOmode (FCR[0] = logic 1; FCR[3]= logic 1), the TXRDY pin will be a
logic1 when the transmit FIFOis completely full.It willbea logic0if the
transmit FIFO is completely empty.
Receive operationin mode ‘1’: When the SC16C550Bisin FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-Out has occurred, the RXRDY pin will go to
a logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO. FCR[2] TX FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO. FCR[1] RX FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO. FCR[0] FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic1= enable the transmit and receive FIFO.
Thisbit mustbea‘1’
when other FCR bits are written to, or they will not be
programmed.
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
7.4 Interrupt Status Register (ISR)The SC16C550B provides four levelsof prioritized interruptsto minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is
cleared. However, it should be noted that only the current pending interrupt is cleared by
the read. A lower level interrupt may be seen after re-reading the interrupt status bits.
Table13 “Interrupt source” shows the data values (bits 3:0)for the four prioritized interrupt
levels and the interrupt sources associated with each of these interrupt levels.
Table 12. RX trigger levelsTable 13. Interrupt source 0 1 1 0 LSR (Receiver Line Status Register) 0 1 0 0 RXRDY (Received Data Ready) 1 1 0 0 RXRDY (Receive Data time-out) 0 0 1 0 TXRDY (Transmitter Holding Register Empty) 0 0 0 0 MSR (Modem Status Register)
Table 14. Interrupt Status Register bits description7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFOs are enabled.
logic 0 or cleared = default condition
5:4 ISR[5:4] not used
3:1 ISR[3:1] INT priority bits 2:0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see Table 13).
logic 0 or cleared = default condition ISR[0] INT status.
logic0=an interruptis pending and the ISR contents maybe usedas
a pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
7.5 Line Control Register (LCR)The Line Control Register is used to specify the asynchronous data communication
format. The word length, the numberof stop bits, and the parity are selectedby writing the
appropriate bits in this register.
Table 15. Line Control Register bits description LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhance
Feature mode enable.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch and enhanced feature register enabled LCR[6] Set break. When enabled, the Break control bit causes a break condition to transmitted (theTX outputis forcedtoa logic0 state). This condition exists
until disabled by setting LCR[6] to a logic0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition LCR[5] Set parity. If the parity bit is enabled, LCR[5] selects the forced parity format.
Programs the parity conditions (see Table 16).
logic 0 = parity is not forced (normal default condition)
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1 for
the transmit and receive data
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0 for
the transmit and receive data LCR[4] Even parity. If the parity bit is enabled with LCR[3] set to a logic 1, LCR[4]
selects the even or odd parity format.
logic0= odd parityis generatedby forcingan odd numberof logic1sinthe
transmitted data. The receiver must be programmed to check the same
format (normal default condition).
logic 1 = even parity is generated by forcing an even number of logic 1s in
the transmitted data. The receiver mustbe programmedto check the same
format. LCR[3] Parity enable. Parity or no parity can be selected via this bit.
logic 0 = no parity (normal default condition)
logic 1 = a parity bit is generated during the transmission, receiver checks
the data and parity for transmission errors LCR[2] Stop bits. The length of stop bit is specified by this bit in conjunction with the
programmed word length (see Table 17).
logic 0 or cleared = default condition
1:0 LCR[1:0] Word length bits [1:0]. These two bits specify the word length to be
transmitted or received (see Table 18).
logic 0 or cleared = default condition
NXP Semiconductors SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Table 16. LCR[5] parity selection X 0 no parity 0 1 odd parity
011even parity
101forced parity ‘1’
111forced parity ‘0’
Table 17. LCR[2] stop bit length 5, 6, 7, 8 1 11⁄2 6, 7, 8 2
Table 18. LCR[1:0] word length118
