SC16C2550BIA44-SC16C2550BIB48-SC16C2550BIBS Fast Delivery |IC PHOENIX CO.,LIMITED

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SC16C2550BIA44-SC16C2550BIB48-SC16C2550BIBS
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
General descriptionThe SC16C2550B is a two channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert parallel
data into serial data and vice versa. The UART can handle serial data ratesupto5 Mbit/s.
The SC16C2550B is pin compatible with the ST16C2550. It will power-up to be
functionally equivalent to the 16C2450. The SC16C2550B provides enhanced UART
functions with 16-byte FIFOs, modem control interface, DMA mode data transfer. The
DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDYn and
RXRDYn signals. On-board status registers provide the user with error indications and
operational status. System interrupts and modem control features may be tailored by
software to meet speciﬁc user requirements. An internal loopback capability allows
on-board diagnostics. Independent programmable baud rate generators are provided to
select transmit and receive baud rates.
The SC16C2550B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,
and is available in plastic PLCC44, LQFP48, DIP40 and HVQFN32 packages. Features 2 channel UART5V , 3.3 V and 2.5 V operation5 V tolerant on input only pins1 Industrial temperature range Pin and functionally compatible to 16C2450 and software compatible with INS8250,
SC16C550 Up to 5 Mbit/s data rate at 5 V and 3.3 V and 3 Mbit/s at 2.5V 16-byte transmit FIFO to reduce the bandwidth requirement of the external CPU 16-byte receive FIFO with error ﬂags to reduce the bandwidth requirement of the
external CPU Independent transmit and receive UART control Four selectable Receive FIFO interrupt trigger levels Software selectable baud rate generator Standard asynchronous error and framing bits (Start, Stop and Parity Overrun Break) Transmit, Receive, Line Status and Data Set interrupts independently controlled
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte
FIFOs
Rev. 05 — 12 January 2009 Product data sheet For data bus pins D7 to D0, see Table 23 “Limiting values”.
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Fully programmable character formatting: 5-bit, 6-bit, 7-bit or 8-bit characters Even, odd or no-parity formats 1, 11 ⁄2 or 2-stop bit Baud generation (DC to 5 Mbit/s) False start-bit detection Complete status reporting capabilities 3-state output TTL drive capabilities for bidirectional data bus and control bus Line break generation and detection Internal diagnostic capabilities: Loopback controls for communications link fault isolation Prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, DCD) Ordering information
3.1 Ordering options
Table 1. Ordering information
SC16C2550BIA44 PLCC44 plastic leaded chip carrier; 44 leads SOT187-2
SC16C2550BIBS HVQFN32 plastic thermal enhanced very thin quad ﬂat package; no leads; terminals; body 5×5× 0.85 mm
SOT617-1
SC16C2550BIB48 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads; body 7×7× 1.4 mm SOT313-2
SC16C2550BIN40 DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1
Table 2. Ordering options
SC16C2550BIA44 SC16C2550BIA44
SC16C2550BIBS 2550B
SC16C2550BIB48 16C2550B
SC16C2550BIN40 SC16C2550BIN40
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Block diagram
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Pinning information
5.1 Pinning
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
5.2 Pin description
Table 3. Pin description 19 28 31 28 I Address 0 select bit. Internal register address selection. 18 27 30 27 I Address 1 select bit. Internal register address selection. 17 26 29 26 I Address 2 select bit. Internal register address selection.
CSA 8 14 16 10 I Chip Select A, B (active LOW). This function is associated
with individual channels, A through B. These pins enable data
transfers between the user CPU and the SC16C2550B for the
channel(s) addressed. Individual UART sections (A, B) are
addressed by providing a logic 0 on the respective CSA, CSB
pin.
CSB 9 15 17 11 I 27 1 2 44 I/O Data bus (bidirectional). These pins arethe 8-bit, 3-state data
bus for transferring information to or from the controlling CPU.
D0 is the least signiﬁcant bit and the ﬁrst data bit in a transmit
or receive serial data stream. 28 2 3 45 I/O 29 3 4 46 I/O 30 4 5 47 I/O 31 5 6 48 I/O 32 6 7 1 I/O 1 7 8 2 I/O 2 8 9 3 I/O
GND 13 20 22 17 I Signal and power ground.
INTA 21 30 33 30 O Interrupt A, B (3-state). This function is associated with
individual channel interrupts, INTA, INTB. INTA, INTB are
enabled when MCR bit 3 is set to a logic 1, interrupts are
enabled in the Interrupt Enable Register (IER) and is active
whenan interrupt condition exists. Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer
empty or when a modem status ﬂag is detected.
INTB 20 29 32 29 O
IOR 14 21 24 19 I Read strobe (active LOW strobe). A logic 0 transition on this
pin will load the contents of an internal register deﬁned by
address bits A0to A2 onto the SC16C2550B data bus
(D0to D7) for access by external CPU.
IOW12 18 20 15 I Write strobe (active LOW strobe). A logic 0 transition on this
pin will transfer the contentsof the data bus (D0to D7) from the
external CPU to an internal register that is deﬁned by address
bits A0to A2.
OP2A 22 31 35 32 O Output 2 (user-deﬁned). This function is associated with
individual channels, A through B. The state at these pin(s) are
deﬁnedby the user and through MCR registerbit3. INTA, INTB
are set to the active mode and OP2 to logic 0 when MCR[3] is
set to a logic 1. INTA, INTB are set to the 3-state mode and
OP2 to a logic 1 when MCR[3] is set to a logic 0. See Table 18
“Modem Control Register bits description”, bit 3 (MCR[3]).
Since these bits control both the INTA, INTB operation and
OP2 outputs, only one function shouldbe usedat one time, INT OP2.
OP2B 7 13 15 9 O
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
RESET 24 35 39 36 I Reset (active HIGH).A logic1on thispin will resetthe internal
registers and all the outputs. The UART transmitter output and
the receiver input will be disabled during reset time. (See
Section 7.10 “SC16C2550B external reset condition” for
initialization details.)
RXRDYA- - 34 31 O Receive ReadyA,B (active LOW). This functionis associated
with PLCC44 and LQFP48 packages only. This function
provides the RX FIFO/RHR status for individual receive
channels (A-B). RXRDYn is primarily intended for monitoring
DMA mode 1 transfers for the receive data FIFOs. A logic0
indicates thereisa receive datato read/upload, thatis, receive
ready status with one or more RX characters available in the
FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty
or when the programmed trigger level has not been reached.
This signal can also be used for single mode transfers (DMA
mode0).
RXRDYB- - 23 18 O
TXRDYA- - 1 43 O Transmit Ready A, B (active LOW). This function is
associated with PLCC44 and LQFP48 packages only. These
outputs provide theTX FIFO/THR statusfor individual transmit
channels (A, B). TXRDYn is primarily intended for monitoring
DMA mode 1 transfers for the transmit data FIFOs. An
individual channel’s TXRDYA, TXRDYB buffer ready status is
indicated by logic 0, that is, at least one location is empty and
available in the FIFO or THR. This pin goes to a logic 1 (DMA
mode 1) when there are no more empty locations in the FIFO THR. This signal can alsobe usedfor single mode transfers
(DMA mode0).
TXRDYB- - 12 6 O
VCC 26 40 44 42 I Power supply input.
XTAL1 10 16 18 13 I Crystal or external clock input. Functions as a crystal input
or as an external clock input. A crystal can be connected
between this pin and XTAL2 to form an internal oscillator
circuit. Alternatively,an external clock canbe connectedto this
pin to provide custom data rates. (See Section 6.5
“Programmable baud rate generator”.) See Figure6.
XTAL2 11 17 19 14 O Outputof the crystal oscillatoror buffered clock. (See also
XTAL1.) Crystal oscillator output or buffered clock output.
Shouldbeleft openifan external clockis connectedto XTAL1.
For extended frequency operation, this pin should be tied to
VCC via a 2 kΩ resistor.
CDA - 38 42 40 I Carrier Detect (active LOW). These inputs are associated
with individual UART channels A through B. A logic 0 on this
pin indicates thata carrier has been detectedby the modemfor
that channel.
CDB - 19 21 16 I
CTSA 25 36 40 38 I Clearto Send (active LOW). These inputs are associated with
individual UART channels, A through B. A logic 0 on the CTSn
pin indicates the modemor data setis readyto accept transmit
data from the SC16C2550B. Status can be tested by reading
MSR[4]. This pin has no effect on the UART’s transmit or
receive operation.
CTSB 16 25 28 23 I
Table 3. Pin description …continued
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
DSRA - 37 41 39 I Data Set Ready (active LOW). These inputs are associated
with individual UART channels, A through B. A logic 0 on this
pin indicatesthe modemor datasetis powered-on andis ready
for data exchange with the UART. This pin hasno effecton the
UART’s transmit or receive operation.
DSRB - 22 25 20 I
DTRA - 33 37 34 O Data Terminal Ready (active LOW). These outputs are
associated with individual UART channels, A through B. logic 0 on this pin indicates that the SC16C2550B is
powered-on and ready. This pin can be controlled via the
Modem Control Register. Writing a logic 1 to MCR[0] will set
the DTRn output to logic 0, enabling the modem. This pin will
be a logic 1 after writing a logic 0 to MCR[0] or after a reset.
This pin has no effect on the UART’s transmit or receive
operation.
DTRB - 34 38 35 O
RIA - 39 43 41 I Ring Indicator (active LOW). These inputs are associated
with individual UART channels, A through B. A logic 0 on this
pin indicates the modem has receiveda ringing signal from the
telephone line.A logic1 transitionon this input pinwill generate
an interrupt.
RIB - 23 26 21 I
RTSA 23 32 36 33 O Requestto Send (active LOW). These outputs are associated
with individual UART channels, A through B. A logic 0 on the
RTSn pin indicates the transmitter has data ready and waiting
to send. Writing a logic 1 in the Modem Control Register
MCR[1] willset this pintoa logic0, indicating datais available.
After a reset this pin will be set to a logic 1. This pin has no
effect on the UART’s transmit or receive operation.
RTSB 15 24 27 22 O
RXA 4 10 11 5 I Receive dataA,B. These inputs are associated with individual
serial channel data to the SC16C2550B receive input circuits,
A and B. The RXn signal will be a logic 1 during reset, idle (no
data) or when the transmitter is disabled. During the local
Loopback mode, the RXn input pin is disabled and TX data is
connected to the UART RX input, internally.
RXB 3 9 10 4 I
TXA 5 11 13 7 O Transmit data A, B. These outputs are associated with
individual serial transmit channel data from the SC16C2550B.
The TXn signal will be a logic 1 during reset, idle (no data) or
when the transmitter is disabled. During the local Loopback
mode, the TXn output pin is disabled and TX data is internally
connected to the UART RX input.
TXB 6 12 14 8 O
n.c. - - - 12, 24,
25, 37 not connected
Table 3. Pin description …continued
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Functional description
The SC16C2550B provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessaryfor converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character (character orientated protocol). Data integrityis insuredby attachinga paritybit
to the data character. The parity bit is checked by the receiver for any transmission bit
errors. The electronic circuitry to provide all these functions is fairly complex, especially
when manufacturedona single integrated silicon chip. The SC16C2550B represents such
an integration with greatly enhanced features. The SC16C2550B is fabricated with an
advanced CMOS process.
The SC16C2550B is an upward solution that provides a dual UART capability with bytes of transmit and receive FIFO memory, instead of none in the 16C2450. The
SC16C2550B is designed to work with high speed modems and shared network
environments that require fast data processing time. Increased performanceis realizedin
the SC16C2550Bby the transmit and receive FIFOs. This allows the external processorto
handle more networking tasks withina given time. For example, the ST16C2450 withouta
receive FIFO, will require unloading of the RHR in 93 microseconds (this example uses a
character length of 11 bits, including start/stop bits at 115.2 kbit/s). This means the
external CPU will have to service the receive FIFO less than every 100 microseconds.
However, with the 16-byte FIFO in the SC16C2550B, the data buffer will not require
unloading/loadingfor 1.53 ms. This increases the service interval, giving the external CPU
additional time for other applications and reducing the overall UART interrupt servicing
time. In addition, the four selectable receive FIFO trigger interrupt levels are uniquely
provided for maximum data throughput performance especially when operating in a
multi-channel environment. The FIFO memory greatly reduces the bandwidth requirement
of the external controlling CPU, increases performance and reduces power consumption.
The SC16C2550B is capable of operation up to 5 Mbit/s with a 80 MHz clock. With a
crystal or external clock input of 7.3728 MHz, the user can select data rates up to
460.8 kbit/s.
The rich feature setof the SC16C2550Bis available through internal registers. Selectable
receive FIFO trigger levels, selectable TX and RX baud rates and modem interface
controls are all standard features. Following a power-on reset or an external reset, the
SC16C2550B is software compatible with the previous generation, ST16C2450.
6.1 UART A-B functions
The UART provides the user with the capability to bidirectionally transfer information
between an external CPU, the SC16C2550B package and an external serial device. A
logic 0 on chip select pins CSA and/or CSB allows the user to conﬁgure, send data,
and/or receive data via UART channels A through B. Individual channel select functions
are shown in Table4.
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.2 Internal registers
The SC16C2550B provides two sets of internal registers (A and B) consisting of registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shownin Table5. The UART registers functionas data holding
registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO Control
Register (FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM) anda
user-accessible Scratchpad Register (SPR).
[1] These registers are accessible only when LCR[7] is a logic0.
[2] These registers are accessible only when LCR[7] is a logic1.
Table 4. Serial port selection
CSA, CSB=1 none
CSA=0 UART channel A
CSB=0 UART channel B
Table 5. Internal registers decoding
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)[1] 0 0 Receive Holding Register Transmit Holding Register 0 1 Interrupt Enable Register Interrupt Enable Register 1 0 Interrupt Status Register FIFO Control Register 1 1 Line Control Register Line Control Register 0 0 Modem Control Register Modem Control Register 0 1 Line Status Register n/a 1 0 Modem Status Register n/a 1 1 Scratchpad Register Scratchpad Register
Baud rate register set (DLL/DLM)[2] 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 1 MSB of Divisor Latch MSB of Divisor Latch
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.3 FIFO operation
The 16-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
(FCR)bit0. The user can set the receive trigger level via FCR bits 7:6, but not the transmit
trigger level. The receiver FIFO section includes a time-out function to ensure data is
delivered to the external CPU. An interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the loading of a character or the receive
trigger level has not been reached.
6.4 Hardware/software and time-out interrupts
The interrupts are enabled by IER[3:0]. Care must be taken when handling these
interrupts. Followinga reset,if Interrupt Enable Register (IER) bit1=1, the SC16C2550B
will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to
continuing operations. The ISR register provides the current singular highest priority
interrupt only. A condition can exist where a higher priority interrupt may mask the lower
priority interrupt(s). Only after servicing the higher pending interrupt will the lower priority
interrupt(s) be reﬂected in the status register. Servicing the interrupt without investigating
further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC16C2550B
FIFO may hold more characters than the programmed trigger level. Following the removala data byte, the user should re-check LSR[0]for additional characters.A Receive Time
Out will not occur if the receive FIFO is empty. The time-out counter is reset at the center
of each stop bit received or each time the Receive Holding Register (RHR) is read. The
actual time-out valueis4 character time, including data information length, start bit, parity
bit and the size of stop bit, that is, 1×, 1.5× or 2× bit times.
Table 6. Flow control mechanism 14
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.5 Programmable baud rate generator
The SC16C2550B supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s modem
that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s
ISDN modem that supports data compression may needan input data rateof 460.8 kbit/s.
The SC16C2550B can support a standard data rate of 921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable baud rate generatoris capableof
operating witha frequencyofupto80 MHz.To obtain maximum data rate,itis necessary use full rail swingon the clock input. The SC16C2550B canbe conﬁguredfor internalor
external clock operation. For internal clock oscillator operation, an industry standard
microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins.
Alternatively, an external clock can be connected to the XT AL1 pin to clock the internal
baud rate generator for standard or custom rates (see Table 7).
The generator divides the input 16× clock by any divisor from 1 to (216− 1). The
SC16C2550B divides the basic external clock by 16. The basic 16× clock provides table
rates to support standard and custom applications using the same system design. The
rate tableis conﬁgured via the DLL and DLM internal register functions. Customized baud
rates can be achieved by selecting the proper divisor values for the MSB and LSB
sections of baud rate generator.
Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a
user capabilityfor selecting the desired ﬁnal baud rate. The examplein Table7 shows the
selectable baud rate table available when using a 1.8432 MHz external clock input.
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.6 DMA operation
The SC16C2550B FIFO trigger level provides additional ﬂexibility to the user for block
mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an
empty location(s). The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA
mode is de-activated (DMA Mode 0), the SC16C2550B activates the interrupt output pin
(INTn) for each data transmit or receive operation. When DMA mode is activated (DMA
Mode 1), the user takes the advantage of block mode operation by loading or unloading
the FIFO in a block sequence determined by the receive trigger level and the transmit
FIFO. In this mode, the SC16C2550B sets the TXRDYn (or RXRDYn) output pin when
characters in the transmit FIFO is below 16 or the characters in the receive FIFOs are
above the receive trigger level.
6.7 Loopback mode
The internal loopback capability allows on-board diagnostics. In the Loopback mode, the
normal modem interface pins are disconnected and reconﬁgured for loopback internally
(see Figure 7). MCR[3:0] register bits are usedfor controlling loopback diagnostic testing.
In the Loopback mode, the transmitter output (TX) and the receiver input (RX) are
disconnected from their associated interface pins and instead are connected together
internally. The CTS, DSR, CD and RI are disconnected from their normal modem control
input pins and instead are connected internally to RTS, DTR, MCR[3] (OP2) and MCR[2]
(OP1). Loopback test data is entered into the transmit holding register via the user data
bus interface, D0 through D7. The transmit UART serializes the data and passes the serial
data to the receive UART via the internal loopback connection. The receive UART
Table 7. Baud rate generator programming table using a 1.8432 MHz clock 2304 900 09 00 1536 600 06 00
110 1047 417 04 17
150 768 300 03 00
300 384 180 01 80
600 192 C0 00 C0
1200 96 60 00 60
2400 48 30 00 30
3600 32 20 00 20
4800 24 18 00 18
7200 16 10 00 10
9600 12 0C 00 0C
19.2k 6 06 00 06
38.4k 3 03 00 03
57.6k 2 02 00 02
115.2k 1 01 00 01
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
converts the serial data back into parallel data thatis then made availableat the user data
interface D0 through D7. The user optionally compares the received data to the initial
transmitted data for verifying error-free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The modem
control interrupts are also operational.
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Register descriptions
Table 8 details the assigned bit functions for the SC16C2550B internal registers. The
assigned bit functions are more fully deﬁned in Section 7.1 through Section 7.10.
[1] The value shown represents the register’s initialized hexadecimal value; X= not applicable.
[2] Accessible only when LCR[7] is logic0.
[3] Baud rate registers accessible only when LCR[7] is logic1.
7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writingto the THR transfers the contentsof the data bus (D7 through D0)
to the TSR and UART via the THR, providing that the THR is empty. The THR empty ﬂag
in the LSR register will be set to a logic 1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can be performed when the THR
empty ﬂag is set (logic0= at least one byte in FIFO/THR, logic1= FIFO/THR empty).
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive datais removed from the SC16C2550B and
receive FIFO by reading the RHR register. The receive section provides a mechanism to
Table 8. SC16C2550B internal registers
General register set[2]
Special register set[3]
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
prevent false starts. On the falling edge of a start or false start bit, an internal receiver
counter starts counting clocks at the 16× clock rate. After 71 ⁄2 clocks, the start bit time
should be shifted to the center of the start bit. At this time the start bit is sampled and if it
is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver
from assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTA, INTB output pins.
Table 9. Interrupt Enable Register bits description
7:4 IER[7:4] not used IER[3] Modem Status Interrupt. This interrupt will be issued whenever there is a
modem status change as reﬂected in MSR[3:0].
logic 0 = disable the Modem Status Register interrupt (normal default
condition)
logic 1 = enable the Modem Status Register interrupt IER[2] Receive Line Status interrupt. This interrupt will be issued whenever a
receive data error condition exists as reﬂected in LSR[4:1].
logic0= disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt IER[1] Transmit Holding Register interrupt. In the 16C450 mode, this interrupt will
be issued whenever the THR is empty and is associated with LSR[5]. In the
FIFO modes, this interrupt will be issued whenever the FIFO is empty.
logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt
(normal default condition)
logic 1 = enable the TXRDY (ISR level 3) interrupt IER[0] Receive Holding Register. In the 16C450 mode, this interrupt will be issued
when the RHR has data or is cleared when the RHR is empty. In the FIFO
mode, this interrupt will be issued when the FIFO has reached the
programmed trigger level or is cleared when the FIFO drops below the
trigger level.
logic0= disable the receiver ready (ISR level2, RXRDY) interrupt (normal
default condition)
logic 1 = enable the RXRDY (ISR level 2) interrupt
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation
When the receive FIFO (FCR[0]= logic 1) and receive interrupts (IER[0]= logic 1) are
enabled, the receive interrupts and register status will reﬂect the following: The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared
when the receive FIFO drops below the programmed trigger level. Receive FIFO status will also be reﬂected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit and
the interrupt will be cleared when the FIFO drops below the trigger level. The receive data ready bit (LSR[0]) is set as soon as a character is transferred from
the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty. When the Transmit FIFO and interrupts are enabled, an interrupt is generated when
the transmit FIFOis empty dueto the unloadingof the databy the TSR and UARTfor
transmission via the transmission media. The interruptis cleared eitherby reading the
ISR register or by loading the THR with new data characters.
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
When FCR[0]= logic 1, resetting IER[3:0] enables the SC16C2550B in the FIFO polled
mode of operation. In this mode, interrupts are not generated and the user must poll the
LSR register for TX and/or RX data status. Since the receiver and transmitter have
separate bits in the LSR either or both can be used in the polled mode by selecting
respective transmit or receive control bit(s). LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO. LSR[4:1] will provide the type of receive errors or a receive break, if encountered. LSR[5] will indicate when the transmit FIFO is empty. LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty. LSR[7] will show if any FIFO data errors occurred.
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels and select the DMA mode.
7.3.1 DMA mode
7.3.1.1 Mode 0 (FCR bit 3 = 0)
Set and enable the interrupt for each single transmit or receive operation and is similar to
the 16C450 mode. T ransmit Ready (TXRDYn) on PLCC44 and LQFP48 packages will go
to a logic 0 whenever the FIFO (THR, if FIFO is not enabled) is empty. Receive Ready
(RXRDYn) on PLCC44 and LQFP48 packages will go to a logic 0 whenever the Receive
Holding Register (RHR) is loaded with a character.
7.3.1.2 Mode 1 (FCR bit 3 = 1)
Set and enable the interruptina block mode operation. The transmit interruptis set when
the transmit FIFOis empty. TXRDYnon PLCC44 and LQFP48 packages remainsa logic0
as long as one empty FIFO location is available. The receive interrupt is set when the
receive FIFO ﬁlls to the programmed trigger level. However, the FIFO continues to ﬁll
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
regardless of the programmed level until the FIFO is full. RXRDY on PLCC44 and
LQFP48 packages transitions LOW when the FIFO reaches the trigger level and
transitions HIGH when the FIFO empties.
7.3.2 FIFO mode
Table 10. FIFO Control Register bits description
7:6 FCR[7:6] RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
logic 0 (or cleared) = normal default condition
logic 1 = RX trigger level
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continuetobe
loaded until it is full. Refer to Table 11.
5:4 FCR[5:4] Not used; initialized to logic0. FCR[3] DMA mode select.
logic 0 = set DMA mode ‘0’
logic 1 = set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C2550B is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0]= logic1; FCR[3]= logic0) and when there areno
charactersin the transmit FIFOor Transmit Holding Register, the TXRDYn
pin in PLCC44 or LQFP48 packages will be a logic 0. Once active, the
TXRDYn pin will go to a logic 1 after the ﬁrst character is loaded into the
Transmit Holding Register.
Receive operation in mode ‘0’: When the SC16C2550B is in mode‘0’
(FCR[0] = logic 0) or in the FIFO mode (FCR[3] = logic 0) and there is at
least one character in the receive FIFO, the RXRDYn pin will be a logic0.
Once active, the RXRDYn pin on PLCC44 and LQFP48 packages will go
to a logic 1 when there are no more characters in the receiver.
Transmit operation in mode ‘1’: When the SC16C2550B is in FIFO
mode (FCR[0] = logic 1; FCR[3]= logic 1), the TXRDYn pin on PLCC44
and LQFP48 packages will be a logic 1 when the transmit FIFO is
completely full. It will be a logic 0 if one or more FIFO locations are empty.
Receive operationin mode ‘1’: Whenthe SC16C2550Bisin FIFO mode
(FCR[0]= logic1; FCR[3]= logic1) and the trigger level has been reached
or a Receive Time-out has occurred, the RXRDYn pin on PLCC44 and
LQFP48 packages willgotoa logic0. Once activated,it willgotoa logic1
after there are no more characters in the FIFO. FCR[2] XMIT FIFO reset.
logic 0 = Transmit FIFO not reset (normal default condition).
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the Transmit Shift Register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.4 Interrupt Status Register (ISR)
The SC16C2550B provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged until
the pending interrupt is serviced. A lower level interrupt may be seen after servicing the
higher level interrupt and re-reading the interrupt status bits. Table 12 “Interrupt source”
shows the data values (bits 3:0) for the four prioritized interrupt levels and the interrupt
sources associated with each of these interrupt levels. FCR[1] RCVR FIFO reset.
logic 0 = Receive FIFO not reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the Receive Shift Register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO. FCR[0] FIFOs enabled.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’
when other FCR bits are written to or they will not be programmed.
Table 11. RCVR trigger levels
Table 10. FIFO Control Register bits description …continued
Table 12. Interrupt source 0 1 1 0 LSR (Receiver Line Status Register) 0 1 0 0 RXRDY (Received Data Ready) 1 1 0 0 RXRDY (Receive Data Time-out) 0 0 1 0 TXRDY (Transmitter Holding Register empty) 0 0 0 0 MSR (Modem Status Register)
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the numberof stop bits and the parity are selectedby writing the
appropriate bits in this register.
Table 13. Interrupt Status Register bits description
7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not
being used in the 16C450 mode. They are set to a logic 1 when the
FIFOs are enabled in the SC16C2550B mode.
logic 0 or cleared = default condition
5:4 ISR[5:4] not used
3:1 ISR[3:1] INT priority bits 2:0. These bits indicate the sourcefora pending interrupt
at interrupt priority levels 1, 2 and 3 (see Table 12).
logic 0 or cleared = default condition ISR[0] INT status.
logic0=an interruptis pending and the ISR contents maybe usedas
a pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
Table 14. Line Control Register bits description LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
logic0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled LCR[6] Set break. When enabled, the Break controlbit causesa break condition
to be transmitted (the TX output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
5:3 LCR[5:3] Programs the parity conditions (see Table 15) LCR[2] Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with
the programmed word length (see Table 16).
logic 0 or cleared = default condition
1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see Table 17).
logic 0 or cleared = default condition
Table 15. LCR[5:3] parity selection X 0 no parity 0 1 odd parity 1 1 even parity 0 1 forced parity ‘1’ 1 1 forced parity ‘0’
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 16. LCR[2] stop bit length 5, 6, 7, 8 1 11⁄2 6, 7, 8 2
Table 17. LCR[1:0] word length
Table 18. Modem Control Register bits description
7:5 MCR[7:5] reserved; set to ‘0’ MCR[4] Loopback. Enable the local Loopback mode (diagnostics).In this modethe
transmitter output (TX) and the receiver input (RX), CTS, DSR, CD andRI
are disconnected from the SC16C2550B I/O pins. Internally the modem
data and control pins are connected into a loopback data conﬁguration
(see Figure7).In this mode, the receiver and transmitter interrupts remain
fully operational. The Modem Control Interrupts are also operational, but
the interrupts’ sources are switched to the lower four bits of the Modem
Control. Interrupts continue to be controlled by the IER register.
logic 0 = disable Loopback mode (normal default condition)
logic 1 = enable local Loopback mode (diagnostics) MCR[3] OP2/INT enable
logic0= forces INT(A,B) outputsto the 3-state mode and sets OP2toa
logic 1 (normal default condition)
logic1= forces the INT(A,B outputsto the active mode and sets OP2to
a logic0 MCR[2] (OP1). OP1A/OP1B are not available as an external signal in the
SC16C2550B. This bit is instead used in the Loopback mode only. In the
Loopback mode, this bit is used to write the state of the modemRI
interface signal. MCR[1] RTS
logic0 = force RTS output to a logic 1 (normal default condition)
logic1= force RTS output to a logic0 MCR[0] DTR
logic0 = force DTR output to a logic 1 (normal default condition)
logic 1 = force DTR output to a logic0
NXP Semiconductors SC16C2550B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C2550B and
the CPU.
Table 19. Line Status Register bits description LSR[7] FIFO data error.
logic 0 = no error (normal default condition)
logic 1 = at least one parity error, framing error or break indication is in the
current FIFO data. This bit is cleared when there are no remaining error ﬂags
associated with the remaining data in the FIFO. LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a
logic 1 whenever the Transmit Holding Register and the T ransmit Shift Register
are both empty. It is reset to logic 0 whenever either the THR or TSR contains a
data character. In the FIFO mode, this bit is set to ‘1’ whenever the Transmit
FIFO and Transmit Shift Register are both empty. LSR[5] THR empty. This bit is the Transmit Holding Register Empty indicator. This bit
indicates that the UART is ready to accept a new character for transmission. In
addition, this bit causes the UART to issue an interrupt to CPU when the THR
interrupt enable is set. The THR bit is set to a logic 1 when a character is
transferred from the transmit holding register into the transmitter shift register.
The bit is reset to a logic 0 concurrently with the loading of the transmitter
holding register by the CPU. In the FIFO mode, this bit is set when the transmit
FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO. LSR[4] Break interrupt.
logic 0 = no break condition (normal default condition)
logic 1 = the receiver received a break signal (RX was a logic 0 for one
character frame time). In the FIFO mode, only one break character is loaded
into the FIFO. LSR[3] Framing error.
logic 0 = no framing error (normal default condition)
logic1= framing error. The receive character didnot havea valid stop bit(s).In
the FIFO mode, this error is associated with the character at the top of the
FIFO. LSR[2] Parity error.
logic 0 = no parity error (normal default condition
logic 1 = parity error. The receive character does not have correct parity
information andis suspect.In the FIFO mode, this erroris associated with the
character at the top of the FIFO. LSR[1] Overrun error.
logic0 = no overrun error (normal default condition)
logic1= overrun error. A data overrun error occurred in the Receive Shift
Register. This happens when additional data arrives while the FIFO is full. In
this case, the previous datain the shift registeris overwritten. Note that under
this condition, the data bytein the Receive Shift Registerisnot transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.

Partno	Mfg	Dc	Qty	Available	Descript
SC16C2550BIA44	PHLIPS	N/a	1723	avai	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
SC16C2550BIA44	PHILIS	N/a	79	avai	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
SC16C2550BIB48	NXP	N/a	2500	avai	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
SC16C2550BIBS	PHI	N/a	50	avai	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs