SAF7118H ,Multistandard video decoder with adaptive comb filter and component video inputTHERMAL CHARACTERISTICS1.3 Component video processing1.4 Video scaler13 CHARACTERISTICS1.5 Vertical ..
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SAF7118EH-SAF7118H
Multistandard video decoder with adaptive comb filter and component video input
Philips Semiconductors Product specification
Multistandard video decoder with adaptive
comb filter and component video input SAF7118
CONTENTS FEATURES
1.1 Video acquisition/clock
1.2 Video decoder
1.3 Component video processing
1.4 Video scaler1.5 Vertical Blanking Interval (VBI) data decoder
and slicer
1.6 Audio clock generation
1.7 Digital I/O interfaces
1.8 Miscellaneous APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION
8.1 Decoder
8.2 Component video processing
8.3 Decoder output formatter
8.4 Scaler
8.5 VBI data decoder and capture(subaddresses 40Hto 7FH)
8.6 Image port output formatter
(subaddresses 84Hto 87H)
8.7 Audio clock generation
(subaddresses 30Hto 3FH) INPUT/OUTPUT INTERFACES AND PORTS
9.1 Analog terminals
9.2 Audio clock signals
9.3 Clock and real-time synchronization signals
9.4 Interrupt handling9.5 Video expansion port (X port)
9.6 Image port (I port)
9.7 Host portfor 16-bit extensionof video data I/O port)
9.8 Basic input and output timing diagrams I portand X port BOUNDARY SCAN TEST
10.1 Initialization of boundary scan circuit
10.2 Device identification codes LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS APPLICATION INFORMATION I2C-BUS DESCRIPTION
15.1 I2 C-bus format
15.2 I2 C-bus details15.3 Programming register RGB/Y-PB-PR
component input processing
15.4 Interrupt mask registers
15.5 Programming register audio clock generation
15.6 Programming register VBI data slicer15.7 Programming register interfaces and scaler
part PROGRAMMING START SET-UP
16.1 Decoder part
16.2 Component video part and interrupt mask
16.3 Audio clock generation part16.4 Data slicer and data type control part
16.5 Scaler and interfaces PACKAGE OUTLINES SOLDERING
18.1 Introduction to soldering surface mount
packages
18.2 Reflow soldering
18.3 Wave soldering18.4 Manual soldering
18.5 Suitability of surface mount IC packages for
wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2 C COMPONENTS
Philips Semiconductors Product specification
Multistandard video decoder with adaptive
comb filter and component video input SAF7118
FEATURES
1.1 Video acquisition/clock Up to sixteen analog CVBS, split as desired (all of the
CVBS inputs optionally can be used to convert e.g.
Vestigial Side Band (VSB) signals) Up to eight analog Y+ C inputs, split as desired Upto four analog component inputs, with embeddedor
separate sync, split as desired Four on-chip anti-aliasing filters in front of the
Analog-to-Digital Converters (ADCs) Automatic Clamp Control (ACC) for CVBS, Y andC(or VSB) and component signals Switchable white peak control Four 9-bit low noise CMOS ADCs running at twice the
oversampling rate (27 MHz) Fully programmable static gain or Automatic Gain
Control (AGC), matching to the particular signal
properties On-chip line-locked clock generationin accordance with
“ITU 601” Requires only one crystal (32.11or 24.576 MHz)forall
standards Horizontal and vertical sync detection.
1.2 Video decoder Digital PLL for synchronization and clock generation
fromall standards and non-standard video sources e.g.consumer grade VTR Automatic detection of any supported colour standard Luminance and chrominance signal processing for
PAL B, G, D, H, I and N, combination PAL N, PALM,
NTSC M, NTSC-Japan, NTSC 4.43 and SECAM Adaptive 2/4-line comb filter for two dimensional
chrominance/luminance separation, also with VTR
signals Increased luminance andchrominance bandwidthfor
all PAL and NTSC standards Reduced cross colour and cross luminance artefacts PAL delay line for correcting PAL phase errors Brightness Contrast Saturation (BCS) adjustment,
separately for composite and baseband signals User programmable sharpness control Detection of copy-protected signals according to the
Macrovision(1) standard, indicating level of protection Independent gain and offset adjustment for raw data
path.
1.3 Component video processing RGB component inputs Y-PB-PR component inputs Fast blanking between CVBS and synchronouscomponent inputs Digital RGB to Y-CB-CR matrix.
1.4 Video scaler Horizontal and vertical downscaling and upscaling to
randomly sized windows Horizontal and vertical scaling range: variable zoom to⁄64 (icon)(it shouldbe noted that theH andV zoom are
restricted by the transfer data rates) Anti-alias and accumulating filter for horizontal scaling Vertical scaling with linear phase interpolation and
accumulating filter for anti-aliasing (6-bit phase
accuracy) Horizontal phase correct up and downscaling for
improved signal quality of scaled data, especially for
compression and video phone applications, with 6-bit
phase accuracy (1.2 ns step width) Two independent programming sets for scaler part, to
define two ‘ranges’ per field or sequences over frames Fieldwise switching between decoder part and
expansion port (X port) input Brightness, contrast and saturation controls for scaled
outputs.
1.5 Vertical Blanking Interval (VBI) data decoder
and slicer Versatile VBI data decoder, slicer, clock regeneration
and byte synchronization e.g. for World Standard
Teletext (WST), North American Broadcast Text System
(NABTS), closed caption, Wide Screen Signalling
(WSS), etc.
(1) Macrovision is a registered trademark of the Macrovision
Corporation.
Philips Semiconductors Product specification
Multistandard video decoder with adaptive
comb filter and component video input SAF7118
1.6 Audio clock generation Generation of a field-locked audio master clock to
support a constant number of audio clocks per video
field Generation of an audio serial and left/right (channel)
clock signal.
1.7 Digital I/O interfaces Real-time signal port (R port), inclusive continuous
line-locked reference clock and real-time status
information supporting RTC level 3.1 (referto document
“RTC Functional Specification” for details) Bidirectional expansion port (X port) with half duplex
functionality (D1), 8-bit Y-CB-CR: Output from decoder part, real-time and unscaled Input to scaler part, e.g. video from MPEG decoder(extension to 16-bit possible) Video image port (I port) configurable for 8-bit data
(extension to 16-bit possible) in master mode (ownclock), or slave mode (external clock), with auxiliary
timing and handshake signals Discontinuous data streams supported 32-word× 4-byte FIFO register for video output data 28-word× 4-byte FIFO register for decoded VBI data
output Scaled 4:2: 2, 4:1: 1, 4:2: 0, 4:1: 0 Y-CB-CR
output Scaled 8-bit luminance only and raw CVBS data output Sliced, decoded VBI data output.
1.8 Miscellaneous Power-on control5 V tolerant digital inputs and I/O ports Software controlled power saving standby modes
supported Programming via serialI2 C-bus, full read back abilityby
an external controller, bit rate up to 400 kbit/s Boundary scan test circuit complies with the “IEEE Std.
1149.b1- 1994”.
APPLICATIONS PC-video capture and editing Personal video recorders (time shifting) Cable, terrestrial, and satellite set-top boxes Internet terminals Flat-panel monitors DVD recordable players AV-ready hard-disk drivers Digital televisions/scan conversion Video surveillance/security Video editing/post production Video phones Video projectors Digital VCRs.
GENERAL DESCRIPTIONThe SAF7118isa video capture devicefor applicationsatthe image port of VGA controllers.
Philips X-VIP is a new multistandard comb filter video
decoder chip with additional component processing,
providing high quality, optionally scaled, video.
The SAF7118 is a combination of a four-channel analog
preprocessing circuit including source selection,
anti-aliasing filter and ADC with succeeding decimation
filters from27to 13.5 MHz data rate. Each preprocessing
channel comes withan automatic clamp and gain control.The SAF7118 combines a Clock Generation Circuit
(CGC), a digital multistandard decoder containing
two-dimensional chrominance/luminanceseparationbyan
adaptive comb filter and a high performance scaler,
including variable horizontal and vertical up and downscaling and a brightness, contrast and saturation
control circuit.
Philips Semiconductors Product specification
Multistandard video decoder with adaptive
comb filter and component video input SAF7118isa highly integrated circuitfor desktop video and similarapplications. The decoder is based on the principle of
line-locked clockdecoding andis ableto decode the colour
of PAL, SECAM and NTSC signals into ITU 601
compatible colour component values. The SAF7118
accepts CVBSor S-video (Y/C)as analog inputs fromTVor VCR sources, including weak and distorted signals as
wellas baseband component signals Y-PB-PRor RGB.An
expansion port (X port) for digital video (bidirectional half
duplex, D1 compatible) is also supported to connect to
MPEGora video phone codec.At theso called image port(I port) the SAF7118 supports8or 16-bit wide output data
with auxiliary reference data for interfacing to VGA
controllers.
The target application for the SAF7118 is to capture and
scale video images, to be provided as a digital videostream through the image port of a VGA controller, for
capture to system memory, or just to provide digital
baseband video to any picture improvement processing.
The SAF7118 also provides a means for capturing theserially coded data in the vertical blanking interval (VBI
data). Two principal functions are available: To capture raw video samples, after interpolation tothe required output data rate, via the scaler A versatile data slicer (data recovery) unit.
The SAF7118 also incorporates field-locked audio clock
generation. This function ensures that thereis always the
same numberof audio samples associated witha field,or
a set of fields. This prevents the loss of synchronization
between video and audio during capture or playback.
All of the ADCs may be used to digitize a VSB signal for
subsequent decoding; a dedicated output port and a
selectable VSB clock input is provided.
The circuit is I2 C-bus controlled (full write/read capabilityfor all programming registers, bit rate up to 400 kbit/s).
QUICK REFERENCE DATA
Note Power dissipationis measuredin component mode (four ADCs active) and 8-bit image port output mode, expansion
port is 3-stated.
ORDERING INFORMATION
