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SAF1761BE
Hi-Speed Universal Serial Bus On-The-Go controller
1. General descriptionThe SAF1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG)
Controller integrated with advanced NXP slave host controller and the peripheral
controller.
The Hi-Speed USB host controller and peripheral controller comply to Ref. 1 “Universal
Serial Bus Specification Rev. 2.0” and support data transfer speeds of up to 480 Mbit/s.
The Enhanced Host Controller Interface (EHCI) core implemented in the host controller is
adapted from Ref. 2 “Enhanced Host Controller Interface Specification for Universal Serial
Bus Rev. 1.0”. The OTG controller adheres to Ref. 3 “On-The-Go Supplement to the USB
Specification Rev. 1.3”.
The SAF1761 has three USB ports. Port 1 can be configured to function as a downstream
port, an upstream port or an OTG port; ports 2 and 3 are always configured as
downstream ports. The OTG port can switch its role from host to peripheral, and
peripheral to host. The OTG port can become a host through the Host Negotiation
Protocol (HNP) as specified in the OTG supplement.
2. Features and benefits Automotive qualified in accordance with AEC-Q100 Compliant with Ref. 1 “Universal Serial Bus Specification Rev. 2.0”; supporting data
transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) Integrated Transaction Translator (TT) for original USB (full-speed and low-speed)
peripheral support Three USB ports that support three operational modes: Mode 1: Port 1 is an OTG controller port, and ports 2 and 3 are host controller ports Mode 2: Ports 1, 2 and 3 are host controller ports Mode 3: Port 1 is a peripheral controller port, and ports 2 and 3 are host controller
ports Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) Multitasking support with virtual segmentation feature (up to four banks) High-speed memory controller (variable latency and SRAM external interface) Directly addressable memory architecture Generic processor interface to most CPUs, such as Hitachi SH-3 and SH-4, NXP XA,
Intel StrongARM, NEC and Toshiba MIPS, Freescale DragonBall and PowerPC
Reduced Instruction Set Computer (RISC) processors Configurable 32-bit and 16-bit external memory data bus Supports Programmed I/O (PIO) and Direct Memory Access (DMA) Slave DMA implementation on CPU interface to reduce the host systems CPU load
SAF1761
Hi-Speed Universal Serial Bus On-The-Go controller
Rev. 2 — 19 June 2012 Product data sheet
NXP Semiconductors SAF1761
Hi-Speed USB OTG controller Separate IRQ, DREQ and DACK lines for the host controller and the peripheral
controller Integrated multi-configuration FIFO Double-buffering scheme increases throughput and facilitates real-time data transfer Integrated Phase-Locked Loop (PLL) with external 12 MHz crystal for low
ElectroMagnetic Interference (EMI)T olerant I/O for low voltage CPU interface (1.65 V to 3.3V) 3.3 V-to-5.0 V external power supply input Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for
low-power core) Internal power-on reset or low-voltage reset and block-dedicated software reset Supports suspend and remote wake-up Built-in overcurrent circuitry (analog overcurrent protection) Hybrid-power mode: VCC(5V0) (can be switched off), VCC(I/O) (permanent)T arget total current consumption: Normal operation; one port in high-speed active: ICC < 100 mA when the internal
charge pump is not used Suspend mode: ICC(susp) < 150 μA at ambient temperature of +25°C Host controller-specific features High performance USB host with integrated Hi-Speed USB transceivers; supports
high-speed, full-speed and low-speed EHCI core is adapted from Ref. 2 “Enhanced Host Controller Interface
Specification for Universal Serial Bus Rev. 1.0” Configurable power management Integrated TT for Original USB peripheral support on all three ports Integrated 64 kB high-speed memory (internally organized as 8k × 64 bit) Additional 2.5 kB separate memory for TT Individual or global overcurrent protection with built-in sense circuits Built-in overcurrent circuitry (digital or analog overcurrent protection) OTG controller-specific features OTG transceiver: fully integrated; adheres to Ref. 3 “On-The-Go Supplement to the
USB Specification Rev. 1.3” Supports HNP and SRP for OTG dual-role devices HNP: status and control registers for software implementation SRP: status and control registers for software implementation Programmable timers with high resolution (0.01 ms to 80 ms) for HNP and SRP Supports external source of VBUS Peripheral controller-specific features High-performance USB peripheral controller with integrated Serial Interface Engine
(SIE), FIFO memory and transceiver Complies with Ref. 1 “Universal Serial Bus Specification Rev. 2.0” and most device
class specifications Supports auto Hi-Speed USB mode discovery and Original USB fallback
capabilities Supports high-speed and full-speed on the peripheral controller Bus-powered or self-powered capability with suspend mode
NXP Semiconductors SAF1761
Hi-Speed USB OTG controller Slave DMA, fully autonomous and supports multiple configurations Seven IN endpoints, seven OUT endpoints and one fixed control IN and OUT
endpoint Integrated 8 kB memory Software-controllable connection to the USB bus, SoftConnect
3. ApplicationsThe SAF1761 can be used to implement a dual-role USB device, USB host or USB
peripheral, depending on the cable connection. If the dual-role device is connected to a
typical USB peripheral, it behaves like a typical USB host. The dual-role device can also
be connected to a PC or any other USB host and behave like a typical USB peripheral.
This NXP USB product can only be used in automotive applications. Inclusion or use of
the NXP USB products in other than automotive applications is not permitted and for your
company’s own risk. Your company agrees to full indemnify NXP for any damages
resulting from such inclusion or use.
4. Ordering informationTable 1. Ordering informationSAF1761BE LQFP128 plastic low profile quad flat package; 128 leads; body 14 × 20 × 1.4 mm SOT425-1
NXP Semiconductors SAF1761
Hi-Speed USB OTG controller
5. Block diagramNXP Semiconductors SAF1761
Hi-Speed USB OTG controller
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin descriptionOC3_N 1 AI/I port 3 analog (5 V input) and digital overcurrent input; if not used, connect to
VCC(I/O) through a 10 kΩ resistor
input, 5 V tolerant
REF5V 2 AI 5 V reference input for analog OC detector; connect a 100 nF decoupling capacitor 3 I ID input to detect the default host or peripheral setting when port 1 is in OTG mode;
pull-up to 3.3 V through a 4.7 kΩ resistor
input, 3.3 V tolerant
GNDA 4 G analog ground
REG1V8 5 P core power output (1.8 V); internal 1.8 V for the digital core; used for decoupling;
connect a 100 nF capacitor; for details on additional capacitor placement, see
Section7.8
VCC(5V0) 6 P input to internal regulators (3.0 V-to-5.5 V); connect a 100 nF decoupling capacitor;
see Section 7.8
VCC(5V0) 7 P input to internal regulators (3.0 V-to-5.5 V); connect a 100 nF decoupling capacitor;
see Section 7.8
GND(OSC) 8 G oscillator ground
REG3V3 9 P regulator output (3.3 V); for decoupling only; connect a 100 nF capacitor and a
4.7 μF-to-10 μF capacitor; see Section 7.8
VCC(I/O) 10 P digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor; see
