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SAF-C515-L24M-SAF-C515-LM
8-Bit CMOS Microcontroller

Edition 1997-08-01
Published by
Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
Siemens AG 1997.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).
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your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
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Critical components
of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems
with the express
written approval of the Semiconductor Group of Siemens AG.A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
C515
8-Bit CMOS Microcontroller
Full upward compatibility with SAB 80C515
Up to 24 MHz external operating frequency500ns instruction cycle at 24 MHz operation
8K byte on-chip ROM (with optional ROM protection) alternatively up to 64K byte external program memory
Up to 64K byte external data memory
256 byte on-chip RAM
Six 8-bit parallel I/O ports
One input port for analog/digital input
Full duplex serial interface (USART)4 operating modes, fixed or variable baud rates
Three 16-bit timer/countersTimer 0 / 1 (C501 compatible)Timer 2 for 16-bit reload, compare, or capture functions
(more features on next page)

Figure 1
C515
Features (cont’d):
8-bit A/D converter8 multiplexed analog inputsProgrammable reference voltages
16-bit watchdog timer
Power saving modesIdle modeSlow down mode (can be combined with idle mode)Software power-down mode
12 interrupt sources (7 external, 5 internal) selectable at four priority levels
On-chip emulation support logic (Enhanced Hooks Technology
TM
ALE switch-off capability
P-MQFP-80-1 package
Temperature Ranges :SAB-C515
= 0 to 70
SAF-C515
= -40 to 85
SAH-C515
= -40 to 110
C (max. operating frequency: 16 MHz)
The C515 is an upward compatible version of the SAB 80C515A 8-bit microcontroller which
additionally provides ALE switch-off capability, on-chip emulation support, ROM protection, and
slow down mode capability. With a maximum external clock rate of 24 MHz it achieves a 500 ns
instruction cycle time (1
s at 12 MHz). The C515 is mounted in a P-MQFP-80 package.

Note:
Versions for extended temperature ranges – 40C to 110
˚C (SAH-C515C-LM and SAH-
C515-1RM) are available on request. The ordering number of ROM types (DXXXX
extensions) is defined after program release (verification) of the customer.
Ordering Information
C515

Figure 2
Logic Symbol
Additional Literature
For further information about the C515 the following literature is available:
C515

Figure 3

C515 Pin Configuration (P-MQFP-80 Package, Top View)

C515
Table 1
Pin Deﬁnitions and Functions I= Input= Output
C515I= Input= Output
Table 1
Pin Deﬁnitions and Functions (cont’d)
C515I= Input= Output
Table 1
Pin Deﬁnitions and Functions (cont’d)
C515I= Input= Output
Table 1
Pin Deﬁnitions and Functions (cont’d)
C515I= Input= Output
Table 1
Pin Deﬁnitions and Functions (cont’d)
C515I= Input= Output
Table 1
Pin Deﬁnitions and Functions (cont’d)
C515

Figure 4
Block Diagram of the C515C
C515
CPU
The C515 is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-
byte instructions. With a 6 MHz crystal, 58% of the instructions are executed in 1.0ms (10 MHz: 600).
Special Function Register PSW (Address D0H) Reset Value : 00H
D0HPSWHD6HD5HD4HD3HD2HD1HD0H
Bit No.MSBLSB
C515
Memory Organization
The C515 CPU manipulates data and operands in the following four address spaces:up to 64 Kbyte of internal/external program memoryup to 64 Kbyte of external data memory256 bytes of internal data memorya 128 byte special function register area
Figure 5 illustrates the memory address spaces of the C515.

Figure 5
C515 Memory Map
C515
Reset and System Clock
The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the
oscillator is running. A pullup resistor is internally connected to VCC to allow a power-up reset with
an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting
the RESET pin to VSS via a capacitor. Figure 6 shows the possible reset circuitries.

Figure 6
Reset Circuitries
C515
Figure 7 shows the recommended oscillator circuitries for crystal and external clock operation.

Figure 7
Recommended Oscillator Circuitries
C515
Enhanced Hooks Emulation Concept
The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.
Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.
The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500
together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.

Figure 8
Basic C500 MCU Enhanced Hooks Concept Configuration
Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the programm execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.
C515
Special Function Registers
The registers, except the program counter and the four general purpose register banks, reside in
the special function register area.
The 59 special function registers (SFRs) include pointers and registers that provide an interface
between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0-
2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable.
The SFRs of the C515 are listed in table 2 and table 3. In table 2 they are organized in groups
which refer to the functional blocks of the C515. Table 3 illustrates the contents of the SFRs in
numeric order of their addresses.

C515
Table 2
Special Function Registers - Functional Blocks
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved
C515

1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved
Table 2
Special Function Registers - Functional Blocks (cont’d)
C515
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
C515

1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
C515
Digital I/O Ports
The C515 allows for digital I/O on 48 lines grouped into 6 bidirectional 8-bit ports. Each port bit
consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0
through P5 are performed via their corresponding special function registers P0 to P5.
The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external
memory. In this application, port 0 outputs the low byte of the external memory address, time-
multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory
address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR
contents.
Analog Input Ports
Ports 6 is available as input port only and provides two functions. When used as digital inputs, the
corresponding SFR P6 contains the digital value applied to the port 6 lines. When used for analog
inputs the desired analog channel is selected by a three-bit field in SFR ADCON. Of course, it
makes no sense to output a value to these input-only ports by writing to the SFR P6. This will have
no effect.
lf a digital value is to be read, the voltage levels are to be held within the input voltage specifications
(VIL/VIH). Since P6 is not bit-addressable, all input lines of P6 are read at the same time by byte
instructions.
Nevertheless, it is possible to use port 6 simultaneously for analog and digital input. However, care
must be taken that all bits of P6 that have an undetermined value caused by their analog function
are masked.
C515
Timer / Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4 :
In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the
count rate is fOSC/12.
In the “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be
programmed to function as a gate to facilitate pulse width measurements. Figure 9 illustrates the
input clock logic.

Figure 9
Table 4
Timer/Counter 0 and 1 Operating Modes
C515
Timer/Counter 2 with Compare/Capture/Reload
The timer 2 of the C515 provides additional compare/capture/reload features. which allow the
selection of the following operating modes:Compare: up to 4 PWM signals with 16-bit/500 ns resolutionCapture: up to 4 high speed capture inputs with 500 ns resolutionReload: modulation of timer 2 cycle time
The block diagram in figure 10 shows the general configuration of timer 2 with the additional
compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as
multifunctional port functions at port 1.

Figure 10
C515
Timer 2 Operating Modes
The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A
roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer overflow flag TF2 in SFR
IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer
2 operation.
Timer Mode: In timer function, the count rate is derived from the oscillator frequency. A prescaler
offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency.
Gated Timer Mode: In gated timer function, the external input pin T2 (P1.7) functions as a gate to
the input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the
counting procedure. This facilitates pulse width measurements. The external gate signal is sampled
once every machine cycle.
Event Counter Mode: In the event counter function. the timer 2 is incremented in response to a 1-
to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is
sampled every machine cycle. Since it takes two machine cycles (24 oscillator periods) to recognize
a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are no
restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled
at least once before it changes, it must be held for at least one full machine cycle.
Reload of Timer 2: Two reload modes are selectable:
In mode 0, when timer 2 rolls over from all 1’s to all 0’s, it not only sets TF2 but also causes the timer
2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software.
In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the correspon-
ding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1 has been
set.
C515
Timer 2 Compare Modes
The compare function of a timer/register combination operates as follows : the 16-bit value stored
in a compare or compare/capture register is compared with the contents of the timer register; if the
count value in the timer register matches the stored value, an appropriate output signal is generated
at a corresponding port pin and an interrupt can be generated.
Compare Mode 0
In compare mode 0, upon matching the timer and compare register contents, the output signal
changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode
0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port
will have no effect. Figure 11 shows a functional diagram of a port circuit when used in compare
mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The
input line from the internal bus and the write-to-latch line of the port latch are disconnected when
compare mode 0 is enabled.

Figure 11
Port Latch in Compare Mode 0

Partno	Mfg	Dc	Qty	Available	Descript
SAF-C515-L24M \|SAFC515L24M	INF	N/a	7	avai	8-Bit CMOS Microcontroller
SAF-C515-LM \|SAFC515LM	INF	N/a	1000	avai	8-Bit CMOS Microcontroller