SAF-C165H-LFV1.3 ,16-Bit Microcontroller with HDLCData Sheet, DS 1, April 2001C165HEmbedded C166 with USART, IOM-2 and HDLC SupportVersion 1.3WiredCo ..
SAF-C165H-LFV1.3 . ,16-Bit Microcontroller with HDLCData Sheet, DS 1, April 2001C165HEmbedded C166 with USART, IOM-2 and HDLC SupportVersion 1.3WiredCo ..
SAF-C165-L25F ,16-Bit Single-Chip MicrocontrollerData Sheet, V2.0, Dec. 2000C16516-Bit Single-Chip MicrocontrollerMicrocontrollersNe ve r st op t h ..
SAF-C165-L25M ,16-Bit Single-Chip MicrocontrollerData Sheet, V2.0, Dec. 2000C16516-Bit Single-Chip MicrocontrollerMicrocontrollersNe ve r st op t h ..
SAF-C165-LF ,16-Bit Single-Chip MicrocontrollerData Sheet, V2.0, Dec. 2000C16516-Bit Single-Chip MicrocontrollerMicrocontrollersNe ve r st op t h ..
SAF-C165-LM ,16-Bit Single-Chip MicrocontrollerData Sheet, V2.0, Dec. 2000C16516-Bit Single-Chip MicrocontrollerMicrocontrollersNe ve r st op t h ..
SC801IML.TRT , Fully Integrated High Currnet Lithium-Ion Battery Charger System
SC801IMLTRT , Fully Integrated High Currnet Lithium-Ion Battery Charger System
SC802 , Fully Integrated Lithium-Ion Battery Charger System with Timer
SC802-09 ,SCHOTTKY BARRIER DIODE
SC802AIMLTRT , Fully Integrated Lithium-Ion Battery Charger System with Timer
SC802IMLTRT , Fully Integrated Lithium-Ion Battery Charger System with Timer
SAF-C165H-LFV1.3-SAF-C165H-LFV1.3 .
16-Bit Microcontroller with HDLC
C165H
Embedded C166 with
USART, IOM-2 and
HDLC Supportrsion 1.3
C165H
Embedded C166 with
USART, IOM-2 and
HDLC Supportrsion 1.3
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
C165H
Revision History:2001-04-01DS 1
Previous Version: This is the first non-preliminary version. 1)All previous distributed versions are preliminary. They have been replaced by this version.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.1Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3Pinning Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.4Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4.1ISDN NT and PBX Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1C165H Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2C165H Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.1Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2On-Chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3Clock Generation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.4On-Chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.5Protected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.1Internal RAM and SFR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Central Processor Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555.1Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.2Bit-Handling and Bit-Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.4CPU Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.5PEC - Extension of Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926.1Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.2Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3Operation of the PEC Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.4Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . . . . 105
6.5Saving the Status during Interrupt Service . . . . . . . . . . . . . . . . . . . . . . . 108
6.6Interrupt Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.7PEC Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.8External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.8.1Fast External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.8.2External Interrupt Source Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.8.3Interrupt Subnode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.8.4The Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.9Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
