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SAF-C161S-LM3VAA
16-Bit Microcontrollers
C161S
Revision History:2003-11V1.0
Previous Version:none
C161S16-Bit Single-Chip Microcontroller
C166 Family
C161SSummary of FeaturesHigh Performance 16-bit CPU with 4-Stage Pipeline80 ns Instruction Cycle Time at 25MHz CPU Clock400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)Enhanced Boolean Bit Manipulation FacilitiesAdditional Instructions to Support HLL and Operating SystemsRegister-Based Design with Multiple Variable Register BanksSingle-Cycle Context Switching Support16 Mbytes Total Linear Address Space for Code and Data1024 Bytes On-Chip Special Function Register Area16-Priority-Level Interrupt System with 30 Sources, Sample-Rate down to 40 ns8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock inputOn-Chip Memory Modules: 2 Kbytes On-Chip Internal RAM (IRAM)On-Chip Peripheral ModulesTwo Multi-Functional General Purpose Timer Units with 5 TimersTwo Serial Channels (Sync./Asynchronous and High-Speed-Synchronous)On-Chip Real Time ClockExternal Address Space for Code and DataProgrammable External Bus Characteristics for Different Address RangesMultiplexed or Demultiplexed External Address/Data Buses with 8-bit or 16-bit
Data Bus WidthFour Programmable Chip-Select Signals4 Mbytes maximum address window size, results in a total external address space
of 16 Mbytes, when all chip-select signal (address windows) are activeIdle and Power Down Modes with Flexible Power ManagementProgrammable Watchdog Timer and Oscillator WatchdogUp to 63 General Purpose I/O Lines,
partly with Selectable Input Thresholds and HysteresisPower Supply: the C161S can operate from a 5 V or a 3 V power supply (see Table
1)Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming BoardsOn-Chip Bootstrap Loader
