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SABC501GL24M-SAB-C501G-L24M-SAB-C501G-L24N-SAB-C501G--L24N-SAB-C501G-L24P-SAB-C501G-L40P-SAB-C501-GLM-SAB-C501G-LP
8-Bit Microcontroller
Edition 1997-04-01
Published by
Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München Siemens AG 1997.
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C501
8-Bit CMOS Microcontroller
C501Fully compatible to standard 8051 microcontroller
Versions for 12/24/40 MHz operating frequency
Program memory :completely external (C501-L)
·
8 ROM (C501-1R)
·
8 OTP memory (C501-1E)
256
8 RAM
Four 8-bit ports
Three 16-bit timers / counters (timer 2 with up/down counter feature)
USART
Six interrupt sources, two priority levels
Power saving modes
Quick Pulse programming algorithm (C501-1E only)
2-Level program memory lock (C501-1E only)
P-DIP-40, P-LCC-44, and P-MQFP-44 package
Temperature ranges :SAB-C501
: 0
˚C to 70
SAF-C501
: – 40
˚C to 85
Figure 1
C501G Functional Units
C501The C501-1R contains a non-volatile 8K
8 read-only program memory, a volatile 256
8 read/
write data memory, four ports, three 16-bit timers counters, a seven source, two priority level
interrupt structure and a serial port. The C501-L is identical, except that it lacks the program
memory on chip. The C501-1E contains a one-time programmable (OTP) program memory on chip.
The term C501 refers to all versions within this specification unless otherwise noted. Further, the
term C501 refers to all versions which are available in the different temperature ranges, marked with
SAB-C501... or SAF-C501....
.
Ordering InformationC501
Note:Versions for extended temperature range – 40
˚C to 110
C (SAH-C501G) on request.
The ordering number of ROM types (DXXX extensions) is defined after program release
(verification) of the customer.
Additional LiteratureFor further information about the C501 the following literature is available :
Figure 2
Pin Configuration P-LCC-44 Package (Top view)C501
Figure 3
Pin Configuration P-DIP-40 Package (top view)
C501
Figure 4
Pin Configuration P-MQFP-44 Package (top view)
Figure 5
C501
Table 1
Pin Definitions and FunctionsI= Input= Output
C501I= Input= Output
Table 1
Pin Definitions and Functions (cont’d)
C501I= Input= Output
Table 1
Pin Definitions and Functions
(cont’d)
C501I= Input= Output
Table 1
Pin Definitions and Functions (cont’d)
C501I= Input= Output
Table 1
Pin Definitions and Functions (cont’d)
C501
Functional Description
The C501 is fully compatible to the standard 8051 microcontroller family.
It is compatible with the 80C32/52/82C52. While maintaining all architectural and operational
characteristics of the 8051microcontroller family, the C501 incorporates some enhancements in the
timer 2 unit.
Figure 6 shows a block diagram of the C501.
Figure 6
Block Diagram of the C501
C501
CPU
The C501 is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15%
three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0 ms
24 MHz: 500 ns, 40 MHz : 300 ns).
Special Function Register PSW (Address D0H) Reset Value : 00H
D0HPSWHD6HD5HD4HD3HD2HD1HD0H
Bit No.MSBLSB
C501
Memory Organization
The C501 CPU manipulates data and operands in the following four address spaces:up to 64 Kbyte of internal/external program memoryup to 64 Kbyte of external data memory256 bytes of internal data memorya 128 byte special function register area
Figure 7 illustrates the memory address spaces of the C501.
Figure 7
C501 Memory Map
C501
Special Function Registers
The registers, except the program counter and the four general purpose register banks, reside in
the special function register area.
The 27 special function registers (SFRs) include pointers and registers that provide an interface
between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits
0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable.
The SFRs of the C501 are listed in table 2 and table 3. In table 2 they are organized in groups
which refer to the functional blocks of the C501. Table 3 illustrates the contents of the SFRs in
numeric order of their addresses.
C501
Table 2
Special Function Registers - Functional Blocks
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved
C501
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses
1) X means that the value is undefined and the location is reserved
C501
Timer / Counter 0 and 1
Timer/counter 0 and 1 can be used in four operating modes as listed in table 4.
In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the
count rate is fOSC/12.
In the “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is fOSC/24. External inputs INTO and INT1 (P3.2, P3.3) can be
programmed to function as a gate to facilitate pulse width measurements. Figure 8 illustrates the
input clock logic.
Figure 8
Table 4
Timer/Counter 0 and 1 Operating Modes
C501
Timer 2
Timer 2 is a 16-bit timer/counter with an up/down count feature. It can operate either as timer or as
an event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown
in table 5.
Note: fl = falling edge
Table 5
Timer/Counter 2 Operating Modes
C501
Serial Interface (USART)
The serial port is full duplex and can operate in four modes (one synchronous mode, three
asynchronous modes) as illustrated in table 6. The possible baudrates can be calculated using the
formulas given in table 7.
Table 6
USART Operating Modes
Table 7
Formulas for Calculating Baudrates
C501
Interrupt System
The C501 provides 6 interrupt sources with two priority levels. Figure 9 gives a general overview of
the interrupt sources and illustrates the request and control flags.
Figure 9
Interrupt Request Sources
C501
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-
priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.
If two requests of different priority level are received simultaneously, the request of higher priority is
serviced. If requests of the same priority are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority
structure determined by the polling sequence as shown in table 9.
Table 8
Interrupt Sources and their Corresponding Interrupt Vectors
Table 9
Interrupt Priority-Within-Level
C501
Power Saving Modes
Two power down modes are available, the Idle Mode and Power Down Mode.
The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode,
respectively. If the Power Down mode and the Idle mode are set at the same time, the Power Down
mode takes precedence. Table 10 gives a general overview of the power saving modes.
In the Power Down mode of operation, VCC can be reduced to minimize power consumption. It must
be ensured, however, that VCC is not reduced before the Power Down mode is invoked, and that VCC
is restored to its normal operating level, before the Power Down mode is terminated. The reset
signal that terminates the Power Down mode also restarts the oscillator. The reset should not be
activated before VCC is restored to its normal operating level and must be held active long enough
to allow the oscillator to restart and stabilize (similar to power-on reset).
Table 10
Power Saving Modes Overview
