SAB82525-SAB82525H-SAB82525N-SAB82525-N-SAB82526N-SAF82525-SAF82525N-SAF82526-SAF82526N-SAF-82532H-10-SAF82532N-10-SAF82538H-10 Fast Delivery |IC PHOENIX CO.,LIMITED

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Partno	Mfg	Dc	Qty	Available	Descript
SAB82525	INFINEON	N/a	10	avai	Data Communications ICs
SAB82525H	INFINEON	N/a	190	avai	Data Communications ICs
SAB82525N	INFINEON	N/a	1235	avai	Data Communications ICs
SAB82525-N \|SAB82525N	INFINEON	N/a	42	avai	Data Communications ICs
SAB82526N	SIEMENS	N/a	400	avai	Data Communications ICs
SAF82525	N/A	N/a	630	avai	Data Communications ICs
SAF82525N	INFINEON	N/a	2000	avai	Data Communications ICs
SAF82526	INFINEON	N/a	27	avai	Data Communications ICs
SAF82526N		N/a	500	avai	Data Communications ICs
SAF82526N	SIEMENS	N/a	16	avai	Data Communications ICs
SAF-82532H-10 \|SAF82532H10	infineon	N/a	280	avai	ICs for Communications
SAF82532N-10 \|SAF82532N10	SIEMENS	N/a	2	avai	ICs for Communications
SAF82538H-10 \|SAF82538H10	INFINEON	N/a	7	avai	ICs for Communications

SAF82525N ,Data Communications ICsapplications, processes and circuits implemented within components or assemblies.The information de ..
SAF82526 ,Data Communications ICs Data Communications ICsHigh-Level ..
SAF82526N ,Data Communications ICscharacteristics apply at TA = 25 °C and the given supply voltage.Operating RangeIn the operating ra ..
SAF82526N ,Data Communications ICs Data Communications ICsHigh-Level ..
SAF-82532H-10 ,ICs for Communicationscharacteristics are ensured over the operating range of the integrated circuit. Typical
SAF82532H-10V3.2A ,ESCC2 (Enhanced Serial Communication ...Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
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SC801IMLTRT , Fully Integrated High Currnet Lithium-Ion Battery Charger System
SC802 , Fully Integrated Lithium-Ion Battery Charger System with Timer
SC802-09 ,SCHOTTKY BARRIER DIODE
SC802AIMLTRT , Fully Integrated Lithium-Ion Battery Charger System with Timer
SC802IMLTRT , Fully Integrated Lithium-Ion Battery Charger System with Timer

SAB82525-SAB82525H-SAB82525N-SAB82525-N-SAB82526N-SAF82525-SAF82525N-SAF82526-SAF82526N-SAF-82532H-10-SAF82532N-10-SAF82538H-10
Data Communications ICs

Table of ContentsPage
1Features..................................................................................................................... 6
1.1Pin Definitions and Functions................................................................................... 10
1.2System Integration.................................................................................................... 17
1.3Functional Description ..............................................................................................22Operating Modes .....................................................................................................24
2.1Auto-Mode (MODE: MDS1, MDS0 = 00) ..................................................................24
2.2Non-Auto Mode (MODE: MDS1, MDS0 = 01) ..........................................................24
2.3Transparent Mode 1 (MODE: MDS1, MDS0, ADM = 101) .......................................25
2.4Transparent Mode 0 (MODE: MDS1, MDS0, ADM = 100) .......................................25
2.5Extended Transparent Modes 0; 1 (MODE: MDS1, MDS0 = 11) .............................25
2.6Receive Data Flow (Summary) .................................................................................26
2.7Transmit Data Flow ...................................................................................................27Procedural Support (Layer-2 Functions) ..............................................................28
3.1Full-Duplex LAPB/LAPD Operation ..........................................................................28
3.2Half-Duplex SDLC-NRM Operation ..........................................................................34
3.3Error Handling ...........................................................................................................38CPU Interface ..........................................................................................................38
4.1Register Set.............................................................................................................. 38
4.2Data Transfer Modes.................................................................................................38
4.3Interrupt Interface ......................................................................................................39
4.4DMA Interface........................................................................................................... 43
4.5FIFO Structure ..........................................................................................................47Serial Interface (Layer-1 Functions) ......................................................................49
5.1Clock Modes..............................................................................................................49
5.2Clock Recovery (DPLL)............................................................................................ 57
5.3Bus Configuration..................................................................................................... 60
5.4Data Encoding ..........................................................................................................63
5.5Modem Control Functions (RTS/CTS, CD) ...............................................................63Special Functions ...................................................................................................65
6.1Fully Transparent Transmission and Reception .......................................................65
6.2Cyclic Transmission (Fully Transparent) ...................................................................65
6.3Continuous Transmission (DMA Mode only) ............................................................66
6.4Receive Length Check Feature ................................................................................66
6.5One Bit Insertion .......................................................................................................67
6.6Data Inversion........................................................................................................... 67
Table of ContentsPage
6.8Test Mode .................................................................................................................68
6.7Special RTS Function ...............................................................................................68Operational Description .........................................................................................69
7.1RESET...................................................................................................................... 69
7.2Initialization ...............................................................................................................70
7.3Operational Phase.................................................................................................... 71
7.4Data Transmission.................................................................................................... 71
7.5Data Reception .........................................................................................................75Detailed Register Description................................................................................ 79
8.1Register Address Arrangement .................................................................................79
8.2Register Definitions ...................................................................................................80Electrical Characteristics .....................................................................................108Quartz Specifications ...........................................................................................118Package Outlines ..................................................................................................125

Features (cont’d)

Pin Configurations
(top view)

Pin No.

Pin No.

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RTS Signal in Clock Mode 5
When using the RTS signal in clock mode 5, it has to be considered, that the RTS signal is
deactivated after the transmission of the second last bit (instead of the last) of a closing flag, if
that second last bit is the last bit of a time-slot “window“. In other words, RTS is inactive during
the transmission of the last bit, transmitted in the next time-slot window. See figure 24.
Figure 24
SAB82525
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This must be considered for applications, where several transmitters are sharing the same
time-slot on a non open-drain bus, e.g. a balanced bus, not using collision detection as the
resolution mechanism. One such application is slave stations in a point-to-multipoint
configuration sharing the same time-slot and using NRM auto-mode. Thus, RTS and the time-
slot marker TxCLK cannot simply be gated to generate a driver control signal. Instead the
following recommendations apply:Do not use the RTS signal directly in clock mode 5 e.g. to enable drivers for TxD in a
balanced bus configuration. Instead, use an arrangement of the type shown in the figure 25
Figure 25
SAB82525
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SAF82526delay the rising edge of RTS (e.g. for NRM mode with balanced bus).
Figure 26
Timing diagram for recommendation b):
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SAB82526
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SAF82526
CTS Signal in Clock Mode 5
In clock mode 5 the CTS signal is evaluated not only in the time-slot “window“, but also
between the time-slot “windows“. If data transmission must not be stopped, CTS has to be
active, even between the time-slot “windows“, until the transmission of the frame has been
completed. In other words, a deactivation of CTS stops the transmitter immediately.
Note:When several HDLC channels are sharing the same time-slot on a bus without using
the bus collision detection, the strobe signals (AxCLKA/B) can be used to select/
deselect particular time-slot “windows“ for an individual HDLC channel.
Clock Mode 6 (OSC – Receive Clock from DPLL)
This clock mode equals the features of Clock Mode 2, with the only exception that the clock for
the BRG is delivered by the OSC and must not be provided externally.
Clock Mode 7 (OSC – Receive and Transmit Clock from DPLL)
Similar to Clock Mode 3, but BRG clock is provided by OSC.
SAB82525
SAB82526
SAF82525
SAF82526
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The following functions have been implemented to facilitate a high-speed and reliable
synchronization (see figures 28).
– Interference Rejection
In the case where two or more edges appear in the data stream within a time period of 16
reference clocks, these are detected as interference without performing additional
adjustments.

Figure 28b
– Phase Adjustment
In the case where an edge with a phase angle of 20 to 112 degrees appears in the data stream
within the time window, the phase will be adjusted by 1/16 of the data clock.

Figure 28c
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5.3Bus Configuration
Beside the point-to-point configuration, the HSCX effectively supports point-to-multipoint (pt-
mpt, or bus) configurations by means of internal idle and collision detection/collision resolution
methods.
In a pt-mpt configuration, comprising a central station (master) and several peripheral stations
(slaves), or in a multimaster configuration (see figure 6), data transmission can be initiated by
each station over a common transmit line (bus). In case more than one station attempt to
transmit data simultaneously (collision), the bus is assigned to one station by a collision-
resolution procedure implemented by the HSCX. The bus assignment function is based on a
priority principle with both fixed and rotating priorities that enables each station to access the
bus in a predeterminable time. As a result, any number of transmitters can be connected to the
serial bus.
Prerequisites for bus operation are:
– NRZ encoding
– OR connection of data at the bus
– feedback of bus information (C×DA/C×DB input)
The bus configuration is selected via the CCR1 register.
Note: Central clock supply for each station is not necessary if both the receive and transmit
clock is recovered by the DPLL (clock mode 7). In this case, the function of the DPLL
also minimizes the phase shift between the transmit clocks of the individual transmitters
so that an opening flag sequence will be sufficient to allow a correct collision detection.
The bus mode can be operated independently of the clock mode, e.g. also during clock
mode 1 (receive and transmission strobe) or clock mode 5 (programmable time-slots).
SAB82525
SAB82526
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