SAB80C166-M ,16-Bit MicrocontrollerCharacteristics for Different Address Rangesl 8-Bit or 16-Bit External Data Busl Multiplexed or Dem ..
SAB80C166-M ,16-Bit MicrocontrollerCharacteristics for Different Address Rangesl 8-Bit or 16-Bit External Data Busl Multiplexed or Dem ..
SAB80C166-M25DA ,16-Bit MicrocontrollerMicrocomputer Components16-Bit CMOS Single-Chip MicrocontrollerSAB 80C166/83C166Data Sheet 09.94 C1 ..
SAB-80C166-MDA ,16-Bit MicrocontrollerCharacteristics for Different Address Rangesl 8-Bit or 16-Bit External Data Busl Multiplexed or Dem ..
SAB80C166-MDA ,16-Bit MicrocontrollerMicrocomputer Components16-Bit CMOS Single-Chip MicrocontrollerSAB 80C166/83C166Data Sheet 09.94 C1 ..
SAB80C166-M-DA ,16-Bit MicrocontrollerCharacteristics for Different Address Rangesl 8-Bit or 16-Bit External Data Busl Multiplexed or Dem ..
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SAB80C166-M-SAB80C166-M25DA-SAB-80C166-MDA-SAB80C166-MDA-SAB80C166-M-DA-SAB80C166-MT3-SAB80C166-M-T3-SAB83C166-5M-SAB83C166-5M-T3
16-Bit Microcontroller
High Performance 16-bit CPU with 4-Stage Pipeline100 ns Instruction Cycle Time at 20 MHz CPU Clock500 ns Multiplication (16 · 16 bit), 1 ms Division (32 / 16 bit)Enhanced Boolean Bit Manipulation FacilitiesRegister-Based Design with Multiple Variable Register BanksSingle-Cycle Context Switching SupportUp to 256 KBytes Linear Address Space for Code and Data1 KByte On-Chip RAM32 KBytes On-Chip ROM (SAB 83C166 only)Programmable External Bus Characteristics for Different Address Ranges8-Bit or 16-Bit External Data BusMultiplexed or Demultiplexed External Address/Data BusesHold and Hold-Acknowledge Bus Arbitration Support512 Bytes On-Chip Special Function Register AreaIdle and Power Down Modes8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral EventController (PEC)16-Priority-Level Interrupt System10-Channel 10-bit A/D Converter with 9.7 ms Conversion Time16-Channel Capture/Compare UnitTwo Multi-Functional General Purpose Timer Units with 5 TimersTwo Serial Channels (USARTs)Programmable Watchdog TimerUp to 76 General Purpose I/O LinesSupported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages,
Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers,
Programming BoardsOn-Chip Bootstrap Loader100-Pin Plastic MQFP Package (EIAJ)
C16x-Family of
High-Performance CMOS 16-Bit Microcontrollers
Preliminary
SAB 80C166/83C166 16-Bit Microcontroller
SAB 80C166/83C166
SAB 80C166/83C166
IntroductionThe SAB 80C166 is the first representative of the Siemens SAB 80C166 family of full featured
single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million
instructions per second) with high peripheral functionality and enhanced IO-capabilities.
Figure 1
Logic Symbol
Ordering Information
Note:The ordering codes (Q67120-D...) for the Mask-ROM versions are defined for each product
after verification of the respective ROM code.
SAB 80C166/83C166
Pin Configuration Rectangular P-MQFP-100-2(top view)
SAB 80C166/83C166
Pin Definitions and Functions
SAB 80C166/83C166
Pin Definitions and Functions (cont’d)
SAB 80C166/83C166
Pin Definitions and Functions (cont’d)
SAB 80C166/83C166
Pin Definitions and Functions (cont’d)
SAB 80C166/83C166
Functional DescriptionThe architecture of the SAB 80C166 combines advantages of both RISC and CISC processors and
of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives
an overview of the different on-chip components and of the advanced, high bandwidth internal bus
structure of the SAB 80C166.
Note:All time specifications refer to a CPU clock of 20 MHz
(see definition in the AC Characteristics section).
Figure 3
Block Diagram
SAB 80C166/83C166
Memory OrganizationThe memory space of the SAB 80C166 is configured in a Von Neumann architecture which means
that code memory, data memory, registers and I/O ports are organized within the same linear
address space which includes 256 KBytes. Address space expansion to 16 MBytes is provided for
future versions. The entire memory space can be accessed bytewise or wordwise. Particular
portions of the on-chip memory have additionally been made directly bit addressable.
The SAB 83C166 contains 32 KBytes of on-chip mask-programmable ROM for code or constant
data. The ROM can be mapped to either segment 0 or segment 1.
1 KByte of on-chip RAM is provided as a storage for user defined variables, for the system stack,
general purpose register banks and even for code. A register bank can consist of up to 16 wordwide
(R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers
(GPRs).
512 bytes of the address space are reserved for the Special Function Register area. SFRs are
wordwide registers which are used for controlling and monitoring functions of the different on-chip
units. 98 SFRs are currently implemented. Unused SFR addresses are reserved for future
members of the SAB 80C166 family.
In order to meet the needs of designs where more memory is required than is provided on chip, up
to 256 KBytes of external RAM and/or ROM can be connected to the microcontroller.
External Bus ControllerAll of the external memory accesses are performed by a particular on-chip External Bus Controller
(EBC). It can be programmed either to Single Chip Mode when no external memory is required, or
to one of four different external memory access modes, which are as follows:
– 16-/18-bit Addresses, 16-bit Data, Demultiplexed
– 16-/18-bit Addresses, 16-bit Data, Multiplexed
– 16-/18-bit Addresses, 8-bit Data, Multiplexed
– 16-/18-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on Port 1 and data is input/output on Port 0.
In the multiplexed bus modes both addresses and data use Port 0 for input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-
State Time, Read/Write Delay and Length of ALE, i.e. address setup/hold time with respect to ALE)
have been made programmable to allow the user the adaption of a wide range of different types of
memories. In addition, different address ranges may be accessed with different bus characteristics.
Access to very slow memories is supported via a particular ‘Ready’ function. A HOLD/HLDA
protocol is available for bus arbitration.
For applications which require less than 64 KBytes of external memory space, a non-segmented
memory model can be selected. In this case all memory locations can be addressed by 16 bits and
Port 4 is not required to output the additional segment address lines.
SAB 80C166/83C166
Central Processing Unit (CPU)The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the SAB 80C166’s instructions can be executed in just
one machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate
instructions are always processed during one machine cycle independent of the number of bits to
be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast
as well: branches in 2 cycles, a 16 · 16 bit multiplication in 5 cycles and a 32-/16 bit division in
10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution
time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are
physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the
base address of the active register bank to be accessed by the CPU at a time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter passing,
a register bank may overlap others.
Figure 4
CPU Block Diagram
SAB 80C166/83C166A system stack of up to 512 bytes is provided as a storage for temporary data. The system stack is
allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register.
Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value
upon each stack access for the detection of a stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently be utilized
by a programmer via the highly efficient SAB 80C166 instruction set which includes the following
instruction classes:Arithmetic InstructionsLogical InstructionsBoolean Bit Manipulation InstructionsCompare and Loop Control InstructionsShift and Rotate InstructionsPrioritize InstructionData Movement InstructionsSystem Stack InstructionsJump and Call InstructionsReturn InstructionsSystem Control InstructionsMiscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words.
A variety of direct, indirect or immediate addressing modes are provided to specify the required
operands.
SAB 80C166/83C166
Interrupt SystemWith an interrupt response time within a range from just 250 ns to 600 ns (in case of internal
program execution), the SAB 80C166 is capable of reacting very fast to the occurrence of non-
deterministic events.
The architecture of the SAB 80C166 supports several mechanisms for fast and flexible response to
service requests that can be generated from various sources internal or external to the
microcontroller. Any of these interrupt requests can be programmed to being serviced by the
Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is suspended and
a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service. A PEC service implies a single byte or word data transfer between
any two memory locations with an additional increment of either the PEC source or the destination
pointer. An individual PEC transfer counter is implicity decremented for each PEC service except
when performing in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data, or for
transferring A/D converted results to a memory table. The SAB 80C166 has 8 PEC channels each
of which offers such fast interrupt-driven data transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable flag and an
interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each
source can be programmed to one of sixteen interrupt priority levels. Once having been accepted
by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For
the standard interrupt processing, each of the possible interrupt sources has a dedicated vector
location.
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
The following table shows all of the possible SAB 80C166 interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:
SAB 80C166/83C166
SAB 80C166/83C166The SAB 80C166 also provides an excellent mechanism to identify and to process exceptions or
error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause
immediate non-maskable system reaction which is similar to a standard interrupt service (branching
to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by
an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service
is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap
services can normally not be interrupted by standard or PEC interrupts.
The following table shows all of the possible exceptions or error conditions that can arise during run-
time:
SAB 80C166/83C166
Capture/Compare (CAPCOM) UnitThe CAPCOM unit supports generation and control of timing sequences on up to 16 channels with
a maximum resolution of 400 ns (@ 20 MHz CPU clock). The CAPCOM unit is typically used to
handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation
(PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external
events.
Two 16-bit timers (T0/T1) with reload registers provide two independent time bases for the capture/
compare register array.
The input clock for the timers is programmable to several prescaled values of the CPU clock, or may
be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of
variation for the timer period and resolution and allows precise adjustments to the application
specific requirements. In addition, an external count input for CAPCOM timer T0 allows event
scheduling for the capture/compare registers relative to external events.
The capture/compare register array contains 16 dual purpose capture/compare registers, each of
which may be individually allocated to either CAPCOM timer T0 or T1, and programmed for capture
or compare function. Each register has one port pin associated with it which serves as an input pin
for triggering the capture function, or as an output pin to indicate the occurrence of a compare event.
When a capture/compare register has been selected for capture mode, the current contents of the
allocated timer will be latched (captured) into the capture/compare register in response to an
external event at the port pin which is associated with this register. In addition, a specific interrupt
request for this capture/compare register is generated. Either a positive, a negative, or both a
positive and a negative external signal transition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modes are
continuously compared with the contents of the allocated timers. When a match occurs between the
timer value and the value in a capture/compare register, specific actions will be taken based on the
selected compare mode.
SAB 80C166/83C166
Figure 5
CAPCOM Unit Block Diagram
SAB 80C166/83C166
General Purpose Timer (GPT) UnitThe GPT unit represents a very flexible multifunctional timer/counter structure which may be used
for many different time related tasks such as event timing and counting, pulse width and duty cycle
measurements, pulse generation, or pulse multiplication.
The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1
and GPT2. Each timer in each module may operate independently in a number of different modes,
or may be concatenated with another timer of the same module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three
basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the
input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while
Counter Mode allows a timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of
a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has
one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the
timers in module GPT1 is 400 ns (@ 20 MHz CPU clock).
Figure 6
Block Diagram of GPT1
SAB 80C166/83C166The count direction (up/down) for each timer is programmable by software. For timer T3 the count
direction may additionally be altered dynamically by an external signal on a port pin (T3EUD) to
facilitate e. g. position tracking.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-flow/
underflow. The state of this latch may be output on a port pin (T3OUT) e. g. for timeout monitoring
of external hardware components, or may be used internally to clock timers T2 and T4 for
measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture
registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The
contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins
(TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or
by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to
alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM
signal, this signal can be constantly generated without software intervention.
Figure 7
Block Diagram of GPT2
SAB 80C166/83C166With its maximum resolution of 200 ns (@ 20 MHz), the GPT2 module provides precise event
control and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via
a programmable prescaler. The count direction (up/down) for each timer is programmable by
software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The
overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1,
and to cause a reload from the CAPREL register. The CAPREL register may capture the contents
of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer
T5 may optionally be cleared after the capture procedure. This allows absolute time differences to
be measured or pulse multiplication to be performed without software overhead.
A/D ConverterFor analog signal measurement, a 10-bit A/D converter with 10 multiplexed input channels and a
sample and hold circuit has been integrated on-chip. It uses the method of successive
approximation. The sample time (for loading the capacitors) and the conversion time adds up to
9.7 us @ 20 MHz CPU clock.
Overrun error detection/protection is provided for the conversion result register (ADDAT): an
interrupt request will be generated when the result of a previous conversion has not been read from
the result register at the time the next conversion is complete.
For applications which require less than 10 analog input channels, the remaining channel inputs can
be used as digital input port pins.
The A/D converter of the SAB 80C166 supports four different conversion modes. In the standard
Single Channel conversion mode, the analog level on a specified channel is sampled once and
converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified
channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode,
the analog levels on a prespecified number of channels are sequentially sampled and converted. In
the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and
converted.
The Peripheral Event Controller (PEC) may be used to automatically store the conversion results
into a table in memory for later evaluation, without requiring the overhead of entering and exiting
interrupt routines for each data transfer.
SAB 80C166/83C166
Parallel PortsThe SAB 80C166 provides up to 76 I/O lines which are organized into five input/output ports and
one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise)
programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports
which are switched to high impedance state when configured as inputs. During the internal reset, all
port pins are configured as inputs.
All port lines have programmable alternate input or output functions associated with them. Port 0
and Port 1 may be used as address and data lines when accessing external memory, while Port 4
outputs the additional segment address bits A17/A16 in systems where segmentation is enabled to
access more than 64 KBytes of memory. Port 2 is associated with the capture inputs or compare
outputs of the CAPCOM unit and/or with optional bus arbitration signals (BREQ, HLDA, HOLD).
Port 3 includes alternate functions of timers, serial interfaces, optional bus control signals (WR,
BHE, READY) and the system clock output (CLKOUT). Port 5 is used for the analog input channels
to the A/D converter. All port lines that are not used for these alternate functions may be used as
general purpose I/O lines.
Serial ChannelsSerial communication with other microcontrollers, processors, terminals or external peripheral
components is provided by two serial interfaces with identical functionality, Asynchronous/
Synchronous Serial Channels ASC0 and ASC1.
They are upward compatible with the serial ports of the Siemens SAB 8051x microcontroller family
and support full-duplex asynchronous communication up to 625 Kbaud and half-duplex
synchronous communication up to 2.5 Mbaud @ 20 MHz CPU clock.
Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning.
For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for
each serial channel.
In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit
and terminated by one or two stop bits. For multiprocessor communication, a mechanism to
distinguish address from data bytes has been included (8-bit data + wake up bit mode).
In synchronous mode one data byte is transmitted or received synchronously to a shift clock which
is generated by the SAB 80C166.
A loop back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. A parity bit can automatically be generated on transmission or be
checked on reception. Framing error detection allows to recognize data frames with missing stop
bits. An overrun error will be generated, if the last character received has not been read out of the
receive buffer register at the time the reception of a new character is complete.
SAB 80C166/83C166
Watchdog TimerThe Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to
prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time
interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up
procedure is always monitored. The software has to be designed to service the Watchdog Timer
before it overflows. If, due to hardware or software related failures, the software fails to do so, the
Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low
in order to allow external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the CPU clock divided either by 2 or by 128. The
high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in
WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced
by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals
between 25 ms and 420 ms can be monitored (@ 20 MHz CPU clock). The default Watchdog Timer
interval after reset is 6.55 ms (@ 20 MHz CPU clock).
Bootstrap LoaderThe SAB 80C166 provides a built-in bootstrap loader (BSL), which allows to start program
execution out of the SAB 80C166’s internal RAM. The program to be started is loaded via the serial
interface ASC0 and does not require external memory or an internal ROM.
The SAB 80C166 enters BSL mode, when ALE is sampled high at the end of a hardware reset and
if NMI becomes active directly after the end of the internal reset sequence. BSL mode is entered
independent of the bus mode selected via EBC0, EBC1 and BUSACT.
After entering BSL mode the SAB 80C166 scans the RXD0 line to receive a zero byte, i.e. one start
bit, eight ‘0’ data bits and one stop bit. From the duration of this zero byte it calculates the
corresponding baudrate factor with respect to the current CPU clock and initializes ASC0
accordingly. Using this baudrate, an acknowledge byte is returned to the host that provides the
loaded data. The SAB 80C166 returns the value <55H>.
The next 32 bytes received via ASC0 are stored sequentially into locations 0FA40H through 0FA5FH
of the internal RAM. To execute the loaded code the BSL then jumps to location 0FA40H. The
loaded program may load additional code / data, change modes, etc.
The SAB 80C166 exits BSL mode upon a software reset (ignores the ALE level) or a hardware reset
(remove conditions for entering BSL mode before).
SAB 80C166/83C166
Instruction Set SummaryThe table below lists the instructions of the SAB 80C166 in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation of the
instructions, parameters for conditional execution of instructions, and the opcodes for each
instruction can be found in the “C16x Family Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Instruction Set Summary
SAB 80C166/83C166
Instruction Set Summary (cont’d)
SAB 80C166/83C166
Special Function Registers OverviewThe following table lists all SFRs which are implemented in the SAB 80C166 in alphabetical order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”.
An SFR can be specified via its individual mnemonic name. Depending on the selected addressing
mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its
short 8-bit address (without using the Data Page Pointers).
Special Function Registers Overview
SAB 80C166/83C166
Special Function Registers Overview (cont’d)
