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SAB-C541U-1EN-SAB-C541U-1EN B12-SAB-C541U-1ENB12
8-Bit USB Microcontroller with on-chi...

Edition 05.99
This edition was realized using the software system FrameMaker.
Published by Siemens AG,
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Kommunikation, Balanstraße 73,
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8-Bit CMOS Microcontroller
Advance Information
C541UEnhanced 8-bit C500 CPUFull software/toolset compatible to standard 80C51/80C52 microcontrollers12 MHz external operating frequency500 ns instruction cycleBuilt-in PLL for USB synchronizationOn-chip OTP program memory 8K byte Alternatively up to 64K byte external program memory Optional memory protectionOn-chip USB module Compliant to USB specification Rev1.0 Full speed or low speed operation Five endpoints :one bidirectional control endpoint
four versatile programmable endpoints Registers are located in special function register area On-chip USB transceiver

Figure 1
C541U Functional Units
C541U
Features (continued) :Up to 64K byte external data memory256 byte on-chip RAMFour parallel I/O ports P-LCC-44 package :three 8-bit ports and one 6-bit port P-SDIP-52* package :four 8-bit ports LED current drive capability for 3 pins (10 mA)Two 16-bit timer/counters (C501 compatible)SSC synchronous serial interface (SPI compatible)Master and slave capableProgrammable clock polarity / clock-edge to data phase relationLSB/MSB first selectable1.5 MBaud transfer rate at 12 MHz operating frequency7 interrupt sources (2 external, 5 internal with 2 USB interrupts) selectable at 2 priority levelsEnhanced fail safe mechanisms Programmable watchdog timerOscillator watchdogPower saving modesidle modesoftware power down mode with wake-up capability through INT0 pin or USBOn-chip emulation support logic (Enhanced Hooks Technology TM)P-LCC-44 and P-SDIP-52* packagesPower supply voltage range : 4.25V to 5.5VTemperature Range :TA=0 to 70°C
* P-SDIP-52 package is available on specific request from customer
C541U
C541U

Figure 3
Pin Configuration (Top View)

C541U
Table 1
Pin Definitions and Functions I=Input=Output
C541UI=Input=Output
Table 1
Pin Definitions and Functions (cont’d)
C541UI=Input
Table 1
Pin Definitions and Functions (cont’d)
C541UI=Input=Output
Table 1
Pin Definitions and Functions (cont’d)
C541U
C541U
CPU
The C541U is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-
byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 500ns.
Special Function Register PSW (Address D0H) Reset Value : 00H
D0HPSWHD6HD5HD4HD3HD2HD1HD0H
Bit No.MSBLSB
C541U
C541U
Reset and System Clock
The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the
oscillator is running. A pulldown resistor is internally connected to VSS to allow a power-up reset with
an external capacitor only. An automatic reset can be obtained when VDD is applied by connecting
the RESET pin to VDD via a capacitor. Figure 6 shows the possible reset circuitries.

Figure 6
Reset Circuitries
C541U
C541U
C541U
C541U
Special Function Registers
The registers, except the program counter and the four general purpose register banks, reside in
the special function register area. The special function register area consists of two portions: the
standard special function register area and the mapped special function register area. One special
function register of the C541U (PCON1) is located in the mapped special function register area. All
other SFRs are located in the standard special function register area.
For accessing PCON1 in the mapped special function register area, bit RMAP in special function
register SYSCON must be set.
Special Function Register SYSCON (Address B1H) Reset Value : XX10XXXXB
As long as bit RMAP is set, a mapped special function register can be accessed. This bit is not
cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed,
the bit RMAP must be cleared/set by software, respectively each.
The registers, except the program counter and the four general purpose register banks, reside in the
special function register area. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H,H, 90H, 98H, ..., F8H, FFH) are bitaddressable.
The 75 special function registers (SFRs) in the SFR area include pointers and registers that provide
an interface between the CPU and the other on-chip peripherals. The SFRs of the C541U are listed
in table 2 to table 4. In table 2 they are organized in groups which refer to the functional blocks of
the C541U. Table 4 and table 4 illustrate the contents of the SFRs in numeric order of their
addresses.
76543210B1HSYSCON
Bit No.MSBLSB
The functions of the shaded bits are not described in this section.
C541U
Table 2
Special Function Registers - Functional Blocks
1) Bit-addressable special function registers
2) “X“ means that the value is undefined and the location is reserved
3) The content of this SFR varies with the actual of the step C541U (eg. 01H for the first step)
4) This SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be
set.

C541U

1) These register are multiple registers (n=0-4) with the same SFR address; selection of register “n“ is done by
SFR EPSEL.
2) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset.
3) The reset value of EPIR0 is 11H.
4) These registers are only used in USB low-speed operation.
Table 2
Special Function Registers - Functional Blocks (cont’d)
C541U
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
C541U
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
4) These are read-only registers
5) The content of this SFR varies with the actual step of the C541U (e.g. 01H for the first step)
6) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset
7) These registers are only used in USB low-speed operation.
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
C541U

1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
4) These are read-only registers
5) The content of this SFR varies with the actual step of the C541U (e.g. 01H for the first step)
6) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset.
7) These registers are only used in USB low-speed operation.
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
C541U
Table 4
Contents of the USB Device and Endpoint Registers (Addr. C1H to C7H)
EPSEL = 1XXX.XXXXB Device Registers
EPSEL = 0XXX.X000BEndpoint 0 Registers
EPSEL = 0XXX.X001BEndpoint 1 Registers
C541U
EPSEL = 0XXX.X010BEndpoint 2 Registers
EPSEL = 0XXX.X011BEndpoint 3 Registers
EPSEL = 0XXX.X100BEndpoint 4 Registers
Table 4
Contents of the USB Device and Endpoint Registers (Addr. C1H to C7H) (cont’d)
C541U
Digital I/O Ports
The C541U three 8-bit I/O ports and one 6-bit I/O port (Port 1). Port 0 is an open-drain bidirectional
I/O port, while ports 1 to 3 are quasi-bidirectional I/O ports with internal pullup resistors. That means,
when configured as inputs, ports 1 to 3 will be pulled high and will source current when externally
pulled low. Port 0 will float when configured as input.
The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external
memory. In this application, port 0 outputs the low byte of the external memory address, time
multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory
address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR
contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET.
Two port lines of port 1 (P1.0/LED0, P1.1/LED1) and one port line of port 3 (P3.0/LED2) have the
capability of driving external LEDs in the output low state.
C541U
Timer / Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in table 5 :
In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the
count rate is fOSC/6.
In the “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is fOSC/12. External inputs INT0 and INT1 (P3.2, P3.3) can be
programmed to function as a gate to facilitate pulse width measurements. Figure 10 illustrates the
input clock logic.

Figure 10
Table 5
Timer/Counter 0 and 1 Operating Modes
C541U
C541U
USB Module
The USB module in the C541U handles all transactions between the serial USB bus and the internal
(parallel) bus of the microcontroller. The USB module includes several units which are required to
support data handling with the USB bus : the on-chip USB bus transceiver, the USB memory with
two pages of 128 bytes each, the memory management unit (MMU) for USB and CPU memory
access control, the UDC device core for USB protocol handling, the microcontroller interface with
the USB specific special function registers and the interrupt control logic. A clock generation unit
provides the clock signal for the USB module for full speed and low speed USB operation. Figure
12 shows the block diagram of the functional units of the USB module with their interfaces.

Figure 12
USB Module Block Diagram
C541U
USB Full-Speed Registers
Two different kinds of registers are implemented for full speed operation in the USB module. The
global registers (GEPIR, EPSEL, ADROFF, USBVAL) describe the basic functionality of the
complete USB module and can be accessed via unique SFR addresses. For reduction of the
number of SFR addresses which are needed to control the USB module inside the C541U, device
registers and endpoint registers are mapped into an SFR address block of seven SFR addresses
(C1H to C7H). The endpoint specific functionality of the USB module is controlled via the device
registers DCR, DPWDR, DIER, DIRR and the frame number registers. An endpoint register set is
available for each endpoint (n=0..4) and describes the functionality of the selected endpoint. Figure
13 explains the structure of the USB module registers.

Figure 13
Register Structure of the USB Module
C541U
C541U

Partno	Mfg	Dc	Qty	Available	Descript
SAB-C541U-1EN \|SABC541U1EN	INFIN	N/a	500	avai	8-Bit USB Microcontroller with on-chi...
SAB-C541U-1EN B12 \|SABC541U1ENB12	INFINEON	N/a	1500	avai	8-Bit USB Microcontroller with on-chi...
SAB-C541U-1ENB12 \|SABC541U1ENB12	SIEMENS	N/a	221	avai	8-Bit USB Microcontroller with on-chi...