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SAB-C517A-LN-SAF-C517A-LN
8-Bit Microcontrollers
Edition 01.99This edition was realized using the software system FrameMaker.
Published by : Siemens AG, Semiconductor Group, Product Definition 8-Bit Microcontroller Components,
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8-Bit CMOS Microcontroller
Advance Information
C517A
C517AFeatures (continued) :
Two full duplex serial interfaces (USART)4 operating modes, fixed or variabie baud ratesprogrammable baud rate generators
Four 16-bit timer/countersTimer 0 / 1 (C501 compatible)Timer 2 for 16-bit reload, compare, or capture functionsCompare timer for compare/capture functions
Powerful 16-bit compare/capture unt (CCU) with up to 21 high-speed or PWM output channels
and 5 capture inputs
10-bit A/D converter12 multiplexed analog inputsBuilt-in self calibration
Extended watchdog facilities15-bit programmable watchdog timerOscillator watchdog
Power saving modesSlow down mode Idle mode (can be combined with slow down mode)Software power-down modeHardware power-down mode
17 interrupt sources (7 external, 10 internal) selectable at 4 priority levels
P-MQFP-100 and P-LCC-84 packages
Temperature Ranges :SAB-C517ATA=0 to 70°C
SAF-C517ATA=-40 to 85°C
SAH-C517ATA=-40 to 110°C
Ordering InformationThe ordering code for Siemens microcontrollers provides an exact reference to the required
product. This ordering code identifies:
the derivative itself, i.e. its function set
the specified temperature range
the package and the type of delivery.
For the available ordering codes for the C517A please refer to the
„Product Information Microcontrollers“, which summarizes all available microcontroller variants.
Note:The ordering codes for the Mask-ROM versions are defined for each product after
verification of the respective ROM code.
C517A
Figure 2
Logic Symbol
C517A
Figure 3
Pin Configuration P-MQFP-100 Package (Top View) �
C517A
Figure 4
Pin Configuration P-LCC-84 Package (Top View) C517A
Table 1
Pin Definitions and Functions I=Input,
O=Output
C517AI=Input
Table 1
Pin Definitions and Functions (cont’d)
C517AI=Input=Output
Table 1
Pin Definitions and Functions (cont’d)
C517AI=Input=Output
Table 1
Pin Definitions and Functions (cont’d)
C517AI=Input
Table 1
Pin Definitions and Functions (cont’d)
C517AI=Input=Output
Table 1
Pin Definitions and Functions (cont’d)
C517AI=Input=Output
Table 1
Pin Definitions and Functions (cont’d)
C517AI=Input=Output
Table 1
Pin Definitions and Functions (cont’d)
C517A
C517A
CPUThe C517A is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-
byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1μs (24 MHz : 500
ns).
Special Function Register PSW (Address D0H) Reset Value : 00H D0HPSWHD6HD5HD4HD3HD2HD1HD0H
Bit No.MSBLSB
C517A
C517A
Reset and System ClockThe reset input is an active low input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the
oscillator is running. A pullup resistor is internally connected to VDD to allow a power-up reset with
an external capacitor only. An automatic reset can be obtained when VDD is applied by connecting
the RESET pin to VSS via a capacitor. Figure 7 shows the possible reset circuitries.
Figure 7
Reset Circuitries
C517A
Figure 8 shows the recommended oscillator circiutries for crystal and external clock operation.
Figure 8
Recommended Oscillator Circuitries
C517A
C517A
Special Function RegistersThe registers, except the program counter and the four general purpose register banks, reside in
the special function register area.
The 94 special function registers (SFRs) in the standard and mapped SFR area include pointers
and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs
with addresses where address bits 0-2 are 0 (e
.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable. The SFRs of the C517A are listed in
table 2 and table 3. In table 2 they are organized in groups which refer to the functional blocks ofthe C517A. Table 3 illustrates the contents of the SFRs in numeric order of their addresses.
C517A
Table 2
Special Function Registers - Functional Blocks 1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved
C517A1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
Table 2
Special Function Registers - Functional Blocks (cont’d)
C517A 1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved.
Table 2
Special Function Registers - Functional Blocks (cont’d)
C517A
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses 1) X means that the value is undefined and the location is reserved
2) Shaded registers are bit-addressable special function registers
C517A1) X means that the value is undefined and the location is reserved
2) Shaded registers are bit-addressable special function registers
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
C517A1) X means that the value is undefined and the location is reserved
2) Shaded registers are bit-addressable special function registers
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
C517A1) X means that the value is undefined and the location is reserved
2) Shaded registers are bit-addressable special function registers
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
C517A
Digital I/O PortsThe C517A allows for digital I/O on 56 lines grouped into 7 bidirectional 8-bit ports. Each port bit
consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0
through P6 are performed via their corresponding special function registers P0 to P6.
The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external
memory. In this application, port 0 outputs the low byte of the external memory address, time-
multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory
address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR
contents.
Analog Input PortsPorts 7 (8-bit) and 8 (4-bit) are input ports only and provide two functions. When used as digital
inputs, the corresponding SFR P7 and P8 contains the digital value applied to the port 7/8 lines.
When used for analog inputs the desired analog channel is selected by a four-bit field in SFR
ADCON1. Of course, it makes no sense to output a value to these input-only ports by writing to the
SFR P7 or P8. This will have no effect.
lf a digital value is to be read, the voltage levels are to be held within the input voltage specificationsIL/VIH). Since P7 and P8 are not bit-addressable, all input lines of P7 and P8 are read at the same
time by byte instructions.
Nevertheless, it is possible to use port 7 and 8 simultaneously for analog and digital input. However,
care must be taken that all bits of P7 and P8 that have an undetermined value caused by their
analog function are masked.
C517A
Timer / Counter 0 and 1Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4 :
In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the
count rate is fOSC/12.
In the “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be
programmed to function as a gate to facilitate pulse width measurements. Figure 10 illustrates the
input clock logic.
Figure 10
Table 4
Timer/Counter 0 and 1 Operating Modes
C517A
Cpmpare / Capture Unit (CCU) The compare/capture unit is one of the C517A’s most powerful peripheral units for use in all kinds
of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse
width measuring etc. The CCU consists of two 16-bit timer/counters with automatic reload feature
and an array of 13 compare or compare/capture registers. A set of six control registers is used for
flexible adapting of the CCU to a wide variety of user’s applications.
The block diagram in figure 11 shows the general configuration of the CCU. All CC1 to CC4
registers and the CRC register are exclusively assigned to timer 2. Each of the eight compare
registers CM0 through CM7 can either be assigned to timer 2 or to the faster compare timer, e.g. to
provide up to 8 PWM output channels. The assignment of the CMx registers - which can be done
individually for every single register - is combined with an automatic selection of one of the two
possible compare modes.
C517AThe main functional blocks of the CCU are :Timer 2 with fOSC/12 input clock, 2-bit prescaler, 16-bit reload, counter/gated timer mode and
overflow interrupt request.Compare timer with fOSC/2 input clock, 3-bit prescaler, 16-bit reload and overflow interrupt
request.Compare/(reload/)capture register array consisting of four different kinds of registers:
one 16-bit compare/reload/capture register,
three 16-bit compare/capture registers,
one 16-bit compare/capture register with additional "concurrent compare" feature,
eight 16-bit compare registers with timer-overflow controlled loading.
Table 5 shows the possible configurations of the CCU and the corresponding compare modeswhich can be selected. The following sections describe the function of these configurations.
Table 5
CCU Configurations
C517A
C517A
C517A
