SAB-C163-LF ,16-Bit Microcontrollerscharacteristics.Terms of delivery and rights to change design reserved.For questions on technology, ..
SAB-C165-L25F ,16-Bit Single-Chip MicrocontrollerData Sheet, V2.0, Dec. 2000C16516-Bit Single-Chip MicrocontrollerMicrocontrollersNe ve r st op t h ..
SAB-C165-L25F HA ,16-Bit MicrocontrollerData Sheet, V2.0, Dec. 2000C16516-Bit Single-Chip MicrocontrollerMicrocontrollersNe ve r st op t h ..
SAB-C165-L25M ,16-Bit Single-Chip MicrocontrollerData Sheet, V2.0, Dec. 2000C16516-Bit Single-Chip MicrocontrollerMicrocontrollersNe ve r st op t h ..
SAB-C165-LF ,16-Bit Single-Chip MicrocontrollerData Sheet, V2.0, Dec. 2000C16516-Bit Single-Chip MicrocontrollerMicrocontrollersNe ve r st op t h ..
SAB-C165-LF ,16-Bit Single-Chip MicrocontrollerData Sheet, V2.0, Dec. 2000C16516-Bit Single-Chip MicrocontrollerMicrocontrollersNe ve r st op t h ..
SC6121-002 ,stock - INFRARED REMOTE CONTROL TRANSMITTER
SC6121-002 ,stock - INFRARED REMOTE CONTROL TRANSMITTER
SC6122 ,stock - INFRARED REMOTE CONTROL TRANSMITTER
SC613IMLTRT , Low Noise Regulated Charge Pump with Selectable Output
SC615AMLTRT , Charge Pump Flash LED Driver
SC615IMLTRT , Charge Pump Flash LED Driver
SAB-C163-L25F-SAB-C163-LF
16-Bit Microcontrollers
High Performance 16-bit CPU with 4-Stage Pipeline80 ns Instruction Cycle Time at 25MHz CPU Clock400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)Enhanced Boolean Bit Manipulation FacilitiesAdditional Instructions to Support HLL and Operating SystemsRegister-Based Design with Multiple Variable Register BanksSingle-Cycle Context Switching Support16 MBytes Total Linear Address Space for Code and Data1024 Bytes On-Chip Special Function Register Area16-Priority-Level Interrupt System with 20 Sources, Sample-Rate down to 40 ns8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities viaPeripheral Event Controller (PEC)Clock Generation via on-chip PLL (1:1.5/2/2.5/3/4/5), via prescaler or via direct clock inputOn-Chip Memory Modules1 KBytes On-Chip Internal RAM (IRAM)On-Chip Peripheral ModulesTwo Multi-Functional General Purpose Timer Units with 5 TimersTwo Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)Up to 16 MBytes External Address Space for Code and DataProgrammable External Bus Characteristics for Different Address RangesMultiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus WidthFive Programmable Chip-Select SignalsHold- and Hold-Acknowledge Bus Arbitration SupportIdle and Power Down Modes Programmable Watchdog Timer and Oscillator WatchdogUp to 77 General Purpose I/O Lines High Speed Operation with 5 V Supply up to 25MHzLow Power Operation with 3 V Supply up to 12MHzSupported by a Large Range of Development Tools like C-Compilers, Macro-Assembler
Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer
Disassemblers, Programming Boards100-Pin TQFP Package (Thin QFP)
This document describes the SAB-C163-LF, the SAB-C163-L25F and the SAF-C163-L25F.
C166-Family of
High-Performance CMOS 16-Bit Microcontrollers
Preliminary
C163-L 16-Bit Microcontroller
C163-L
Introduction
The C163-L is a derivative of the Siemens C166 family of 16-bit single-chip CMOS microcontrollers.
It combines high CPU performance (up to 12.5 million instructions per second) with high peripheral
functionality and enhanced IO-capabilities.
Figure 1
Logic Symbol
The C163-L can be operated from a 5V power supply as well as from a 3V power supply (25MHz
versions C163-L25F only). Within the standard supply voltage range of VDD = 4.5 - 5.5V it delivers
its maximum performance at CPU clock frequencies of up to 25MHz. Within the reduced supply
voltage range of VDD = 2.7 - 3.6V it provides low power operation for energy sensitive applications
at CPU clock frequencies of up to 12MHz (PLL operation is not supported in this case).
Ordering Information
The ordering code for Siemens microcontrollers provides an exact reference to the required
product. This ordering code identifies:the derivative itself, ie. its function setthe specified temperature rangethe packagethe type of delivery.
For the available ordering codes for the C163-L please refer to the
Note:
the respective ROM code.
Pin Configuration TQFP Package
(top view)
Figure 2
Pin Definitions and Functions
Pin Definitions and Functions (cont’d)
Pin Definitions and Functions (cont’d)
Pin Definitions and Functions (cont’d)
Functional Description
The architecture of the C163-L combines advantages of both RISC and CISC processors and of
advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an
overview of the different on-chip components and of the advanced, high bandwidth internal bus
structure of the C163-L.
Note:All time specifications refer to a CPU clock of 25/12 MHz for 5/3 V operation
(see definition in the AC Characteristics section).
Figure 3
Block Diagram
Memory Organization
The memory space of the C163-L is configured in a Von Neumann architecture which means that
code memory, data memory, registers and I/O ports are organized within the same linear address
space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise.
Particular portions of the on-chip memory have additionally been made directly bit addressable.
The C163-L is prepared to incorporate on-chip mask-programmable ROM, OTP or Flash memory
for code or constant data. Currently no program memory is integrated.
1 KByte of on-chip RAM is provided as a storage for user defined variables, for the system stack,
general purpose register banks and even for code. A register bank can consist of up to 16 wordwide
(R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers
(GPRs).
1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register
areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling
and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for
other/future members of the C166 family.
In order to meet the needs of designs where more memory is required than is provided on chip, up
to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller.
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus Controller
(EBC). It can be programmed either to Single Chip Mode when no external memory is required, or
to one of four different external memory access modes, which are as follows:
– 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed
– 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on
PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for
input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-
State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user
the adaption of a wide range of different types of memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx /
BUSCONx) which allow to access different resources with different bus characteristics. These
address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and
BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows
are controlled by BUSCON0.
Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue
logic. Access to very slow memories is supported via a particular ‘Ready’ function.
A HOLD/HLDA protocol is available for bus arbitration and allows to share external resources with
other bus masters. The bus arbitration is enabled by setting bit HLDEN in register SYSCON. After
setting HLDEN once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the
EBC. In Master Mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to ’1’ the
Slave Mode is selected where pin HLDA is switched to input. This allows to directly connect the
slave controller to another master controller without glue logic.
For applications which require less than 16 MBytes of external memory space, this address space
can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no
address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used.
Note:When the on-chip SSP Module is to be used the segment address output on Port 4 must be
limited to 4 bits (ie. A19...A16) in order to enable the alternate function of the SSP interface
pins.
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C163-L’s instructions can be executed in just one
machine cycle which requires 80 ns at 25-MHz CPU clock. For example, shift and rotate instructions
are always processed during one machine cycle independent of the number of bits to be shifted. All
multiple-cycle instructions have been optimized so that they can be executed very fast as well:
branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles.
Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 4
CPU Block Diagram
The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are
physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the
base address of the active register bank to be accessed by the CPU at a time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter passing,
a register bank may overlap others.
A system stack of up to 512 words is provided as a storage for temporary data. The system stack
is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP)
register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently be utilized
by a programmer via the highly efficient C163-L instruction set which includes the following
instruction classes:Arithmetic InstructionsLogical InstructionsBoolean Bit Manipulation InstructionsCompare and Loop Control InstructionsShift and Rotate InstructionsPrioritize InstructionData Movement InstructionsSystem Stack InstructionsJump and Call InstructionsReturn InstructionsSystem Control InstructionsMiscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words.
A variety of direct, indirect or immediate addressing modes are provided to specify the required
operands.
Interrupt System
With an interrupt response time within a range from just 200 ns to 480 ns (in case of internal
program execution), the C163-L is capable of reacting very fast to the occurence of non-
deterministic events.
The architecture of the C163-L supports several mechanisms for fast and flexible response to
service requests that can be generated from various sources internal or external to the
microcontroller. Any of these interrupt requests can be programmed to being serviced by the
Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is suspended and
a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service. A PEC service implies a single byte or word data transfer between
any two memory locations with an additional increment of either the PEC source or the destination
pointer. An individual PEC transfer counter is implicity decremented for each PEC service except
when performing in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data. The C163-
L has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable flag and an
interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each
source can be programmed to one of sixteen interrupt priority levels. Once having been accepted
by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For
the standard interrupt processing, each of the possible interrupt sources has a dedicated vector
location.
Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling
edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
The following table shows all of the possible C163-L interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:
The C163-L also provides an excellent mechanism to identify and to process exceptions or error
conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate
non-maskable system reaction which is similar to a standard interrupt service (branching to a
dedicated vector table location). The occurence of a hardware trap is additionally signified by an
individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in
progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap
services can normally not be interrupted by standard or PEC interrupts.
The following table shows all of the possible exceptions or error conditions that can arise during run-
time:
General Purpose Timer (GPT) Unit
The GPT unit represents a very flexible multifunctional timer/counter structure which may be used
for many different time related tasks such as event timing and counting, pulse width and duty cycle
measurements, pulse generation, or pulse multiplication.
The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1
and GPT2. Each timer in each module may operate independently in a number of different modes,
or may be concatenated with another timer of the same module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three
basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the
input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while
Counter Mode allows a timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of
a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has
one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the
timers in module GPT1 is 320 ns (@ 25MHz CPU clock).
The count direction (up/down) for each timer is programmable by software or may additionally be
altered dynamically by an external signal on a port pin (TxEUD) to facilitate e. g. position tracking.
Figure 5
Block Diagram of GPT1
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-flow/
underflow. The state of this latch may be output on port a pin (T3OUT) e.g. for time out monitoring
of external hardware components, or may be used internally to clock timers T2 and T4 for
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture
registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The
contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins
(TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or
by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to
alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM
signal, this signal can be constantly generated without software intervention.
Figure 6
Block Diagram of GPT2
With its maximum resolution of 160ns (@ 25MHz), the GPT2 module provides precise event
control and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via
a programmable prescaler or with external signals. The count direction (up/down) for each timer is
programmable by software or may additionally be altered dynamically by an external signal on a
port pin (TxEUD). Timer T6 has an output toggle latch (T6OTL) which changes its state on each
timer overflow/underflow. Concatenation of the timers is supported via T6OTL.
The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The
overflows/underflows of timer T6 can additionally be used to cause a reload from the CAPREL
register. The CAPREL register may capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the
capture procedure. This allows absolute time differences to be measured or pulse multiplication to
be performed without software overhead.
Parallel Ports
The C163-L provides up to 77 I/O lines which are organized into six input/output ports and one input
port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise)
programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports
which are switched to high impedance state when configured as inputs. The output drivers of three
I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control
registers. During the internal reset, all port pins are configured as inputs.
All port lines have programmable alternate input or output functions associated with them. PORT0
and PORT1 may be used as address and data lines when accessing external memory, while Port4
outputs the additional segment address bits A23/19/17...A16 in systems where segmentation is
enabled to access more than 64 KBytes of memory. Port 6 provides optional bus arbitration signals
(BREQ, HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial
interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is
used for timer control signals. All port lines that are not used for these alternate functions may be
used as general purpose I/O lines.
Serial Channels
Serial communication with other microcontrollers, processors, terminals or external peripheral
components is provided by two serial interfaces with different functionality, an Asynchronous/
Synchronous Serial Channel (ASC0) and a Synchronous Serial Port (SSP).
The ASC0 is upward compatible with the serial ports of the Siemens 8-bit microcontroller families
and supports full-duplex asynchronous communication at up to 781KBaud and half-duplex
synchronous communication at up to 3.125MBaud @ 25MHz CPU clock.
A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning.
For transmission, reception and error handling 4 separate interrupt vectors are provided. In
asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and
terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish
address from data bytes has been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock
which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is
available for testing purposes.number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. A parity bit can automatically be generated on transmission or be
checked on reception. Framing error detection allows to recognize data frames with missing stop
bits. An overrun error will be generated, if the last character received has not been read out of the
receive buffer register at the time the reception of a new character is complete.
The SSP transmits 1...3 bytes or receives 1 byte after sending 1...3 bytes synchronously to a shift
clock which is generated by the SSP. The SSP can start shifting with the LSB or with the MSB and
allows to select shifting and latching clock edges as well as the clock polarity. Up to two chip select
lines may be activated in order to direct data transfers to one or both of two peripheral devices.
One general interrupt vector is provided for the SSP.
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to
prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time
interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up
procedure is always monitored. The software has to be designed to service the Watchdog Timer
before it overflows. If, due to hardware or software related failures, the software fails to do so, the
Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low
in order to allow external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128.
The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in
WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced
by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals
between 20 μs and 336 ms can be monitored (@ 25 MHz). The default Watchdog Timer interval
after reset is 5.24 ms (@ 25 MHz).
Oscillator Watchdog
During direct drive or prescaler operation the Oscillator Watchdog (OWD) monitors the clock signal
generated by the on-chip oscillator (either with a crystal or via external clock drive). For this
operation the PLL provides a clock signal which is used to supervise transitions on the oscillator
clock. This PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and supplies the
CPU with the PLL clock signal. Under these circumstances the PLL will oscillate with its basic
frequency.
A low level on pin OWE disables the PLL and the OWD’s interrupt output so the clock signal is
derived from the oscillator clock in any case.
Note:The CPU clock source is only switched back to the oscillator clock after a hardware reset.
For 3V operation pin OWE must always be low (OWD disabled) as the PLL cannot deliver an
appropriate clock signal in this case.
For 5V operation pin OWE should only be pulled low (PLL disabled) if direct drive or prescaler
operation is configured. All other configurations (PLL factors) result in direct drive operation.
Instruction Set Summary
The table below lists the instructions of the C163-L in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation of the
instructions, parameters for conditional execution of instructions, and the opcodes for each
instruction can be found in the “C16x Family Instruction Set Manual”.
This document also provides a detailled description of each instruction.
Instruction Set Summary
Instruction Set Summary (cont’d)
Special Function Registers Overview
The following table lists all SFRs which are implemented in the C163-L in alphabetical order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended
SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within
on-chip X-Peripherals (SSP) are marked with the letter “X” in column “Physical Address”.
An SFR can be specified via its individual mnemonic name. Depending on the selected addressing
mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its
short 8-bit address (without using the Data Page Pointers).
Special Function Registers Overview
Special Function Registers Overview (cont’d)
Special Function Registers Overview (cont’d)
The system configuration is selected during reset.Bit WDTR indicates a watchdog timer triggered reset.Special Function Registers Overview (cont’d)
Absolute Maximum Ratings
Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
During absolute maximum rating overload conditions (VIN>VDD or VINmaximum ratings.
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct operation of the
C163-L. All parameters specified in the following sections refer to these operating conditions,
unless otherwise noticed.
Note:Operation at reduced supply voltage is defined for the 25MHz devices (SA*-C163L25F)
only.
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the C163-L and partly
its demands on the system. To aid in interpreting the parameters right, when evaluating them for a
design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the C163-L will provide signals with the respective timing characteristics.
SR (System Requirement):
The external system must provide signals with the respective timing characteristics to the C163-L.Overload conditions occur if the standard operatings conditions are exceeded, ie. the voltage on any pin
exceeds the specified range (ie. VOV>VDD+0.5V, except pin OWE, or VOVinput overload currents on all port pins may not exceed 50 mA. The supply voltage must remain within the
specified limits.Not 100% tested, guaranteed by design characterization.
DC Characteristics (Standard Supply Voltage Range)
(Operating Conditions apply)
This specification is not valid for outputs which are switched to open drain mode. In this case the respectiveoutput will float and the voltage results from the external circuitry.This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if
they are used for CS output and the open drain function is not enabled.The maximum current may be drawn while the respective signal line remains inactive.The minimum current must be drawn in order to drive the respective signal line active.Not 100% tested, guaranteed by design characterization.The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.
These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs
at VIL or VIH.This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at VDD – 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected.
DC Characteristics (Reduced Supply Voltage Range)
(Operating Conditions apply)
This specification is not valid for outputs which are switched to open drain mode. In this case the respectiveoutput will float and the voltage results from the external circuitry.This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if
they are used for CS output and the open drain function is not enabled.The maximum current may be drawn while the respective signal line remains inactive.The minimum current must be drawn in order to drive the respective signal line active.Not 100% tested, guaranteed by design characterization.The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.
These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs
at VIL or VIH.This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at VDD – 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected.
Figure 7
Supply/Idle Current as a Function of Operating Frequency
