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SAB-C161RI-L16F-SAB-C161RI-L16M-SAB-C161RI-L16M .
16-Bit Microcontroller
Edition 1998-05-01
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München© Siemens AG 1998.
All Rights Reserved.
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and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
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Components used in life-support devices or systems must be expressly authorized for such purpose!Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express
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failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
High Performance 16-bit CPU with 4-Stage Pipeline125 ns Instruction Cycle Time at 16MHz CPU Clock625 ns Multiplication (16 · 16 bits), 1.25 ms Division (32 / 16 bit)Enhanced Boolean Bit Manipulation FacilitiesAdditional Instructions to Support HLL and Operating SystemsRegister-Based Design with Multiple Variable Register BanksSingle-Cycle Context Switching SupportClock Generation via Prescaler or via Direct Clock InputUp to 8MBytes Linear Address Space for Code and Data1 KByte On-Chip Internal RAM (IRAM)2 KBytes On-Chip Extension RAM (XRAM)Programmable External Bus Characteristics for Different Address Ranges8-Bit or 16-Bit External Data BusMultiplexed or Demultiplexed External Address/Data Bus5 Programmable Chip-Select Signals1024 Bytes On-Chip Special Function Register Area8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral EventController (PEC)16-Priority-Level Interrupt System, 11 External Interrupts4-Channel 8-bit A/D Converter, conversion time down to 7.625ms2 Multi-Functional General Purpose Timer Units with five 16-bit TimersSynchronous/Asynchronous Serial Channel (USART)High-Speed Synchronous Serial ChannelI2C Bus Interface (10-bit Addressing, 400 KHz) with 2 Channels (multiplexed)Up to 76 General Purpose I/O LinesProgrammable Watchdog TimerOn-Chip Real Time ClockIdle and Power Down Modes with Flexible Power ManagementAmbient temperature range –40 to 85 °CSupported by a Large Range of Development Tools like C-Compilers, Macro-Assembler
Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer
Disassemblers, Programming BoardsOn-Chip Bootstraploader100-Pin MQFP / TQFP Package
This document describes the SAB-C161RI-LM, the SAB-C161RI-LF, the SAF-C161RI-LM and the
SAB-C161RI-LF.For simplicity all versions are referred to by the term C161RI throughout this document.
C166-Family of
High-Performance CMOS 16-Bit Microcontrollers
Preliminary
C161RI 16-Bit Microcontroller
C161RI
C161RI
IntroductionThe C161RI is a new derivative of the Siemens C166 Family of 16-bit single-chip CMOS
microcontrollers. It combines high CPU performance (up to 8 million instructions per second) with
high peripheral functionality and enhanced IO-capabilities. The C161RI derivative is especially
suited for cost sensitive applications.
Figure 1
Logic Symbol
Ordering InformationThe ordering code for Siemens microcontrollers provides an exact reference to the required
product. This ordering code identifies:the derivative itself, i.e. its function setthe specified temperature rangethe packagethe type of delivery.
For the available ordering codes for the C161RI please refer to the
“Product Information Microcontrollers”, which summarizes all available microcontroller variants.
Note:The ordering codes for the Mask-ROM versions are defined for each product after
verification of the respective ROM code.
C161RI
C161RI
Pin Configuration TQFP Package(top view)
Figure 3C161RI
C161RI
Pin Definitions and Functions (cont’d)
C161RI
C161RI1) The following behavior differences must be observed when the bidirectional reset is active:Bit BDRSTEN in register SYSCON cannot be changed after EINIT.After a reset bit BDRSTEN is cleared.The reset indication flags always indicate a long hardware reset.The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader
may be activated when P0L.4 is low.Pin RSTIN may only be connected to external reset devices with an open drain output driver.A short hardware reset is extended to the duration of the internal reset sequence.
Pin Definitions and Functions (cont’d)
C161RI
C161RI
Memory OrganizationThe memory space of the C161RI is configured in a Von Neumann architecture which means that
code memory, data memory, registers and I/O ports are organized within the same linear address
space which includes 16MBytes. The entire memory space can be accessed bytewise or
wordwise. Particular portions of the on-chip memory have additionally been made directly
bitaddressable.
1 KByte of on-chip Internal RAM is provided as a storage for user defined variables, for the system
stack, general purpose register banks and even for code. A register bank can consist of up to 16
wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose
Registers (GPRs).
1024 bytes (2 · 512 bytes) of the address space are reserved for the Special Function Register
areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling
and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for
future members of the C166 family.
In order to meet the needs of designs where more memory is required than is provided on chip, up
to 8MBytes of external RAM and/or ROM can be connected to the microcontroller.
C161RI
C161RI
Central Processing Unit (CPU)The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C161RI’s instructions can be executed in just one
machine cycle which requires 125ns at 16 MHz CPU clock. For example, shift and rotate
instructions are always processed during one machine cycle independent of the number of bits to
be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast
as well: branches in 2 cycles, a 16 · 16 bit multiplication in 5 cycles and a 32-/16 bit division in
10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution
time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 5
CPU Block Diagram
C161RI
C161RI
Interrupt SystemWith an interrupt response time within a range from just 315 ns to 750 ns (in case of internal
program execution), the C161RI is capable of reacting very fast to the occurrence of non-
deterministic events.
The architecture of the C161RI supports several mechanisms for fast and flexible response to
service requests that can be generated from various sources internal or external to the
microcontroller. Any of these interrupt requests can be programmed to being serviced by the
Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is suspended and
a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service. A PEC service implies a single byte or word data transfer between
any two memory locations with an additional increment of either the PEC source or the destination
pointer. An individual PEC transfer counter is implicity decremented for each PEC service except
when performing in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data. The C161RI
has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable flag and an
interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each
source can be programmed to one of sixteen interrupt priority levels. Once having been accepted
by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For
the standard interrupt processing, each of the possible interrupt sources has a dedicated vector
location.
Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling
edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
C161RI
C161RIThe C161RI also provides an excellent mechanism to identify and to process exceptions or error
conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate
non-maskable system reaction which is similar to a standard interrupt service (branching to a
dedicated vector table location). The occurence of a hardware trap is additionally signified by an
individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in
progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap
services can normally not be interrupted by standard or PEC interrupts.
The following table shows all of the possible exceptions or error conditions that can arise during run-
time:
C161RI
C161RI(CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute
time differences to be measured or pulse multiplication to be performed without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer
T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental
Interface Mode.
Figure 6
Block Diagram of GPT1
C161RI
C161RI
Real Time ClockThe Real Time Clock (RTC) module of the C161RI consists of a chain of 3 divider blocks, a fixed
8-bit divider, the reloadable 16-bit timer T14 and the 32-bit RTC timer (accessible via registers
RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided
by 32 via a separate clock driver and is therefore independent from the selected clock generation
mode of the C161RI. All timers count up.
The RTC module can be used for different purposes:System clock to determine the current time and dateCyclic time based interrupt48-bit timer for long term measurements
Figure 7-1
RTC Block Diagram
Note:The registers associated with the RTC are not effected by a reset in order to maintain the
correct system time even when intermediate resets are executed.
C161RI
C161RI
Serial ChannelsSerial communication with other microcontrollers, processors, terminals or external peripheral
components is provided by two serial interfaces with different functionality, an Asynchronous/
Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).
The ASC0 is upward compatible with the serial ports of the Siemens 8-bit microcontroller familiesand supports full-duplex asynchronous communication at up to 500KBaud and half-duplex
synchronous communication at up to 2MBaud @ 16MHz CPU clock.
A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning.
For transmission, reception and error handling 4 separate interrupt vectors are provided. In
asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and
terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish
address from data bytes has been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock
which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is
available for testing purposes.number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. A parity bit can automatically be generated on transmission or be
checked on reception. Framing error detection allows to recognize data frames with missing stop
bits. An overrun error will be generated, if the last character received has not been read out of the
receive buffer register at the time the reception of a new character is complete.
The SSC supports full-duplex synchronous communication at up to 4Mbaud @ 16MHz CPU clock.
It may be configured so it interfaces with serially linked peripheral components. A dedicated baud
rate generator allows to set up all standard baud rates without oscillator tuning. For transmission,
reception and error handling 3 separate interrupt vectors are provided.
The SSC transmits or receives characters of 2…16 bits length synchronously to a shift clock which
can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can
start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock
edges as well as the clock polarity.number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. Transmit and receive error supervise the correct handling of the data
buffer. Phase and baudrate error detect incorrect serial data.
C161RI
C161RI
Instruction Set SummaryThe table below lists the instructions of the C161RI in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation of the
instructions, parameters for conditional execution of instructions, and the opcodes for each
instruction can be found in the “C166 Family Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Instruction Set Summary
C161RI
C161RI
Special Function Registers OverviewThe following table lists all SFRs which are implemented in the C161RI in alphabetical order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended
SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers withinon-chip X-Peripherals (I2C) are marked with the letter “X” in column “Physical Address”.
An SFR can be specified via its individual mnemonic name. Depending on the selected addressing
mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its
short 8-bit address (without using the Data Page Pointers).
C161RI
C161RI
