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SC6121-002 ,stock - INFRARED REMOTE CONTROL TRANSMITTER
SAB-C161O-L16M-SABC161OL16MAA-SAB-C161O-L16MAA-SAB-C161V-L16M
16-Bit Microcontroller
High Performance 16-bit CPU with 4-Stage Pipeline125 ns Instruction Cycle Time at 16-MHz CPU Clock625 ns Multiplication (16 · 16 bits), 1,25 ms Division (32 / 16 bit)Enhanced Boolean Bit Manipulation FacilitiesAdditional Instructions to Support HLL and Operating SystemsRegister-Based Design with Multiple Variable Register BanksSingle-Cycle Context Switching SupportClock Generation via Prescaler or via Direct Clock InputUp to 4 MBytes Linear Address Space for Code and Data1 KByte On-Chip RAM on C161V and C161K, 2 KBytes On-Chip RAM on C161OProgrammable External Bus Characteristics for Different Address Ranges8-Bit or 16-Bit External Data BusMultiplexed or Demultiplexed External Address/Data Buses (MUX Bus only on C161V)Programmable Chip-Select Signals (not on C161V)1024 Bytes On-Chip Special Function Register AreaIdle and Power Down Modes (not on C161V)8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral EventController (PEC)16-Priority-Level Interrupt System with 14 Sources on C161V, 20 Sources on C161K, C161OMulti-Functional General Purpose Timer Unit(s)Synchronous/Asynchronous Serial ChannelHigh-Speed-Synchronous Serial ChannelProgrammable Watchdog TimerUp to 63 General Purpose I/O LinesSupported by a Large Range of Development Tools like C-Compilers, Macro-Assembler
Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer
Disassemblers, Programming BoardsAmbient Temperature Range 0 to 70 ˚C80-Pin MQFP Package (0.65 mm pitch)
This document describes the SAB-C161V-L16M, the SAB-C161K-L16M and the
SAB-C161O-L16M.For simplicity all versions are referred to by the term C161 throughout this document whenever
possible.
C166-Family of
High-Performance CMOS 16-Bit Microcontrollers
Preliminary
C161V, C161K, C161O 16-Bit Microcontrollers
C161
IntroductionThe C161 is a new derivative of the Siemens SAB 80C166 family of single-chip CMOS
microcontrollers. It combines high CPU performance (up to 8 million instructions per second) with
high peripheral functionality and enhanced IO-capabilities. The C161 derivatives are especially
suited for cost sensitive applications.
Figure 1
Logic Symbol
Ordering Information
Figure 2
Pin Configuration Square MQFP-80 Package (top view)
Note:The marked signals are not available on all C161 derivatives. Please refer to the detailed
description below.
Pin Definitions and Functions
Pin Definitions and Functions (cont’d)
Pin Definitions and Functions (cont’d)
Pin Definitions and Functions (cont’d)
Device Cross-Reference The table below describes the differences between the three derivatives described in this data
sheet. This table provides an overview on the capabilities of each derivative for a quick comparison.
Functional DescriptionThe architecture of the C161 combines advantages of both RISC and CISC processors and of
advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an
overview of the different on-chip components and of the advanced, high bandwidth internal bus
structure of the C161.
Note:All time specifications refer to a CPU clock of 16 MHz
(see definition in the AC Characteristics section).
Figure 3
Block Diagram
Memory OrganizationThe memory space of the C161 is configured in a Von Neumann architecture which means that
code memory, data memory, registers and I/O ports are organized within the same linear address
space which includes 4 MBytes. The entire memory space can be accessed bytewise or wordwise.
Particular portions of the on-chip memory have additionally been made directly bit addressable.
The C161 is prepared to incorporate on-chip mask-programmable ROM for code or constant data.
Currently no ROM is integrated.
On-chip RAM (2 KBytes in the C161O, 1 KByte in the C161V and the C161K) is provided as a
storage for user defined variables, for the system stack, general purpose register banks and even
for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL7, RH7) so-called General Purpose Registers (GPRs).
1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register
areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling
and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for
future members of the C161 family.
In order to meet the needs of designs where more memory is required than is provided on chip, up
to 4 MBytes of external RAM and/or ROM can be connected to the microcontroller.
External Bus ControllerAll of the external memory accesses are performed by a particular on-chip External Bus Controller
(EBC). It can be programmed either to Single Chip Mode when no external memory is required, or
to one of four different external memory access modes, which are as follows:
– 16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed(not in the C161V)
– 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed
– 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed
– 16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed(not in the C161V)
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on
PORT0. In the multiplexed bus modes both addresses and data use PORT0 for input/output.
Note:The C161V only provides multiplexed bus modes.
Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-
State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user
the adaption of a wide range of different types of memories. In addition, different address ranges
may be accessed with different bus characteristics. External CS signals (0, 2, 4, depending on the
device) can be generated in order to save external glue logic.
For applications which require less than 4 MBytes of external memory space, this address space
can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no
address lines at all. It outputs all 6 address lines, if an address space of 4 MBytes is used.
Central Processing Unit (CPU)The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C161’s instructions can be executed in just one
machine cycle which requires 125 ns at 16-MHz CPU clock. For example, shift and rotate
instructions are always processed during one machine cycle independent of the number of bits to
be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast
as well: branches in 2 cycles, a 16 · 16 bit multiplication in 5 cycles and a 32-/16 bit division in
10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution
time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 4
CPU Block Diagram
The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are
physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the
base address of the active register bank to be accessed by the CPU at a time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter passing,
a register bank may overlap others.
A system stack is provided as a storage for temporary data. The system stack is allocated in the on-
chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate
SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack
access for the detection of a stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently be utilized
by a programmer via the highly efficient C161 instruction set which includes the following instruction
classes:Arithmetic InstructionsLogical InstructionsBoolean Bit Manipulation InstructionsCompare and Loop Control InstructionsShift and Rotate InstructionsPrioritize InstructionData Movement InstructionsSystem Stack InstructionsJump and Call InstructionsReturn InstructionsSystem Control InstructionsMiscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words.
A variety of direct, indirect or immediate addressing modes are provided to specify the required
operands.
Interrupt SystemWith an interrupt response time within a range from just 315 ns to 750 ns (in case of internal
program execution), the C161 is capable of reacting very fast to the occurence of non-deterministic
events.
The architecture of the C161 supports several mechanisms for fast and flexible response to service
requests that can be generated from various sources internal or external to the microcontroller. Any
of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by
the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is suspended and
a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service. A PEC service implies a single byte or word data transfer between
any two memory locations with an additional increment of either the PEC source or the destination
pointer. An individual PEC transfer counter is implicity decremented for each PEC service except
when performing in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data. The C161
has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable flag and an
interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each
source can be programmed to one of sixteen interrupt priority levels. Once having been accepted
by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For
the standard interrupt processing, each of the possible interrupt sources has a dedicated vector
location.
Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling
edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
The following table shows all of the possible C161 interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:
Note:The shaded interrupt nodes are only available in the C161O,
not in the C161V and the C161K.
The C161 also provides an excellent mechanism to identify and to process exceptions or error
conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate
non-maskable system reaction which is similar to a standard interrupt service (branching to a
dedicated vector table location). The occurence of a hardware trap is additionally signified by an
individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in
progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap
services can normally not be interrupted by standard or PEC interrupts.
The following table shows all of the possible exceptions or error conditions that can arise during run-
time:
General Purpose Timer (GPT) UnitsThe GPT units represent a very flexible multifunctional timer/counter structure which may be used
for many different time related tasks such as event timing and counting, pulse width and duty cycle
measurements, pulse generation, or pulse multiplication.
Two separate modules, GPT1 and GPT2, are available (GPT2 on C161O only). Each timer in each
module may operate independently in a number of different modes, or may be concatenated with
another timer of the same module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three
basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the
input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while
Counter Mode allows a timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of
a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has
one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the
timers in module GPT1 is 500 ns (@ 16-MHz CPU clock).
The count direction (up/down) for each timer is programmable by software or may additionally be
altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking.
Figure 5
Block Diagram of GPT1Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/
underflow. The state of this latch may be output on a port pin (T3OUT) e.g. for time out monitoring
of external hardware components, or may be used internally to clock timers T2 and T4 for
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture
registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The
contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins
(TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or
by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to
alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM
signal, this signal can be constantly generated without software intervention.
Note:The C161V has no external connection for GPT1, ie. the related functions are not available.
Figure 6
Block Diagram of GPT2With its maximum resolution of 250 ns (@ 16 MHz), the
GPT2 module provides precise eventcontrol and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via
a programmable prescaler. The count direction (up/down) for each timer is programmable by
software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5. The overflows/underflows of timer T6 can
cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer
T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may
optionally be cleared after the capture procedure. This allows absolute time differences to be
measured or pulse multiplication to be performed without software overhead.
Note:The GPT2 module is only available on the C161O.
Parallel PortsThe C161 provides up to 63 I/O lines which are organized into six input/output ports and one input
port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise)
programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports
which are switched to high impedance state when configured as inputs. The output drivers of three
I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control
registers. During the internal reset, all port pins are configured as inputs.
All port lines have programmable alternate input or output functions associated with them. PORT0
and PORT1 may be used as address and data lines when accessing external memory, while Port 4
outputs the additional segment address bits A21/19/17...A16 in systems where segmentation is
enabled to access more than 64 KBytes of memory. Port 6 provides optional chip select signals.
Port 3 includes alternate functions of timers, serial interfaces and the optional bus control signal
BHE. Port 5 is used for timer control signals. All port lines that are not used for these alternate
functions may be used as general purpose I/O lines.
Watchdog TimerThe Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to
prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time
interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up
procedure is always monitored. The software has to be designed to service the Watchdog Timer
before it overflows. If, due to hardware or software related failures, the software fails to do so, the
Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low
in order to allow external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128.
The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in
WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced
by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals
between 32 ms and 524 ms can be monitored (@ 16 MHz). The default Watchdog Timer interval
after reset is 8.19 ms (@ 16 MHz).
Serial ChannelsSerial communication with other microcontrollers, processors, terminals or external peripheral
components is provided by two serial interfaces with different functionality, an Asynchronous/
Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).
The ASC0 is upward compatible with the serial ports of the Siemens 8-bit microcontroller familiesand supports full-duplex asynchronous communication at up to 500 KBaud and half-duplex
synchronous communication at up to 2 MBaud @ 16 MHz CPU clock.
A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning.
For transmission, reception and error handling 4 separate interrupt vectors are provided. In
asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and
terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish
address from data bytes has been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock
which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is
available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. A parity bit can automatically be generated on transmission or be
checked on reception. Framing error detection allows to recognize data frames with missing stop
bits. An overrun error will be generated, if the last character received has not been read out of the
receive buffer register at the time the reception of a new character is complete.
The SSC supports full-duplex synchronous communication at up to 4 Mbaud @ 16 MHz CPU clock.It may be configured so it interfaces with serially linked peripheral components. A dedicated baud
rate generator allows to set up all standard baud rates without oscillator tuning. For transmission,
reception and error handling 3 separate interrupt vectors are provided.
The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock which
can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can
start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock
edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. Transmit and receive error supervise the correct handling of the data
buffer. Phase and baudrate error detect incorrect serial data.
Instruction Set SummaryThe table below lists the instructions of the C161 in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation of the
instructions, parameters for conditional execution of instructions, and the opcodes for each
instruction can be found in the “C16x Family Instruction Set Manual”.
This document also provides a detailled description of each instruction.
Instruction Set Summary
Instruction Set Summary (cont’d)
