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SAB-C161PI-LFCA ,16-Bit MicrocontrollersC161PIMicrocontrollersC166 Family16-Bit Single-Chip MicrocontrollerC161PI Data Sheet 1999-07 Prel ..
SAB-C161PI-LM CA ,Consumer Class 16-bit MicrocontrollerBlock Diagram corrected24 Description of divider chain improved25, 51, 52 ADC description updated t ..
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SC605MLTRT , Charge Pump Flash LED Driver
SC606AIML.TRT , Low Noise Smart LED Driver with Serial Interface
SC606AIMLTRT , Low Noise Smart LED Driver with Serial Interface
SC606AIMLTRT , Low Noise Smart LED Driver with Serial Interface
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SC6121-002 ,stock - INFRARED REMOTE CONTROL TRANSMITTER
SAB-C161K-LM-SAB-C161O-LM-SAF-C161K-LM
16-Bit Microcontrollers
C161K
C161O
16-Bit Single-Chip Microcontroller
C161K/O
Revision History:2001-01V2.0
Previous Version:03.97(Preliminary)
09.96(Advance Information)
C161K/O16-Bit Single-Chip Microcontroller
C166 Family
C161K/OHigh Performance 16-bit CPU with 4-Stage Pipeline80 ns Instruction Cycle Time at 25MHz CPU Clock400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)Enhanced Boolean Bit Manipulation FacilitiesAdditional Instructions to Support HLL and Operating SystemsRegister-Based Design with Multiple Variable Register BanksSingle-Cycle Context Switching Support16 MBytes Total Linear Address Space for Code and Data1024 Bytes On-Chip Special Function Register Area16-Priority-Level Interrupt System with 20 Sources, Sample-Rate down to 40 ns8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)Clock Generation via prescaler or via direct clock inputOn-Chip Memory Modules2 KBytes On-Chip Internal RAM (IRAM) on C161O,
1 KByte IRAM on C161KOn-Chip Peripheral ModulesTwo Multi-Functional General Purpose Timer Units with 5 Timers on C161O,
one Timer Unit with 3 Timers on C161KTwo Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)Up to 4 MBytes External Address Space for Code and DataProgrammable External Bus Characteristics for Different Address RangesMultiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus WidthFour Programmable Chip-Select Signals on C161O,
two Chip-Select Signals on C161KIdle and Power Down ModesProgrammable Watchdog TimerUp to 63 General Purpose I/O LinesPower Supply: the C161K/O can operate from a 5V or a 3V power supplySupported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming BoardsOn-Chip Bootstrap Loader80-Pin MQFP Package (0.65 mm pitch)
This document describes several derivatives of the C161 group.
Table1 enumeratesthese derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
For simplicity all versions are referred to by the term C161K/O throughout this document.
Ordering InformationThe ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:the derivative itself, i.e. its function set, the temperature range, and the supply voltagethe package and the type of delivery.
For the available ordering codes for the C161K/O please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.Note:The ordering codes for Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Table1C161K/O Derivative SynopsisThis Data Sheet is valid for devices starting with and including design step HA.
IntroductionThe C161K/O is a derivative of the Infineon C166Family of full featured single-chip
CMOS microcontrollers. It combines high CPU performance (up to 12.5 million
instructions per second) with peripheral functionality and enhanced IO-capabilities. The
C161K/O is especially suited for cost sensitive applications.
Figure1Logic Symbol
Pin Configuration MQFP Package(top view)
Figure2Note:The marked signals are only available in the C161O.
Table2Pin Definitions and Functions
Table2Pin Definitions and Functions (cont’d)
Table2Pin Definitions and Functions (cont’d)
Note:The following behavioral differences must be observed when the bidirectional
reset is active:Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared
automatically after a reset.The reset indication flags always indicate a long hardware reset.The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap
loader may be activated when P0L.4 is low.Pin RSTIN may only be connected to external reset devices with an open drain output
driver.A short hardware reset is extended to the duration of the internal reset sequence.
Table2Pin Definitions and Functions (cont’d)
Functional DescriptionThe architecture of the C161K/O combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C161K/O.
Note:
All time specifications refer to a CPU clock of 25 MHz(see definition in the AC Characteristics section).
Figure3Block DiagramThe program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resources, the X-Peripherals (see Figure
3).
Memory Organization
The memory space of the C161K/O is configured in a Von Neumann architecture which
means that code memory, data memory, registers and I/O ports are organized within the
same linear address space which includes 16MBytes. The entire memory space can be
accessed bytewise or wordwise. Particular portions of the on-chip memory have
additionally been made directly bitaddressable.
The C161K/O is prepared to incorporate on-chip program memory (not in the ROM-less
derivatives, of course) for code or constant data. The internal ROM area can be mapped
either to segment0 or segment1.
On-chip Internal RAM (IRAM) is provided (1KByte in the C161K, 2KBytes in the
C161O) as a storage for user defined variables, for the system stack, general purpose
register banks and even for code. A register bank can consist of up to 16 wordwide (R0
to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers
(GPRs).
1024 bytes (2×512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the C166Family.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 4MBytes of external RAM and/or ROM can be connected to the
microcontroller.
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes, which are
as follows:16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/
output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses
and data use PORT0 for input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time,
Memory Tri-State Time, Length of ALE and Read Write Delay) have been made
programmable to allow the user the adaption of a wide range of different types of
memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs
ADDRSELx / BUSCONx) which control the access to different resources with different
bus characteristics. These address windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to
locations not covered by these 4 address windows are controlled by BUSCON0.
Up to 2 or 4 external CS signals (1 or 3 windows plus default, depending on the device)
can be generated in order to save external glue logic. The C161K/O offers the possibility
to switch the CS outputs to an unlatched mode. In this mode the internal filter logic is
switched off and the CS signals are directly generated from the address. The unlatched
CS mode is enabled by setting CSCFG (SYSCON.6).
For applications which require less than 4 MBytes of external memory space, this
address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case
Port4 outputs four, two, or no address lines at all. It outputs all 6 address lines, if an
address space of 4 MBytes is used.
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C161K/O’s instructions can be
executed in just one machine cycle which requires 80ns at 25MHz CPU clock. For
example, shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: branches in 2 cycles, a 16×16
bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline
optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure4CPU Block Diagram
The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.
These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed by
the CPU at any time. The number of register banks is only restricted by the available
internal RAM space. For easy parameter passing, a register bank may overlap others.
A system stack of up to 1024words is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the
stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection of a
stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient C161K/O instruction set which
includes the following instruction classes:Arithmetic InstructionsLogical InstructionsBoolean Bit Manipulation InstructionsCompare and Loop Control InstructionsShift and Rotate InstructionsPrioritize InstructionData Movement InstructionsSystem Stack InstructionsJump and Call InstructionsReturn InstructionsSystem Control InstructionsMiscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Interrupt System
With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of
internal program execution), the C161K/O is capable of reacting very fast to the
occurrence of non-deterministic events.
The architecture of the C161K/O supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source or the destination pointer. An individual PEC transfer
counter is implicity decremented for each PEC service except when performing in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The C161K/O has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via
its related register, each source can be programmed to one of sixteen interrupt priority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
Table3 shows all of the possible C161K/O interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note:Interrupt nodes which are not used by associated peripherals, may be used to
generate software controlled interrupt requests by setting the respective interrupt
request bit (xIR).
Note:The shaded interrupt nodes are only available in the C161O, not in the C161K.
Table3C161K/O Interrupt Nodes
The C161K/O also provides an excellent mechanism to identify and to process
exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.
Hardware traps cause immediate non-maskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The
occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
Table4 shows all of the possible exceptions or error conditions that can arise during run-
time:
Table4Hardware Trap Summary
General Purpose Timer (GPT) Unit
The GPT unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently in a
number of different modes, or may be concatenated with another timer of the same
module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer
to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 16TCL.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-
flow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components, or may be used internally to clock timers
T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite
state transitions of T3OTL with the low and high times of a PWM signal, this signal can
be constantly generated without software intervention.
Figure5Block Diagram of GPT1
With its maximum resolution of 8TCL, the GPT2 module provides precise event control
and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU
clock. The count direction (up/down) for each timer is programmable by software.
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5. The overflows/underflows of timer
T6 can cause a reload from the CAPREL register. The CAPREL register may capture
the contents of timer T5 based on an external signal transition on the corresponding port
pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This
allows the C161K/O to measure absolute time differences or to perform pulse
multiplication without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
Note:Block GPT2 is only available in the C161O, not in the C161K.
Figure6Block Diagram of GPT2
Serial Channels
Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by two serial interfaces with different functionality, an
Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous
Serial Channel (SSC).
The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller
families and supports full-duplex asynchronous communication at up to 781kBaud and
half-duplex synchronous communication at up to 3.1MBaud (@ 25MHz CPU clock).
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling 4 separate interrupt
vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or
received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a
shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop
back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
The SSC supports full-duplex synchronous communication at up to 6.25MBaud25MHz CPU clock). It may be configured so it interfaces with serially linked
peripheral components. A dedicated baud rate generator allows to set up all standard
baud rates without oscillator tuning. For transmission, reception, and error handling three
separate interrupt vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit and receive error supervise the correct handling
of the data buffer. Phase and baudrate error detect incorrect serial data.
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the EINIT (end of initialization) instruction has been
executed. Thus, the chip’s start-up procedure is always monitored. The software has to
be designed to service the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/128.
The high byte of the Watchdog Timer register can be set to a prespecified reload value
(stored in WDTREL) in order to allow further variation of the monitored time interval.
Each time it is serviced by the application software, the high byte of the Watchdog Timer
is reloaded. Thus, time intervals between 20µs and 336ms can be monitored25MHz).
The default Watchdog Timer interval after reset is 5.24ms (@25MHz).
Parallel Ports
The C161K/O provides up to 63 I/O lines which are organized into six input/output ports
and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of three I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.
PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port4 outputs the additional segment address bits A21/19/17…A16 in
systems where segmentation is enabled to access more than 64 KBytes of memory.
Port6 provides optional chip select signals.
Port3 includes alternate functions of timers, serial interfaces, and the optional bus
control signal BHE/WRH.
Port5 is used for timer control signals.
Instruction Set Summary
Table5 lists the instructions of the C161K/O in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “C166 Family Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table5Instruction Set Summary
Table5Instruction Set Summary (cont’d)
Special Function Registers Overview
The following table lists all SFRs which are implemented in the C161K/O in alphabetical
order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the
Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical
Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column
“Physical Address”.
An SFR can be specified via its individual mnemonic name. Depending on the selected
addressing mode, an SFR can be accessed via its physical address (using the Data
Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).
Note:The shaded registers are only available in the C161O, not in the C161K.
Table6C161K/O Registers, Ordered by Name
Table6C161K/O Registers, Ordered by Name (cont’d)
Table6C161K/O Registers, Ordered by Name (cont’d)
The system configuration is selected during reset.The reset value depends on the indicated reset source.Table6C161K/O Registers, Ordered by Name (cont’d)
Absolute Maximum Ratings
Note:Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the
voltage on VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Table7Absolute Maximum Rating Parameters
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the C161K/O. All parameters specified in the following sections refer to
these operating conditions, unless otherwise noticed.
Table8Operating Condition ParametersOutput voltages and output currents will be reduced when VDD leaves the range defined for active mode.Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV>VDD +0.5V or VOVcurrents on all pins may not exceed 50mA. The supply voltage must remain within the specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR,
etc.Not 100% tested, guaranteed by design and characterization.
