SAA7146AH ,Multimedia bridge, high performance Scaler and PCI circuit (SPCI)FEATURES1.1 Video processing• Full size, full speed video delivery to and from the framebuffer or v ..
SAA7146AH ,Multimedia bridge, high performance Scaler and PCI circuit (SPCI)applications• Colour space conversion with gamma correction for• Horizontal and vertical FIR filter ..
SAA7146AH ,Multimedia bridge, high performance Scaler and PCI circuit (SPCI)FUNCTIONAL DESCRIPTION14.4 Manual soldering7.1 General14.5 Suitability of surface mount IC packages ..
SAA7146AHZ ,Multimedia bridge, high performance Scaler and PCI circuit SPCIINTEGRATED CIRCUITSDATA SHEETSAA7146AMultimedia bridge, highperformance Scaler and PCI circuit(SPCI ..
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SAA7146AH-SAA7146AHZ
Multimedia bridge, high performance Scaler and PCI circuit (SPCI)
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
CONTENTS FEATURES
1.1 Video processing
1.2 Audio processing
1.3 Scaling
1.4 Interfacing
1.5 General GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION
7.1 General
7.2 PCI interface
7.3 Main control
7.4 Register Programming Sequencer (RPS)
7.5 Status and interrupts
7.6 General Purpose Inputs/Outputs (GPIO)
7.7 Event counter
7.8 Video processing
7.9 High Performance Scaler (HPS)
7.10 Binary Ratio Scaler (BRS)
7.11 Video data formats on the PCI-bus
7.12 Scaler register
7.13 Scaler event description
7.14 Clipping
7.15 Data Expansion Bus Interface (DEBI)
7.16 Audio interface
7.17 I2 C-bus interface
7.18 SAA7146A register tables BOUNDARY SCAN TEST
8.1 Initialization of boundary scan circuit
8.2 Device identification codes LIMITING VALUES ELECTRICAL OPERATING CONDITIONS CHARACTERISTICS APPLICATION EXAMPLE PACKAGE OUTLINE SOLDERING
14.1 Introduction to soldering surface mount
packages
14.2 Reflow soldering
14.3 Wave soldering
14.4 Manual soldering
14.5 Suitability of surface mount IC packages for
wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2 C COMPONENTS
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
FEATURES
1.1 Video processing Full size,full speed video deliveryto and from the frame
buffer or virtual system memory enables various
processing possibilities for any external PCI device Full bandwidth PCI-bus master write and read (up to
132 Mbytes/s) Virtual memory support (4 Mbytes per DMA channel) Processing of maximum 4095 active samples per line
and maximum 4095 lines per frame Vanity picture (mirror) for video phone and video
conferencing applications Video flip (upside down picture) Colour space conversion with gamma correction for
different kinds of displays Chroma Key generation and utilization Pixel dithering for low resolution video output formats Brightness, contrast and saturation control Video and Vertical Blanking Interval (VBI) synchronized
programming of internal registers with Register
Programming Sequencer (RPS), ability to control two
asynchronous data streams simultaneously Memory Management Unit (MMU) supports virtual
demand paging memory management (Windows, Unix,
etc.) Rectangular clipping of frame buffer areas minimizes
PCI-bus load Random shape mask clipping protects selectable areas
of frame buffer3× 128 Dword video FIFO with overflow detection and
‘graceful’ recovery.
1.2 Audio processing Time Slot List (TSL) processing for flexible control of
audio frames up to 256 bits on 2 asynchronous
bidirectional digital audio interfaces simultaneously DMA channels) Video synchronous audio capture, e.g. for sound cards Various synchronization modes to support I2S-bus and
other different audio and DSP data formats Audio input level monitoring enables peak control via
software Programmablebit clock generationfor master and slave
applications.
1.3 Scaling Scaling of video pictures down to randomly sized
windows (vertical down to 1: 1024; horizontal down to: 256) High Performance Scaler(HPS) offers two-dimensional,
phase correct data processing for improved signal
qualityof scaled video data, especiallyfor compression
applications Horizontal and vertical FIR filters with up to 65 taps Horizontal upscaling (zoom) supports e.g. CCIR to
square pixel conversion Additional Binary Ratio Scaler (BRS) supports CIF and
QCIF formats, especially for video phone and video
conferencing.
1.4 Interfacing Dual D1 (8-bit, CCIR 656) video I/O interface DMSD2 compatible (16-bit YUV) video input interface Supports various packed (pixel dithering) and planar
video output formats DataExpansion BusInterface (DEBI)for interfacingwith
e.g. MPEG or JPEG decoders with Intel (ISA like) and
Motorola (68000 like) protocol style, capability for
immediate and block mode (DMA) transfers with up to Mbytes/s peak data rate5 digital audio I/O ports4 independent user configurable General Purpose I/O
Ports (GPI/O) for interrupt and status processing PCI interface (release 2.1)I2 C-bus interface (bus master).
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
1.5 General Subsystem (board) vendor ID support for board
identification via software driver Internal arbitration control Diagnostic support and event analysis Programmable Vertical Blanking Interval (VBI) data
region for e.g. to support INTERCAST, teletext, closed
caption and similar applications 3.3 V supply enables reduced power consumption, 5V
tolerant I/Os for 5 V PCI signalling environment.
GENERAL DESCRIPTIONThe SAA7146A, Multimedia PCI-bridge, is a highly
integrated circuit for DeskTop Video (DTV) applications.
The device provides a number of interface ports that
enable a wide variety of video and audio ICs to be
connected to the PCI-bus thus supporting a number of
video applicationsina PC. One exampleof the application
capabilities is shown in Fig.48.
Figure 1 shows the various interface ports and the main
internal function blocks.
QUICK REFERENCE DATA ORDERING INFORMATION
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
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BLOCK DIAGRAM
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
PINNING
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
Notes For continuous CCIR 656 format at the D1_A port this pin must be set HIGH. For continuous CCIR 656 format at the D1_B port this pin must be set HIGH.
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A FUNCTIONAL DESCRIPTION
This chapter provides information about the features
realized with this device. First, a general, thus short,
description of the functionality is given. The following
sections deal with the single featuresina detailed manner.
7.1 General
The Dual D1 (DD1) interface can be connected to digital
video decoder ICs suchas the SAA7111A, SAA7113 and
SAA7115 digital video encoder such as the SAA7128A
and SAA7129A, video compression CODECs or to aD1
compatible connector, e.g. for interconnection to an
external digital camera.
Theinterfacesupportsbidirectionalfull duplex twochannel
full D1 (CCIR 656), optionally with separate sync lines
H/V, pixel qualifier signal and double pixel clock I/O,upto MHz.
Oneof the two internal video processorsof the SAA7146A
is the two-dimensional High Performance Scaler (HPS).
Phase accurate re-sampling by interpolation supports
independent horizontal up and downscaling. In the
horizontal direction the scaling process isperformedin two
functional blocks: integer decimationby window averaging
(up to 65 tap), and phase linear interpolation (10 tap filter
for luminance, 6 tap filter for chrominance). The vertical
processing for downscaling either uses averaging over a
window (up to 65 tap) or linear interpolation (2 tap).
The scaling function canbe usedfor random sized display
windowing, for horizontal upscaling (zoom) or for
conversion between various sample schemes such as
CCIR or SQP. Incorporated with the HPS function is
brightness, contrast and saturation control. Colour key
generationis also established. The outputof the HPS can
be formatted in various RGB and YUV formats.
Additionally, this output can be dithered for low bit rate
formats. Packed formats as well as planar formats (YUV)
are supported.
A second video channel (YUV4:2:2 format) bypasses
the HPS and connects the real time video interface with
the PCI interface. This video bypass channel, using the
second video processor Binary Ratio Scaler (BRS), is
bidirectional and has meansto convert fromfull size video
(50or60 Hz) to Common Interchange Format (CIF),
Quarter Common Interchange Format (QCIF) or Quarter
Quarter Common Interchange Format (QQCIF) and vice
versa (binary ratio 1,2,4,8,1⁄2,1⁄4 and1⁄8 only). Multiple
programmable VBI data and test signal regions can be
bypassed without processing during each field.
The bidirectional digital audio serial interface is based on
the I2S-bus standard, but supports flexible programming
for various data and timing formats.
Two independent interface circuits control audio data
streamingofupto2× 128-bit frame width (bidirectionalor
simultaneous input/output). Five or more I2 S-bus devices
suchas the UDA1345, UDA1355 and UDA1380 (ADC and
DAC) and UDA1334 (DAC) can be connected.
The peripheral data port [Data Expansion Bus Interface
(DEBI)] enables 8or 16-bit parallel access for system
set-up and programmingof peripheral multimedia devices
(behind SAA7146A), butis also highly capableto interface
compressed MPEG/JPEG data of peripheral ICs with the
PCI system. DEBI supports both Intel compatible (ISA-bus
like) and Motorola (68000 style) compatible handshaking
protocols with up to 23 Mbytes/s peak data rate. Besides
the parallel port, thereis alsoanI2 C-bus portto controlvia
the standard protocol external devices with speeds of up
to 400 kbit/s.
The PCI interface has master read and master write
capability. The video signal flowsto and from the PCI and
is controlled by three video DMA channels with a total
FIFO capacity of 384 Dwords. The video DMA channel
definition supports the typical video data structure
(hierarchy) of pixels, lines, fields and frames. The audio
signal flowis controlledby four audio DMA channels, each
with 24 Dwords FIFO capacity. The DEBI port is
connected to the PCI by single instruction direct access
(immediate mode) and via a data DMA channel for
streaming data (block mode) with 32 Dwords FIFO
capacity. To improve PCI-bus efficiency, an arbiter
schedules the access to PCI-bus for all local DMA
channels.
The PCI interface of the SAA7146A supports virtual
memory addressing for operating systems running virtual
demand paging. The integrated Memory Management
Unit (MMU) translates linear addressing to physical
addresses using a page table inside the system memory
providedby the software driver. The MMU supportsupto Mbytes of virtual address space per DMA channel.
The SAA7146A can changeits programming sets usinga
Register Programming Sequencer (RPS) that works by
itself on a user defined program controlled by internally
supported real time events. The SAA7146A has two RPS
machines to optimize flow control of e.g. an MPEG
compressed data stream and real time video scaling
control. The RPS programmingis definedbyan instruction
list in the system main memory that consists of multiple
RPS commands.
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
7.2 PCI interface
This section describes the interface of the SAA7146A to
the PCI-bus. This includes the PCI modules, the DMA
controls of the video, audio and data channels, the
Memory Management Unit (MMU) and the Internal
Arbitration Control (INTAC). The handling of the FIFOs
and the corresponding errors are also described andalist
of all DMA control registers is given.
7.2.1 PCI MODULES AND CONFIGURATION SPACE
The SAA7146A providesa PCI-bus interface having both
slave and master capability. The master and the slave
module fulfil the PCI local bus specification revision 2.1.
They decode the C/BE# lines to provide a byte-wise
accessand support 32-bit transfers uptoa maximum clock
rate of 33 MHz. To increase bus performance, they are
able to handle fast back-to-back transfers.
During normal operation the SAA7146A checks for parity
errors and reports them via the PERR# pin.Ifan address
parity error is detected the SAA7146A will not respond.
Using the SAA7146A as a slave, access is obtained only
to the programmable registers and to its configuration
space. Video, audio and other data of the SAA7146A
reads/writes autonomously via the master interface (see
Fig.3). The useof the PCI master module, i.e. which DMA
channel gets access to the PCI-bus, is controlled by the
INTAC (see Section 7.2.5).
The registers described in Table 1 are closely related to
the PCI specification.It shouldbe noted that Header type,
Cache Line Size, BIST, Card bus CIS Pointer and
Expansion ROM Base Address Registers are not
implemented.All registers, which are not implemented are
treatedas read only witha valueof zero. Some values are
loaded after PCI reset via I2 C-bus from EEPROM with
device address 1010000 (binary). This loading will take
approximately 1 ms at 33 MHz PCI clock. If any device
triesto reador write data fromorto the SAA7146A during
the loading phase after reset, the SAA7146A will
disconnect with retry.
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
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Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
Table 1 Configuration space registers
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
7.2.2 VIDEO DMA CONTROL
The SAA7146A’s DMA control is able to support up to
three independent video targets or sources respectively.
For this purpose it provides three video DMA channels.
Each channel consists of a FIFO, a FIFO Input Control
(FINC) placed on the video side of the FIFO, and a FIFO
Control (FICO) placed on the PCI side of the FIFO.
Channel 1 only supports the unidirectional data stream
into the PCI memory. It is not able to read data from
system memory. However, this access is possible using
Channels2or 3. Table 2 surveys the possibilities and
purposes of each video DMA channel.
Each FIFO, i.e. each DMA channel, has its own
programming set including base address (doubledfor odd
and even fields), pitch, protection address, page table
base address, several handling mode control bits and a
transfer enablebit (TR_E).In addition, each channel hasa
threshold and a burst length definition for internal
arbitration (see Table 6, Section 7.2.5).
To handle the reading modes FIFO 2 and FIFO 3 offer
some additional registers: Number of Bytes per line
(NumBytes), Number of Lines per field (NumLines) and
the vertical scaling ratio (only FIFO 3, see Table 69).
The programming sets could be reloaded after the
previous job is done [Video Transfer Done (VTD)] to
support several DMA targets per FIFO. The programming
set currently usedis loadedby the Register Programming
Sequencer (RPS). If the RPS is not used, the registers
could be rewritten each time, using the SAA7146A as a
slave. But then the programmer must take care of the
synchronization of these write accesses.
All registers needed for DMA control are described in
Table 3, except the transfer enable bits, which are
describedin Table 10. The registers are accessed through
PCI base address with appropriate offset (see Table1).
Table 2 Size, direction and purpose of the video FIFOs and the associated DMA controls
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
Table 3 Video DMA control registers
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
The video channels provide 32 bits of data signals and bits of Byte Enable (BE) signals, End-Of-Line (EOL),
End-Of-Window (EOW), Begin-Of-Field (BOF),
Line-Locked Clock (LLC), Odd/Even signal (OE) and a
Valid Data (VD) signal.To starta video data transfer, e.g.
via video DMA Channel 3, this channel must first be
included in the internal arbitration scheme. This is
achieved by setting the corresponding TR_E bit
(see Table 10).Ifa TR_Ebitis not set, the corresponding
FIFO is reset.
In read mode, which is offered by Channels2 and 3, the
FICO requests a PCI transfer with the next BOF. Data is
providedby the PCI master module. The FICO calculates
the PCI address autonomously, starting with the base
addressof the corresponding field. Only the received data
will be filled into the FIFO. FIFO 3 offers the possibility to
read video information from PCI memory, e.g. from the
frame buffer. This could be achieved by using the
NumBytes and the NumLines register, which defines the
sizeof the source picture,so that the DMA controlis able synchronize itselfto the source frame. FIFO2 does the
same if reading clip information from memory.
To support the Binary Ratio Scaler (BRS) included in the
SAA7146A, which only provides the possibility of
horizontal upscaling, the DMA control3 canbe appliedto
perform line repetition by reading lines up to four times
from PCI memory. This featureis controlledby the vertical
scaling ratio in outbound mode (see Table 69). This ratio
specifies the number of times each line should be read:= only once, 01= twice, and so on.
In the event of FIFO underflow, i.e. if the BRS or the
clipping unit respectively triesto read data from the FIFO,
even if the DMA control was not able to fill any data until
that moment, the reading unit triesto synchronize itselfto
the outgoing data streamas soonas possible.In this way
the readingof invalid datais minimized.If the clipping unit
receives no data, it will disable the associated pixels.
The behaviour of the BRS depends on the selected read
mode which is described in Section 7.10.
In the event of FIFO overflow, i.e. if the scaler tries to
transfer data although the FIFO is full, the FIFO input
control locks the FIFOfor the incoming data. During FIFO
overflow the PCI address of the incoming data will be
increased, over writing itself each time, if the scaler
transfers data, which has been clipped, the same
mechanism is used to improve PCI performance.
The SAA7146A is able to handle a negative pitch.
With that, top-down-flipof the transmitted fieldsor frames possible.A negative pitch (MSB=1) leadstoa different
definition of the protection and the base address, as
shownin Fig.4.If using negative pitch the first line startsat
base address+ pitch.
In ‘none-RPS’ mode the SAA7146A supports the
displaying of interlaced video data by using the two
different base addresses (BaseOdd and BaseEven) and
vertical start phases (YPE6to YPE0 and YPO6to YPO0)
for odd and even fields.
Using the protection address, system memory could be
keptof from prohibited write accesses.If the PCI pointerof
the current transfer reaches or exceeds the protection
address, the SAA7146A stops this transfer and an
interrupt is initiated. No interrupt is set if a protection
violation occurs due to the programming that was done
before the channel has been switched on.To prevent one
field from being transferred into memory, set its base
address (BaseOddor BaseEven)to the same valueas the
protection address.
If the Protection Violation (PV) handling bit and the limit
register are reset, the following data will be ignored until
detection of the End-Of-Window (EOW) signal. In read
mode the DMA control also waitsfor thissignal,to start the
next data transfer.If the PVbitis set, the inputof the FIFO
willbe locked and the FIFO willbe emptied.If the FIFOis
empty the TR_Ebitis reset. This feature couldbe usedfor
a single capture mode, if the protection address is the
same address as the last pixel in this field. With that, the
SAA7146A will write one field into system memory and
then stop. the limit registerof any DMA channel (video, VBI dataor
audio) has a value other than ‘0000’ the continuous write
mode is chosen. If the actual PCI address hits the
protection address and the PVbitis zero, the FINC stops
the current transfer, setsan interrupt and resets the actual
address to the base address. Regarding this, the
protection address could be used to define a memory
space to which data is sent. The SAA7146A offers the
possibilityto monitor the filling levelof this memory space.
The limit register definesan address limit, which generates
an interrupt if passed by the actual PCI address pointer.
‘0001’ means an interrupt will be generated if the lower bits (64 bytes) of the PCI address are zero. ‘0010’
defines a limit of 128 bytes, ‘0011’ one of 256 bytes, andonupto1 Mbyte definedby ‘1111’. This interrupt range
can be calculated as follows:
Range=2(5+ Limit) bytes.
The protection handling modes suchas those selectedby
the PVbit and the contentsof the limit register are shown
in Table4.
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
Table 4 Protection violation handling modes
Note X= don’t care.
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
7.2.3 AUDIO DMA CONTROL
The SAA7146A providesupto four audio DMA channels,
each using a FIFO of 24 Dwords. Two channels are read
only (A1_in and A2_in) and two channels are write only
(A1_out and A2_out). Because audio represents a
continuous data stream, which is neither line nor field
dependent, the audio DMA control offers only one base
address (BaseAxx) and no pitch register. For FIFO
overflow and underflow the handling of these channels is
done in the same way as the video DMA channels
(see Section 7.2.2).
The protection violation handling differs only if the limit
register and thePVbit are programmedto zero. The audio
DMA channel does not wait for the EOF signal, like the
video ones. It does not generate interrupts. The interrupt
range specifiedby the limit registeris definedin the same
way as described in Section 7.2.2. The audio DMA
channels try immediately to transfer data after setting the
transfer enable bits. All registers for audio DMA control,
which are the base address, the protection address and
the control bits are listed in the following Table 5, except
the input control bits (Burst, Threshold), which are listedin
Table6.
Table 5 Audio DMA control register
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
7.2.4 MEMORY MANAGEMENT UNIT (MMU)
7.2.4.1 Introduction perform DMA transfers, physically continuous memory
space is needed. However, operating systems such as
Microsoft Windows are working with virtual demand
paging, using a MMU to translate linear to physical
addresses. Memory allocation is performed in the linear
address space, resulting in fragmented memory in the
physical address space. Thereisno wayto allocate large
buffersof physical, continuous memory, except reserving
it during system start-up. Thus decreasing the system
performance dramatically. To overcome this problem the
SAA7146A contains a Memory Management Unit (MMU)
as well. This MMU is able to handle memory fragmented
to 4 kbyte pages, similar to the scheme used by the Intel
8086 processor family. The MMU can be bypassed to
simplify transfers to non-paged memory such as the
graphics adapter’s frame buffer.
7.2.4.2 Memory allocation
The SAA7146A’s MMU requires a special scheme for
memory allocation. The following steps have to be
performed: Allocationofn pages, each page being4 kbytesof size,
aligned to a 4 kbyte boundary Allocation of one extra page, to be used as page table Initialization of the page table.
Allocation of pages is done in physical address space.
Operating systems implementing virtual memory provide
services to allocate and free these pages.
The page tableis storedina separate page. This limits the
linear address pagetoa sizeof4 Mbytes and resultsina kbyte overhead. The page tableis organizedasan arrayn Dwords, with each entry giving the physical addressof
one of the n pages of allocated memory. As pages are
aligned to 4 kbytes, the lower 12 bits of each entry are
fixed to zero.
7.2.4.3 Implementation
The SAA7146A has up to 8 DMA channels (3 video, audio and 1 DEBI channel) for which the memory
mappingis done.Each ofthem provides the linear address (from) whichit wantsto send (read) data during the next
transfer. Their register sets contain a page table base
address (Pagexx) and a mapping enable bit (MExx).
If MExx is set, mapping is enabled.
The MMU checks for each channel whether its address
has been already translated. If translated, its request can
passto the Internal Arbitration Control (INTAC) managing
the access to the PCI-bus. If not, the MMU starts a bus
transfer to the page table. The page table entry address
could be calculated from the channels PCI address and
the page tablebase address,as shownin Fig.5. The upper bits of the PCI address are replaced by the upper bits of the according page address to generate the
mapped PCI address.
If the PCI address crosses a 4 kbyte boundary during a
transfer, the MMU stops this transfer and suppresses its
request to the INTAC until it has renewed the page
address, which means replacing the upper 20 bits of the
current address.To reduce latency the SAA7146A willdo
a pre-fetch, i.e. it will always try to load the next page
address in advance.
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
Philips Semiconductors Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI) SAA7146A
7.2.5 INTERNAL ARBITRATION CONTROL
The SAA7146A hasupto three video DMA channels, four
audio DMA channels and threeother DMA channels (RPS,
MMU and DEBI) each tryingto get accessto the PCI-bus.
To handle this, an Internal Arbitration Control (INTAC) is
needed. INTAC controls on the one hand the PCI-bus
requests and on the other hand the order in which each
DMA channel gets access to the bus.
The basic implementationof the internal arbitration control
is a round-robin mechanism on the top, consisting of the
RPS, the MMU and one of the eight data channels. Data
channel arbitration is performed using a ‘first come first
serve’queue architecture,which may consist ofupto eight
entries.
Each data channel reaching a certain filling level of its
FIFO definedby the threshold,is allowedto makean entry
into the arbitration queue. The threshold defines the
numberof Dwords neededto starta sensible PCI transfer
and mustbe small enoughto avoida lossof data duetoan
overflow regarding the PCI latency time. After each job
(Video Transfer Done, VTD) the video channels havetobe
emptied and are allowed to fill an entry into the queue,
even if they have not yet reached their threshold.
Concurrently to the entry the channel sets a bit which
prohibits further entriesto this channel.In the worst case,
each data channel can have only one entry in the queue. each channel wantsto access the bus, which means the
queue is full, an order like the one shown below will be
given. MMU RPS.
First entry of the data channel queue: MMU RPS.
Second entry of the data channel queue: MMU and so on. INTAC detectsat least one DMA channelin the queueor MMUoran RPS request,it signals the needfor the bus
by setting the REQ# signal on the PCI-bus. If the GNT#
signal goes LOW, the SAA7146A is the owner of the bus
and makes the PCI master module working with the first
channel selected. The master module triesto transfer the
numberof Dwords definedin the Burst Register. For RPS
the burst length is hardwired to four and for the MMU it is
hardwired to two Dwords. After that the master module
stops this transfer and starts a transfer using the next
channel (due to the round-robin).
If a DMA channel gets its transfer stopped due to a retry,
the arbitration control sets the corresponding retry flag.
INTAC tries to end a retried transfer, even if this transfer
gets stopped via the Transfer Enable bit (TR_E). For this
reason the Transfer Enable bits are internally shadowed INTAC.A transfer can onlybe stoppedifit hasno retry
pending.
The Arbitration Control Registers (Burst and Thresholdof
DEBI, Video 1to 3, Audio 1to 4) are listed in Table6.
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Table 6 Arbitration control registers
Table 7 Burst length definition
Table 8 Threshold definition
Note The threshold is reached, if the FIFO contains at least this number of Dwords.
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7.2.6 STATUS INFORMATIONOF THE PCI INTERFACE
Table9 lists the status information that the PCI interface makes availableto the userin additionto the interrupt sources
that are described later. This information is read only.
Table 9 Status bits of the DMA control
7.3 Main control
7.3.1 GENERAL
The SAA7146A has two Dwords of general control to
support quick enable/disable switching of any activity of
the SAA7146A via direct accessby the CPU. These main
control Dwords are splitin two parts. The upper parts have bits of bit-mask to allow bit-selective write to the lower
part which contains single bit enable/disable control of
major interface functions of SAA7146A. If a certain bit
positionis masked witha logic1in the mask word (upper bytes) duringa write access, then the correspondingbit the control word (lower2 bytes)is changed accordingto
the contentsof the transmitted data.By that the CPU can
easily switch on or off certain selected interfaces of the
SAA7146A without checking the actual ‘remaining’
programming (enabling) of the other parts.
The programming of registers for the 3 Video DMA
channels, both video processors (HPS, BRS) and for the
interfaces DEBI and I2 C-bus is performed by an upload
method. Thisis doneto guarantee coherent programming
data. During initiation of an upload operation from a
shadow RAM each of the UPLD bits [10to 0] (see
Table 11) is assigned to a set of registers. If a logic 1 is
written into a UPLD bit all dedicated shadow RAM
registers containing changed data are uploaded into their
working registers immediately. During a read cycle the
UPLD bits give information on whether the shadow RAM
contains changed data not yet uploaded into the working
registers. The UPLD bits remain HIGH as long as the
contents of the shadow RAM represents the current
programming.
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Table 10 Main control register1
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Table 11 Main control register2
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7.4 Register Programming Sequencer (RPS)
The RPS is used as an additional method to program or
read the registers of the SAA7146A. Its main function is
programming the registers on demand without delay via
the interrupt handler of the host system.
Because different applications of the SAA7146A can run
independently on and asynchronously to each other the
RPS is capable of running two parallel tasks. Both tasks
are completely equal to each other and each has its own
set of registers (RPS address, RPS page, HBI threshold
and RPS time out value). Each task can be separately
enabledby settingits related ERPSxbitin the Main control
register 1 (see Table 10). To allow communication
between both tasks and the CPU there are five signals
which canbe setor reset from both tasks (see Table 11).
The programmingofa taskis definedbyan instructionlist
in the system main memory that consists of RPS
commands. The operation of the RPS is initiated on
commandby setting the ERPSbitof the desired taskin the
Main control register1.
The processing of RPS can be controlled by a sequence
of wait commands on special events. Furthermore the
program flow can be controlled via conditional jumps
related to the communication with the host setting
semaphores or special internal interrupts.
7.4.1 RESET
During a reset the ERPSx (Enable RPS of task ‘x’) bits in
the Main control register 1 (see Table 10) of the
SAA7146A are cleared so that an RPS task has to be
explicitly started.
7.4.2 EVENT DESCRIPTION
Table12 shows the events available during the execution
of an RPS program. The execution can for example wait
on these events to become true. In general these events
are setifa rising edgeof the corresponding signal occurs
and are cleared if a falling edge of the signal occurs. signals are logic HIGH after the reset andno rising edge
occurs the corresponding event (available in an RPS
program execution) will not be set.
Table 12 Description of events
NoteIfan RPS programis usedto make DEBI transfer consecutive data blocks employ the following commands: LOAD
REGISTER, CLEAR SIGNAL, UPLOAD and PAUSE. Before uploading the register contents the DEBI_DONE flaga former transfer hastobe cleared. With this, the following PAUSE command waits correctlyfor DEBI_DONEof
the just started DEBI block transfer.
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7.4.3 COMMAND LIST
An instruction list of an RPS task is built in the system
memory by the device driver. This list is made up of
command sequences; each command being at least one
Dword long. The first Dwordofa command consistsof the
instruction code (4-bit) and a command specific part
(28 bits). Commands longer than one Dword contain data
in the additional Dwords.
Table 13 Command Dword
7.4.4 THE INSTRUCTION CODE
The instruction code identifies one of the following
commands (see bits31to 28 of Tables14to 29).
7.4.4.1 PAUSE
The PAUSE command is a one Dword command. This
command contains in the command specific part the
eventsto wait for; see Tables14 and 15. The executionof
the RPS task is delayed until the condition addressed via
the events becomes true or a time out occurs.
To control the time a PAUSE command stays in the wait
state,itis possibleto seta RPS time out value. This value
specifies after how many PCI clocks and/or V_syncs a
time out willbe asserted. Whenit occurs the RPS_TO bits the PSR (see Table 38)is set andif enabledan interrupt
will be generated. However, the RPS will stop this task.
The OAN bit specifies if the condition in bits25to 0 is an
AND (OAN setto0)orif the conditionisan OR (OAN set 1). If the INV bit is set this command will wait for the
condition to become false.
7.4.4.2 UPLOAD
The UPLOAD command is a one Dword-command. This
command contains in the command specific part the
sections to be uploaded from the shadow RAM to the
working registers, see Tables16 and 17.
If the UPLOAD command finds a bit of a section set it
uploads the corresponding registers from the shadow
RAM to the working registers. This is done for registers
with changed shadow RAM values only.
7.4.4.3 CHECK-LATE
The CHECK_LATE command is a one Dword-command.
This command containsin the command specific part the
events to check and if necessary to wait for, as shown in
Tables18 and 19. The execution of the RPS task is
delayed until the condition addressed via the events
becomes true, or a time out occurs and the upload is
performed.
The OAN bit specifies if the condition in bits25to 0 is an
AND (OAN setto0)orif the conditionisan OR (OAN set 1). If the INV bit is set this command will wait for the
condition to become false.
If the CHECK_LATE command finds that the wait
conditionis already true the RPS-LATEis set. Otherwiseit
waitsfor the conditionas the PAUSE command.A time out
behaviour such as described for the PAUSE command is
also supplied.
7.4.4.4 CLR_SIGNAL
The CLR_SIGNAL Command clears the selected signals.
This will not affect the real status bits of the SAA7146A.
Only a copy of this bit related to the RPS will be cleared. willbe set again viaa SET_SIGNAL commandor when
the real status will be set due to normal processing.
The CLR_SIGNAL format is shown in Tables 20 and 21.
7.4.4.5 NOP
The NOP command consists of one Dword and has the
instruction code 0000. All bits of the command specific
part have to be set to zero. This command is a special
case of the CLR_SIGNAL command.
7.4.4.6 SET_SIGNAL
The SET_SIGNAL command sets the selected signals.
If one of the SAA7146A status related signals is selected
to be set, it will not affect the real status bit of the
SAA7146A. Onlya copyof thisbit relatedto the RPS, will
be set. The SET_SIGNAL format is shown in
Tables22 and 23.
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7.4.4.7 INTERRUPT
The INTERRUPT command will set the RPS_I bit of the
task in the Interrupt status register (see Table 41) if it is
executed and the condition describedby the event flagsis
true. The execution of RPS continues. The format of the
Interrupt command is shown in Tables24 and 25.
The OAN bit specifies if the condition in bits25to 0 is an
AND (OAN setto0)orif the conditionisan OR (OAN set 1). If the INV bit is set this command will wait for the
condition to become false.
7.4.4.8 STOP
TheSTOP command will terminate the RPSexecution and
reset the ERPS-bit. The command specific part of the
STOP commandis like the INTERRUPT command.If the
addressed event is true the STOP will be executed
otherwise the execution will continue with the next
command. If no event is addressed the STOP will be
executed unconditionally. The format of the STOP
command is shown in Tables26 and 27.
The OAN bit specifies if the condition in bits 25to 0 is an
AND (OAN setto0)orif the conditionisan OR (OAN set 1). If the INV bit is set this command will wait for the
condition to become false.
7.4.4.9 JUMP
The JUMP command is a two Dword command.
The second Dword contains the physical addressat which
the RPS will continue its execution. The address in the
second Dword is directly transferred to the RPSAddr
Register. The command specific part in the first Dword of
the JUMP command is like the INTERRUPT command. the addressed eventis true the JUMP willbe performed
otherwise the execution will continue at the next
command. If no event is addressed the JUMP will be
unconditional. The formatof the JUMP commandis shown
in Tables28 and 29.
The OAN bit specifies if the condition in bits 25 to 0 is an
AND (OAN setto0)orif the conditionisan OR (OAN set 1). If the INV bit is set this command will wait for the
condition to become false.
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7.4.4.10 LDREG and STREG
The Load Register (LDREG) command has a variable
Dword count specified by the Block_length. It is at least
two Dwords long and at maximum 256 Dwords.
The LDREG command interprets the following Dwordsas
data and writes itto the registers beginningat the specified
register address (D6to D0).
The Store Register (STREG) command is a two Dword
command. It transfers the contents of the addressed
(D6to D0) SAA7146A register into PCI memory that is
addressed by interpreting the contents of the next data
Dword as the 32-bit target base address.
To perform STREG by two
different tasks, a kind ofarbitration with two semaphore signals is necessary.
The Block_length entry defines the number of data
Dwords to be processed by these commands. This
enables the access to multiple registers on following
addresses within a single RPS command. The value
specified mustbeat least one.If more than one Dwordis
accessed the register addressis incremented each cycle.
A value of zero is reserved and the command will be
interpreted as NOP.
The register address defines the target register addressin
Dwords.If this address points toanon-existent register the
RPS_RE (read error)bitfor the actual task willbe set and enabled aninterrupt willbe generated. The command will
be ignored and the execution of RPS continues.
All reserved bits shouldbe writtenas zeros and shouldbe
ignored during read cycles.
Table 30 LDREG command format
Table 31 STREG command format
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7.4.4.11 MASKLOAD
The MASKLOAD command is a three Dword command. Its purpose is to modify only portions or selected bits of a
SAA7146A register. The first Dword of the command contains the instruction code and specifies the register to be
modified. The second Dword containsthe mask and the third Dword contains the datatobe writtento the register through
this mask. The mask works as follows: if a bit in the mask is set, the data from the third Dword at the corresponding bit
position will be transferred to the register. If a bit in the mask is zero, the corresponding bit in the register will remain
unchanged.
Table 32 MASKLOAD command first Dword
7.4.5 OPERATION
The operationof the RPSis controlledby the enable bitsin the main control register1 (see Table 10).If oneof these bits
is set the related RPS task starts its execution with the command addressed by the task related RPS_ADDR register.
Whena RPS taskis switchedonit immediately starts fetchingits data via DMA, beginningat the actual address pointers
location. Four Dwords are fetchedata time and loaded intoan instruction queue. Operation continuesto the endof the
queue at the time the RPS DMA loads the next four Dwords in the RPS list.
To monitor the ongoing execution and the end of RPS there are status and interrupt bits for each task in the Primary
Status Register (PSR) and the Secondary Status Register (SSR), see Tables 38 and 39.
7.4.6 RPS ADDRESS REGISTER
The start addressof the RPSlistof each taskis definedin the RPS address registerof the task. The start address must
be Dword aligned.
During an RPS list execution this register works like a program counter. Since the RPS can write data into the main
memoryof the systema protection mechanismis implemented. Thereisa 4-kbyte pagein the memoryfor each taskin
which the RPS tasks are allowedto writein. Every write access outside this page will causean error and the RPS task
will stop immediately. If the corresponding bit in the interrupt enable register is set, an interrupt will be generated. This
protection mechanism canbe disabledvia the Enable RPS Page Register (ERPSPx) bit. Thisbitis locatedatbit0of the
RPS page register. A zero enables page errors. This bit is set to 1 after a reset.
Table 33 RPS address register
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Table 34 RPS page register
7.4.7 LINE COUNTER THRESHOLDS
For the events relatedto the line countersof the source and the target, (either HPSor BRS) there are two thresholdsfor
each taskin the HBI threshold register (see Table 35). The purposeof this registeristo set the HSor HT event flag when
the corresponding line counter has reached the threshold. These thresholds mustbe written before waitingon the event.
A value of zero as threshold turns the HS or HT event on, for every line.
Table 35 HBI threshold register
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7.4.8 RPS TIME OUT VALUE
These registers contain the valuesfor the time out conditionsof the PAUSE and CHECK_LATE commandsfor each task.
If the selected counter value is zero, the time out generation is disabled.
Table 36 RPS time out value
Table 37 RPS_TOx generation
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7.5 Status and interrupts7.5.1 GENERAL
In order to control the SAA7146A, the status information is collected and stored in two status registers: Primary Status
Register (PSR) and Secondary Status Register (SSR). These two registers followa hierarchical approach because the
PSR contains summed up information from the SSR. Interrupts can only be generated from the PSR and are enabled
via the Interrupt Enable Register (IER). If an interrupt condition occurs and the interrupt is enabled, the corresponding
bit in the Interrupt Status Register (ISR) is set. These bits can be cleared by writing a logic1.
Both status registers are read only. Writing a logic 1 into any of the PSR bits causes the corresponding interrupt to be
generated if enabled. Writing a logic 0 has no effect.
Table 38 Primary status register
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Table 39 Secondary status register
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Table 40 Interrupt enable register
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Table 41 Interrupt status register
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7.6 General Purpose Inputs/Outputs (GPIO)7.6.1 GENERAL
The SAA7146A has four general purpose I/O pins. For example, they could be used to signal to other devices a
power-down mode or to map an internal status bit to it.
Table 42 GPIO registers
Table 43 GPIO control register
7.7 Event counterTheeventcountersin the SAA7146A provide the possibilityof obtaining astatistical lookat the different interruptsources.
For this purpose six counters are implemented in two registers (EC1R and EC2R). Each register contains one 12-bit
counter and two 10-bit counters. To be flexible in the information collected in the counters it is possible to map each
statusbitto any counter. Thisis donevia the Event Counter Source Select Register (ECSSR). The four 10-bit counters
and the two 12-bit counters are ableto select oneof the64 possible sources (see Table 47).In additionto the counting,
it is possible to generate interrupts via threshold values for the counters. These thresholds are kept in the two Event
Threshold Registers (ET1R and ET2R).Ifa counter exceedsits threshold,itis resetto zero and the corresponding status
bit is set.
Table 44 Event Counter set 1 Register (EC1R)
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Table 45 Event Counter set 2 Register (EC2R)
Table 46 Event Counter set 1 Source Select Register 1 (EC1SSR)
Table 47 Event Counter set 2 Source Select Register (EC2SSR)
Table 48 Status Bit Addresses (SBA)
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Table 49 Event Counter Threshold set 1 Register (ECT1R)
Note Eachof these threshold values shows the limitupto which the related counter will run beforeit setsits interrupt status
bit.
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Table 50 Event Counter Threshold set 2 Register (ECT2R)
Note Eachof these threshold values shows the limitupto which the related counter will run beforeit setsit interrupt status
bit.
7.8 Video processing7.8.1 THE REAL TIME VIDEO INTERFACE
The real time video interface consists of two bidirectional 8-bit wide ports transporting colour difference samples and
luminance samples in a byte sequential manner. Each of the two video ports (A and B) has its own clock pin, pixel
qualifier and horizontal and vertical sync signal pin. The sync signal can be optionally coded in SAV and EAV codes
according to the D1 standard (SMPTE125M or CCIR 656). The two 8-bit ports can be combined to form a single 16-bit
wide YUV port to be compatible to the DMSD2 output format.
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7.8.2 DD1: DUAL D1 (CCIR 656, SMPTE125M), I/O
7.8.2.1 Cb-Y-Cr-Y 8-bit wide stream
In this mode two video ports with YUV 4 :2:2 sampling scheme are available. Each D1 port has an I/O capability and
has a separate clock input and separate sync lines. In this format the pixel rate is equivalent to the clock rate LLC.
The colour difference signal sample and luminance signal sample (straight binary) are byte-wise multiplexed into the
same 8-bit wide data stream, with sequence and timing in accordance with CCIR 656 recommendation (respectively
accordingto D1for60 Hz application). The incoming and scaled data are reformattedto 16-bitfor the HPS data path and
the corresponding reference signals are generated.A discontinuous data streamis supportedby acceptingor generating
a pixel/byte qualifying signal (PXQ= 1: qualified pixel, PXQ= 0: invalid data, see Fig.8). The start condition for
synchronizing to the correct Cb-Y-Cr-Y sequence is given by the selected horizontal reference signal. The sequence
increments only with qualified bytes.
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7.8.2.2 YUV 16-bit parallel (DMSD2) stream this mode only the HPS data pathis available since the BRS data path supports only 8-bit wide data streams. Colour
difference signal and luminance signal (straight binary) are availablein parallelona 16-bit wide data stream.In this mode
both D1 ports are inputs (see Fig.9). With this format the pixel rate is half the clock rate LLC. The start condition for
synchronising the clock divider and/or the correct U-V sequenceis givenby the CREF signal, which mustbe connected
to the same port as the colour difference signal.
7.8.3 VIDEO DATA FORMATSON DD1
D1 (SMPTE125M, CCIR 656) as well as YUV16 represent both the same 4 :2:2 sample scheme. Both formats, and YUV16, are assumed to agree with the CCIR recommendation 601 coding:=16= black, 0%= 235= white, 100% brightness
U,V= 128= no colour, 0% saturation
U,V= 128 ±112= full colour, 100% saturation.
Data path processing in HPS and BRS is not limited to this range and allows overshoots and uses ‘margins’ for
processing. The reference values can be manipulated by the BCS processing in the HPS data path.
7.8.4 VIDEO TIMING REFERENCE CODES (SAV AND EAV)
There are two timing reference codes; one at the beginning of each video data block [Start of Active Video (SAV)] and
one at the end of each video data block [End of Active Video (EAV)] as shown in Fig.10.
Each timing reference code consistsofa four byte sequencein the following format:FF0000 XY. (values are expressed hexadecimal notation: codes FF,00 are reservedfor usein timing reference codes). The first three bytes area fixed
preamble. The fourth byte contains information defining field identification, the stateof field blanking and the stateof line
blanking. The assignment of bits within the timing reference code is given in Table 51.
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Table 51 Video timing reference codes
Notes F= logic 0 during field 1 and logic 1 during field2. V= logic 0 elsewhere and logic 1 during field blanking. H= logic 0 in SAV and logic 1 in EAV. P0,P1,P2 and P3: protection bits (see Table 52).
Bits P0,P1,P2 and P3, have states dependenton the statesof the bitsF,V andHas shownin Table 52.At the receiver
(SAA7146A) this arrangement permits one-bit errors to be corrected. If two-bit errors or up to four-bit errors occur, i. e.
depending on uncoded protection bits, the circuit processes direct on the coded values. In this case the protection bits
are ignored.
SAV and EAV are only decoded and removed from the signal stream (substituted with neighbouring first or last active
video sample),if chosen this way. However, ‘single’ qualified codesof ‘00’ and/or ‘FF’in the data stream, remainin the
data stream and are processed as data.
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Table 52 Protection bits
7.8.5 SYNCHRONIZATION SIGNALS
Horizontal, vertical and frame synchronization signals are
either carried beside the data stream on the extra sync
pinsof DD1 (one pairof sync pins per D1 channel)or are
encoded as SAV and EAV in the 8-bit wide video signal
stream. For the 16-bit wide YUV stream sync signals are
always availableon separate pins. ForD1 video inputs the
SAA7146Ais programmedto determine whereto recover
the synchronization information (from the dedicated sync
pinsor from the encoded SAV and EAV codesin the data
stream).
ForD1 video outputs, the SAA7146A canbe programmed
to deliver synchronization information both in SAV and
EAV codes as well as on the dedicated sync pins.
Non-standard rastered video signals are supported by
sync signalsat the dedicated sync pinsas wellasvia SAV
and EAV codes. The number of clock cycles, pixels per
line andlines per field canbe non-standard.Thesenumber
can range from 1 up to 4095.
The signal at the HS pin can perform the following
functions: HS: input only, the rising edge is selected to act as
timing reference HREF: input only, gated with CREF, the rising edge is
selected as timing reference HGT: I/O, HIGH during active video ACT input only: HIGH during active video, inactive
during horizontal and vertical blanking HGT and ACT: envelope all active pixels (there is no
active pixel outside HGTor ACT), but may also include
clock cycles marked as not valid pixels by means of
PXQ.
The vertical sync signal can perform the following
functions: VS: input only positiveor negative, one edgeis selected
as timing reference: If selected edge of VS and selected edge of HS are
in phase, then begin 1st (odd) fieldIf selected edgesof VS and HS are out ofphase, then
begin 2nd (even) field. V-DMSD: input only, falling (trailing) edge is timing
reference: If falling edge of V-DMSD is in high phase of HREF,
then begin 1st (odd) field If falling edge of V-DMSD is in low phase of HREF,
then begin 2nd (even) field. VGT: I/O, HIGH during active video, (no holes for
horizontal blanking) FS: input only, positive or negative, frame sync,
(odd/even), (313/312, 263/262 lines) HIGHin one field,
LOW in the other, changes on full line boundaries only.
7.8.6 FIELD DETECTION
The fields are detected simultaneously at both D1 sync
inputs. The results are available in two status registers.
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Table 53 Field interval definitions for D1 (CCIR 656) SAV and EAV codes; note1
Note Signals F and V change state synchronously with the end of active video timing reference code at the beginning of
the digital line.
7.8.6.1 Field detection control
Field detection modes: Direct mode: FLD signal detected from incoming H/V signals, for timing behaviour see Figs. 11 and 12. Forced toggle: FLD signal regularly synchronizedto source, but will never stay more than two fields with the same ID.
The circuit expectsto detecta field change with every vertical reference edge,if the field does not change (field error),
the circuit change the field ID automatically. If the circuit switch to the wrong sequence i. e. at the beginning of
processing, it will be synchronized after one second where no field error has occurred. Free toggle: FLD signal toggles with every vertical reference edge, independent of source FID.
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7.8.7 ACQUISITION CONTROL
The processing window for the scaling unit is defined in the acquisition control. The internal counters (one for the HPS
and onefor the BRS) receives programmable valuesfor offset (HXO11to HXO0, HYO11to HYO0 and BXO9to BXO0,
BYO9to BYO0) and length (NumLines, NumBytes). These counters are resetby the corresponding sync reference input
signal. The horizontal counter increments in qualified pixels for the HPS and qualified bytes for the BRS, the vertical
counter increments in qualified lines, i.e. lines containing at least one qualified pixel. In order to avoid programming
dependent line drop effects, the horizontal offset value must not exceed the numberof pixels per line.In orderto avoid
programming dependent field drop effects, the vertical offset value must not exceed the number of lines per field.
The acquisition provides the possibility to re-program the vertical offset after the previous job is done (EOW at the
HPS and BRS is reached). Thus multiple windows can be opened during one field.
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7.8.8 COMPARISON BETWEEN CCIR 656 LINE AND SOURCE LINE COUNTER
This section describes how to choose the vertical offset and how to use the source line counter event for RPS
programming for capturing the expected line.
The internal Source Line Counter (SLC)is resetby the selected edgeof the vertical sync signal whichis providedat port
VS_x.The falling and rising edgesof this signal are selectedby the SYNC_X bitsin the ‘Initial settings DD1Port Register’
(offset= 50H). Consequently, the behaviourof the SLC dependson the connected vertical sync signalso that different
offsets mustbe selectedto capture the expected line. The active video beginsin the CCIR 656 line23of the video signal;
Table 54 lists the different offsets which must be selected to capture the expected line. The subsequent diagrams and
tables illustrate the relationship between the different vertical sync signalsof the PAL and NTSC standards, the ODD and
EVEN field and the internal SLC.
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Table 54 Offsets to CCIR 656 line 23 depending on PAL or NTSC source (in compliance with Recommendation 601),
ODD and EVEN field and select mode (see note1)
Notes Line numbers in parenthesis refer to EVEN field counting. Sync signal SLC with SAV/EAV detection (50H, SYNC_X=7). Sync signal SLC with external Field Identification Signal (50H, SYNC_X=6). Sync signal SLC with detection on the falling edge of the vertical sync signal (50H, SYNC_X=1,3or5). Sync signal SLC with detectionon the rising edgeof the vertical sync signal. For Philips devices, the rising edge does
not include field information, this informationis only definedat the falling edgeof theVS signal (50H, SYNC_X=0,24).
7.8.8.1 Video with PAL format
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le 55
Compar
ison betw
een CCIR
656 lines and the SLC (note
Notes 1.
Line numbers in parenthesis refer to EVEN field counting.
CCIR
656 (D1) line.
SLC with SAV/EAV detection (50H, SYNC_X
7).
SLC with external Field Identification Signal (50H, SYNC_X
6).
SLC with detection on the falling edge of the vertical sync signal (50H, SYNC_X
5).
SLC with detection on the rising edge of the vertical sync signal. For Philips devices, the rising edge does not include fiel
d information, this
information is only defined at the falling edge of the VS signal (50H,
SYNC_X
4).
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7.8.8.2 Video with NTSC format
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le 56
Compar
ison betw
een CCIR
656 lines and SLC (note
Notes 1.
Line numbers in parenthesis refer to EVEN field counting.
CCIR
656 (D1) line.
SLC with SAV/EAV detection (50H, SYNC_X
7).
SLC with external Field Identification Signal (50H, SYNC_X
6).
SLC with detection on the falling edge of the vertical sync signal (50H, SYNC_X
5).
SLC with detection on the rising edge of the vertical sync signal. For Philips devices, the rising edge does not include fiel
d information, this
information is only defined at the falling edge of the VS signal (50H,
SYNC_X
4).
Philips Semiconductors Product specification
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7.9 High Performance Scaler (HPS)Depending on the selected port modes the incoming and
scaleddata are formatted/reformatted (8-bitor 16-bit),and
the corresponding reference signals aregenerated.Based these reference signalsthe active processing windowis
defined in a versatile way via programming.
The programming register can be loaded during the
processing of the previous field, frame or line by RPS. this way eachD1 port gets processedina fieldor frame
alternating manner.If the incoming signals are not locked,
then the acquisition is waiting for the new active video of
the subsequent field. The corresponding fields are
detectedbya ‘Field Detection’.To support asynchronous
video processingin the two video paths, eachD1 port has
its own ‘Field Detection’. The video signal source is also
source for the qualify signal PXQ.
Before being processed in the central scaling unit the
incoming data passes to the BCS control unit, where
monitor control functions for adjusting Brightness and
Contrast (luminance)as wellas Saturation (chrominance)
are implemented (BCS control). The horizontal scaling is
carried outin two steps;a prefiltering (bandwidth limitation
for initialising) anda horizontal fine scaling. Between them
the vertical processing is performed.
7.9.1 BCS CONTROL
The parameters for brightness, contrast and saturation
can be adjusted in the BCS control unit. The luminance
signal can be controlled by the bits BRIG7to BRIG0 and
CONT6to CONT0. The chrominance signal can be
controlled by the bits SAT6to SAT0.
Brightness control (BRIG7to BRIG0): 00H; minimum offset 80H; CCIR level FFH; maximum offset.
Contrast control (CONT6to CONT0): 00H; luminance off 40H; CCIR level 7FH; 1.9999 amplitude.
Saturation control (SAT6to SAT0): 00H; colour off 40H; CCIR level 7FH; 1.9999 amplitude.
Limits: All resulting output values are limited to minimum
(equals 0) and maximum (equals 255).
7.9.2 SCALING UNIT
The scaling to a randomly sized window is performed in
three steps: Horizontal prescaling (bandwidth limitation for
anti-aliasing, via FIR prefiltering and subsampling) Vertical scaling (generating phase interpolated or
vertically low-passed lines) Horizontal phase scaling (phase correct scaling to the
new geometric relations).
The scaling process generatesa new pixel/clock qualifier
sequence. There are restrictions in the combination of
input sample rate andupor downscaling mode and scaling
factor. The maximum resulting output sample rate at the
DD1 port is 1⁄2LLC, because of compliance to the
CCIR 656 format.
7.9.2.1 Horizontal prescaling
The incoming pixels in the selected range are
pre-processedin the horizontal prescaler (first stageof the
scaling unit). It consists of a FIR prefilter and a pixel
collecting subsampler.
7.9.2.2 FIR prefilter
The video components Y,U and V are FIR pre-filtered to
reduce the signal bandwidth according to the downscale
for factors between1 and1⁄2,so that aliasing, due tosignal
bandwidth expansion,is reduced. The prefilter consistsof filter stages. The transfer functions are listed in the
Section 7.12. The prefilter is controlled by the ‘Scaler
Register’ bits PFY3to PFY0 and PFUV3to PFUV0in the
HPS horizontal prescale register (see Table 79).
Figures18 and 19 show frequency response
characteristics and the corresponding scaler register
settings. The prefilter operates on YUV 4:4:4 data.
As U and V are generated by simple chroma pixel
doubling, the UV prefilter should alsobe usedto generate
the interpolated chroma values.
7.9.2.3 Subsampler
To improve the scaling performance for scales less than⁄2 down to icon size, a FIR filtering subsampler is
available.It performsa subsamplingof the incoming data
by a factor of 1/N, where N=1to 64. This operation is
controlled by XPSC, where N= XPSC+ 1. Where
NIP= number of input pixels/line and NOP= number of
desired output pixels/line, the basic equation to calculate
XPSC is:
XPSC= TRUNC [(NIP/NOP)−1]
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The subsampler collectsa numberof [XPSC+2− XACM]
pixels to calculate a new subsampled output pixel. So a
downscale dependent FIR filter is built with up to 65 taps
which reduces anti-aliasing for small sizes. If XACM=0,
the collecting sequence overlaps which means that the
last pixelof sequenceMis also the first pixelof sequence
M+1. implementa real subsampler bypass, XACM hastobe
set to logic1.
As the phase correct horizontal fine scaling is limited to a
maximum downscaleof1⁄4, this circuitry hastobe usedfor
downscales less than 1⁄4 of the incoming pixel count.
To get unity gain at the subsamplers output for all
subsampling ratios, the scaler register parameters CXY,
CXUV and DCGX havetobe used.In addition, this canbe
used to modify the FIR characteristic of the subsampler
slightly. Table 57 illustrates examples for scaler register
settings, dependingona given prescale ratio. Referringto
Table 57 (divider in column ‘Weight Sum’) it should be
noted that an internal XPSC depending automatic
prenormalization is valid for:
XPSC>8,> 16,> 32, which reduces the input signal
quantization. In addition it should be noted that for
XPSC≥ 15 the LSB of the CXY,CXUV parameter
becomes valid.
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Table 57 Horizontal prescaling and normalization
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7.9.2.4 Vertical scaler
Thevertical scaler performs the vertical downscalingof the
input data stream to a randomly number of output lines.
It can be used for input line lengths up to 768 pixels/line
and has to be bypassed, if the input line length exceeds
this pixel count.
For the vertical scaling there are two different modes: The ACCU mode (vertical accumulation) for scales
down to icon size and The Linear Phase Interpolation (LPI) mode for scales
between 1 and1⁄2.
7.9.2.5 ACCU mode (scaling factor range1to 1/1024;
YACM=1)
For vertical scales downto icon size the ACCU mode can
be used. In this mode the parameter YSCI controls the
scaling and the parameter YACL the vertical anti-aliasing
filtering.
The output lines are generated by a scale-dependent
variable averagingof (YACL+2) input lines.In this waya
vertical FIR filter is build for anti-aliasing, with up to
maximum 65 taps.
YSCI defines the output line qualifier pattern and YACL
defines the sequence length for the line averaging.
For accurate processing the sequence has to fit into the
qualifying pattern. In case of misprogramming YACL,
unexpected line dropping occurs.
Where: NOL= Number of Output Lines and NIL= Number of Input Lines.
the YSCI (scaling increment), YACL (accumulation length;
optimum:1 line overlap) andYP (scaling start phase) have
to be set according to the equations below, see Fig.20. YACL= TRUNC [NIL/NOL− 1] accumulation sequence
length; i.e. number of lines per sequence, that are not
part of overlay region of neighbouring sequences
(optimum: 1 line overlapped) YSCI= INT [1024×(1− NOL/NIL)] scaling increment YPx= INT [YSCI/16] scaling startphase (fix; modifiedin
LPI mode only).
In order to get a unity amplitude gain for all sequence
lengths and to improve the vertical scaling performance,
the accumulated lines canbe weighted and the amplitude
of the scaled output signal has to be renormalized. In the
given example (see Fig.20), using the optimal weighting,
the gain of a sequence results in 1+2+2+1=6.
Renormalization (factor1 ⁄6) can be done By gain reduction using BCS control (brightness,
contrast, saturation) down to4 ⁄6 and selecting factor1⁄4
for DCGY2to DCGY0 which may result in a loss of
signal quantization, or By gain emphasizing using BCS control up to8⁄6
and selecting factor1 ⁄8 for DCGY2to DCGY0 which
may resultina lossof signal detail dueto limitingin the
BCS control.
Normally, the weighting would be 2+2+2+ 2. In this
case the gain can be renormalized simply with
DCGY2to DCGY0= ‘010’ (factor1 ⁄8). Table 58 gives
examplesfor register settings dependingona given scale
ratio.
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Table 58 Vertical scaling and normalization
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7.9.2.6 LPI mode (scaling factor range1to1⁄2; register
bit YACM=0)
To preserve the signal quality for slight vertical
downscales (scaling factors 1to1 ⁄2) Linear Phase
Interpolation (LPI) between consecutive lines is
implemented to generate geometrically correct vertical
output lines. Thus, the new geometric position between
lines N and N+ 1 can be calculated.
A new output line is calculated by weighting the samples
‘p’of linesN andN+1 with the normalized distanceto the
newly calculated position:
p(M)=A× p(N+1)+(1−A)× p(N); where A=0to63⁄64.
With NOL= Number of Output Lines and NIL= Number of
Input Lines the scaler register bits YSCI (scaling
increment) and YP (scaling start phase) have to be set
according to the following equations: YSCI= INT [1024× (NIL/(NOL−1)] scaling increment YPx= INT [YSCI⁄16] scaling start phase (recommended
value).
The vertical start phase offset is defined by
YP⁄64 (YP=0to 64): YP= 0: offset= 0 geometrical position of 1st
lineout= 1st linein YP= 64: offset=64⁄64= 1 geometrical position of
1st lineout= 2nd linein.
Finally 3 special modes are to be emphasized:
Bypass (YSCI=0,YP= 64); eachlineoutis equivalent
to corresponding linein
Low-pass (YSCI=0,YP< 64); e.g.YP= 32: average
value of 2 lines (1+z−h filter) For processing of
interlaced input signals the LPImode must be used (ACCU mode would cause ‘line
pairing’ problems). The scaling start phasefor odd and
even field have to be set to:
YPeven=3⁄2× YPodd (line1= odd)
In modes 1 and 2 the first input line is fed to the output
(without processing), so that the number of output lines
equals the number of input lines.
7.9.2.7 Flip option (Mirror=1)
For both vertical scaling modes there is a flip option
‘mirroring’ available for input lines with a maximum of
384 pixels. In the case of full screen pictures (e.g.
768× 576) that have to be flipped, they first have to be
downscaled to 384 pixel/line in the horizontal prescaling
unit and after vertical processing (flipping) they may be
rezoomed to the original 768 pixels/line in the following
VPD. shouldbe noted that, when using theflip option, the last
input line can not be displayed at the output.
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7.9.3 HORIZONTAL PHASE SCALING
In the phase correct Horizontal Phase Scaling (HPS) the
pixels are calculated for the geometrically correct,
orthogonal output pattern, down to1⁄4 of the prescaled
pattern. A horizontal zooming feature is also supported.
The maximum zooming factor is at least 2, even more
dependent on input pattern and prescaling settings.
The phase scaling consists of a filter and an arithmetic
structure which is able to generate a phase correct new
pixel value almost without phase or amplitude artefacts.
The required sample phase informationis generatedbya
sample phase calculator, with an accuracy of1 ⁄64 of the
pixel distance. The up/downscaling with this circuitry is
controlledby the scaler register parameters XSCI and XP.
As the fine scaling is restricted to downscales>(1 ⁄4 of the
fine scalers input pixel count), XSCI is also a function of
the prescaling parameter XPSC.
With NIP= Number of Input Pixel/line (at DD1 input) and
NOP= Number of desired Output Pixels/line, XSCI is
defined to:
XSCI= INT [(NIP/NOP)× 1024/(XPSC+1)]
The maximum value of XSCI= 4095. Zooming is
performedfor XSCI values less than 1024. The numberof
disqualified clock cycles between consecutive pixel
qualifiers (at the fine scalers input) defines the maximum
possible zoom factor. Consequently, zooming mayalsobe functionof XPSC.It shouldbe noted thatif the zooming
factor is greater than 2, some artefacts may occur at the
end of the zoomed line.
7.9.4 COLOUR SPACE MATRIX (CSM), DITHER AND
γ-CORRECTION
The scaled YUV output data is converted after
interpolation into RGB data according to CCIR 601
recommendations. The CSM is bypassed in all YUV
formats or monochrome modes.
The matrix equations considering the digital quantization
are:=Y+ 1.375V
G=Y− 0.703125V− 0.34375U=Y+ 1.734375U. dither algorithmis implementedfor error diffusion. ROM
tables are implemented at the matrix output to provide
anti-gamma correction of the RGB data. A curve for a
gamma of 1.4 is implemented. The tables can be used to
compensate gamma correction for linear data
representation of RGB output data.
The ‘Chroma Signal Key’ generatesan alpha signal used
inseveral RGB formats. Therefore, the processed UV data
amplitudes are compared with thresholds. A logic 1 is
generated, if the amplitude is within the specified
amplitude range. Otherwisea logic0is generated. Keying
can be switched off by setting the lower limit higher than
the upper limit.
7.10 Binary Ratio Scaler (BRS)7.10.1 GENERAL DESCRIPTION
The BRSis the second scalerin the SAA7146A. The BRS supposedto supportdifferent encoder applications while
the HPS is processing video data. The BRS does not
support clipping.
The mainstream applicationof the BRSisto read data via
PCI, e.g. a QCIF-formatted video data to proceed with
horizontal and vertical upscalingto CIF-format and placeit
at the encoder’s disposal (normal playback mode).
To support CCIR encoder and square pixel encoder, an
active video windowas inputfor the BRS canbe defined. will prevent black pixels being displayedat the endof the
line or at the bottom of the field.
The BRS supports only the YUV4:2:2 video data format
(see Section 7.11.2). The used DD1 I/O data format is
8-bit. The BRS uses video DMA Channel3 (FIFO3) which only available,if the HPSis notin planar modeor writes
back clip information.
Vertical upscaling is supported by means of repeated
reading of the same line via PCI. Vertical downscaling is
achieved by line dropping.
Horizontal downscaling is performed by an accumulating
FIR filter. The downscaling is available for the inbound
mode and the upscaling is available for the outbound
mode (see Figs22 and 23). Vertical ratios: 4,2,1,1⁄2 and1 ⁄4; select with BRS_V Horizontal ratios: 8,4,2,1,1⁄2,1 ⁄4 and1 ⁄8; select with
BRS_H. the datais sent from DD1to PCI, the processing window
for the BRS scaling unitis definedin the acquisition control
(see Section 7.8.7).
