SAA7128AH ,Digital video encoderFEATURES2• Monolithic CMOS 3.3 V device, 5 V I C-bus optional• Digital PAL/NTSC/SECAM encoder• Syst ..
SAA7129AH ,Digital video encoder
SAA7129AH ,Digital video encoder
SAA7129AH ,Digital video encoderFUNCTIONAL DESCRIPTION12.1 Introduction to soldering surface mount7.1 Versatile faderpackages7.2 Da ..
SAA7129H/V1 ,SAA7128H; SAA7129H; Digital video encoder
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SAA7128AH-SAA7129AH
Digital video encoder
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
CONTENTS FEATURES GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION
7.1 Versatile fader
7.2 Data manager
7.3 Encoder
7.4 RGB processor
7.5 SECAM processor
7.6 Output interface/DACs
7.7 Synchronization
7.8 Clock
7.9 I2 C-bus interface
7.10 Input levels and formats
7.11 Bit allocation map
7.12 I2 C-bus format
7.13 Slave receiver
7.14 Slave transmitter LIMITING VALUES CHARACTERISTICS
9.1 Explanation of RTCI data bits
9.2 Teletext timing APPLICATION INFORMATION
10.1 Digital output signals PACKAGE OUTLINE SOLDERING
12.1 Introduction to soldering surface mount
packages
12.2 Reflow soldering
12.3 Wave soldering
12.4 Manual soldering
12.5 Suitability of surface mount IC packages for
wave and reflow soldering methods REVISION HISTORY DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2 C COMPONENTS
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
FEATURES Monolithic CMOS 3.3 V device, 5V I2 C-bus optional Digital PAL/NTSC/SECAM encoder System pixel frequency 13.5 MHz 54 MHz double-speed multiplexed D1 interface capable
of splitting data into two separate channels (encoded
and baseband) Three Digital-to-Analog Converters (DACs) for CVBS
(CSYNC), VBS (CVBS) and C (CVBS) two times
oversampled with 10-bit resolution (signals in brackets
optional) Three DACsfor RED (CR), GREEN (Y) and BLUE (CB)
two times oversampled with 9-bit resolution (signals in
brackets optional) Alternatively, an advanced composite sync is available
on the CVBS output for RGB display centring Real-time control of subcarrier Cross-colour reduction filter Closed captioning encoding and World Standard
Teletext (WST) and North-American Broadcast Text
System (NABTS) teletext encoding including sequencer
and filter Copy Generation Management System (CGMS)
encoding (CGMS described by standard CPR-1204 of
EIAJ);20 bitsin lines 20/283 (NTSC) canbe loaded via2 C-bus Fast I2 C-bus control port (400 kHz) Line 23 Wide Screen Signalling (WSS) encoding Video Programming System (VPS) data encoding in
line 16 (50/625 lines counting) Encoder can be master or slave Programmable horizontal and vertical input
synchronization phase Programmable horizontal sync output phase Internal Colour Bar Generator (CBG) Macrovision(1) Pay-per-View copy protection system
rev. 7.01 and rev. 6.1 as option; this applies to
SAA7128AH only. The device is protected by USA
patent numbers 4631603, 4577216 and 4819098 and
other intellectual property rights. Useof the Macrovision
anti-copy process in the device is licensed for
non-commercial home use only. Reverse engineeringor
disassembly is prohibited. Please contact your nearest
Philips Semiconductors sales officefor more information Controlled rise/fall times of output syncs and blanking On-chip crystal oscillator (3rd-harmonicor fundamental
crystal) Down mode (low output voltage)or power-save modeof
DACs QFP44 package.
GENERAL DESCRIPTIONThe SAA7128AH; SAA7129AH encodes digital CB-Y-CR
video datatoan NTSC, PALor SECAM CVBSor S-video
signal. Simultaneously, RGBor bypassed but interpolated
CB-Y-CR signals are available via three additional DACs.
Through a 54 MHz multiplexed digital D1 input port, the
circuit accepts two ITU-R BT.656 compatible CB-Y-CR
data streams with 720 active pixels per line in
4:2:2 multiplexed formats. For example, MPEG
decoded data with overlay and MPEG decoded data
without overlay, where one data stream is latched at the
rising, the other one is latched at the falling clock edge.
It includes a sync/clock generator and on-chip DACs.
(1) Macrovision is a trademark of the Macrovision Corporation.
ORDERING INFORMATION
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
QUICK REFERENCE DATA
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
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BLOCK DIAGRAM
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
PINNING
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH FUNCTIONAL DESCRIPTION
The digital video encoder encodes digital luminance and
colour difference signals into analog CVBS, S-video and
simultaneously RGB or CR-Y-CB signals. NTSC-M,
PAL-B/G, SECAM and sub-standards are supported.
Both interlaced and non-interlaced operation is possible
for all standards.
The basic encoder function consists of subcarrier
generation, colour modulation and insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements of “RS-170-A” and “ITU-R BT.470-3”.
For ease of analog post filtering, the signals are twice
oversampled with respect to the pixel clock before
digital-to-analog conversion.
The total filter transfer characteristics are illustrated in
Figs8to 13. The DACs for Y, C and CVBS are realized
with full 10-bit resolution; 9-bit resolution for RGB output.
The CR-Y-CB toRGB dematrix canbe bypassed optionally
in order to provide the upsampled CR-Y-CB input signals.
The8-bit multiplexed CB-Y-CR formats are “ITU-R BT.656”
(D1 format) compatible, but the SAV and EAV codes can
be decoded optionally, when the device is operated in
slave mode. Two independent data streams can be
processed, one latched by the rising edge of LLC1, the
other latchedby the falling edgeof LLC1. The purposeof
that is e.g. to forward one of the data streams containing
both video and On-Screen Display (OSD) information to
the RGB outputs, and the other stream containing video
only to the encoded outputs CVBS and S-video.
For optimum display of RGB signals through a
euro-connector TV set, an early composite sync pulse
(up to 31 LLC1 clock periods) can be provided on the
CVBS output.
As a further alternative, the VBS and C outputs may
provide a second and third CVBS signal.is also possibleto connecta Philips digital video decoder
of the SAA711x family to the SAA7128AH; SAA7129AH.
Via the RTCI pin, connected to RTCO of a decoder,
information concerning actual subcarrier, PAL-ID and
definite subcarrier phase can be inserted.
The device synthesizes all necessary internal signals,
colour subcarrier frequency and synchronization signals
from that clock.
Wide screen signalling data canbe loaded via theI2 C-bus
andis inserted into line23for standards using50Hz field
rate.
VPS datafor program dependent automatic start and stop
of such featured VCR’s is loadable via I2C-bus.
The IC also contains closed caption and extended data
services encoding (line 21), and supports anti-taping
signal generationin accordance withMacrovision.Itis also
possible to load data for copy generation management
system into line 20 of every field (525/60 line counting). numberof possibilities are providedfor setting different
video parameters, such as: Black and blanking level control Colour subcarrier frequency Variable burst amplitude, etc.
During reset (RESET= LOW) and after resetis released,
all digital I/O stages aresetto input mode and the encoder
is set to PAL mode and outputs a ‘black burst’ signal on
CVBS and S-video outputs, while RGB outputs are set to
their lowest output voltages. A reset forces the I2 C-bus
interface to abort any running bus transfer.
7.1 Versatile fader
Important note: whenever the fader is activated with the
SYMP bit set to a logic 1 (enabling the detection of
embedded Start of Active Video (SAV) and End of Active
Video (EAV)), codes 00H and FFH are not allowed within
the actual video data (as prescribed by “ITU-R BT.656”,
anyway). If SAV (00H) has been detected, the fader
automatically passes 100% of the respective signal until
SAV will be detected.
Within the digital video encoder, two data streams canbe
faded against each other; these data streams canbe input the double speed MPEG port, whichis ableto separate
two independent 27 MHz data streams MPA and MPB via
a cross switch controlled by EDGE1 and EDGE2.
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
7.1.1 CONFIGURATION EXAMPLES
Figures4to 7 show examples on how to configure the
fader between the input ports and the outputs, separated
into the composite (and S-video) encoder and the RGB
encoder.
7.1.1.1 Configuration1
Input MPA canbe faded into MPB.
the fader is then encoded simultaneously to composite
(and S-video) and RGB output (RGBIN this example, either MPA or MPB could be an overlay
(menu) signal to be faded smoothly in and out.
7.1.1.2 Configuration2
Input MPA canbe faded into MPB. The resulting outputof
the faderis then encodedto RGB output, while the signal
coming from MPB isfeddirectlyto composite(and S-video)
output (RGBIN= 1, ENCIN= 0). Also in this example,
either MPAor MPB couldbean overlay (menu) signaltobe
faded smoothly in and out, whereas the overlay appears
only in the RGB output connected to the TV set.
7.1.1.3 Configuration3
Input MPBis passed directlyto the RGB output, assuming
e.g. itcontainsvideo including overlay. MPAis equivalently
passed through the inactive fader to the composite (and
S-video) output, assuming e.g.it contains video excluding
overlay (RGBIN= 0, ENCIN=1). appears both composite= ENCIN=0).
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
7.1.2 PARAMETERSOF THE FADER
Basically, there are three independent fade factors
available, allowing for the equation:
Where x= 1, 2 or 3
Factor FADE1 is effective, when a colour in the data
stream fedto the MPEG port fader inputis recognizedas
being between KEY1L and KEY1U. That means, the
colour is not identified by a single numeric value, but an
upper and lower threshold in which a 24-bit YUV colour
space can be defined. FADE1= 00H results in 100%
signal at the MPEG port fader input and 0% signal at the
fader Video port input. Variationof63 stepsis possibleup FADE1= 3FH, resultingin 0% signalat the MPEG port
fader input and 100% signal at the fader Video port input.
Factor FADE2 is effective, when a colour in the data
stream fedto the MPEG port fader inputis recognizedas
being between KEY2L and KEY2U. FADE2 is to be seen
in conjunction with a colour that is defined by a 24-bit
internal Colour Look-Up Table (CLUT). FADE2= 00H
results in 100% of the internally defined LUT colour and
0% signal at the fader Video port input. Variation of stepsis possibleupto FADE2= 3FH, resultingin 0%of
the internally defined LUT colour and 100% signal at the
fader Video port input.
Finally, factor FADE3is effective whena colourin the data
stream fedto the MPEG port fader inputis recognizedas
neither being between KEY1L and KEY1U nor being
between KEY2L and KEY2H. FADE3= 00H results in
100% signal at the MPEG port fader input and 0% signal
at the fader Video port input. Variation of 63 steps is
possibleupto FADE3= 3FH, resultingin 0% signalat the
MPEG port fader input and 100% signalat the fader Video
port input.
Optionally,all upper and lower thresholds canbe ignored,
enabling to fade signals only against the LUT colour.bit CFADMis set HIGH,all dataat the MPEG port fader
are faded against the LUT colour, if bit CFADV is set
HIGH,all dataat the Video port fader are faded against the
LUT colour.
7.2 Data manager
In the data manager, alternatively to the external video
data, a pre-defined colour look-up table located in this
block canbe read outina pre-defined sequence(8 steps
per active video line), achieving a colour bar test pattern
generator without the need for an external data source.
7.3 Encoder
7.3.1 VIDEO PATH
The encoder generates out of Y, U and V baseband
signals luminance and colour subcarrier output signals,
suitable for use as CVBS or separate Y and C signals.
Luminance is modified in gain and in offset (latter
programmableina certain rangeto enable different black
level set-ups).A blanking level canbe set after insertionof
a fixed synchronization pulse tip level in accordance with
standard composite synchronization schemes. Other
manipulations used for the Macrovision anti-taping
process such as additional insertion of AGC super-white
pulses (programmable in height) are supported by the
SAA7128AH only. orderto enable easy analog post filtering, luminanceis
interpolated from a 13.5 MHz data rate to a 27 MHz data
rate, providing luminancein 10-bit resolution. The transfer
characteristics of the luminance interpolation filter are
illustrated in Figs10 and 11. Appropriate transients at
start/end of active video and for synchronization pulses
are ensured.
Chrominance is modified in gain (programmable
separately for U and V), standard dependent burst is
inserted, before baseband colour signals are interpolated
from a 6.75 MHz data rate to a 27 MHz data rate. One of
the interpolation stages canbe bypassed, thus providinga
higher colour bandwidth, which can be made use of for and C output. The transfer characteristics of the
chrominance interpolation filter are illustrated in
Figs8 and9.
The amplitude, beginning and endingof the inserted burst,
is programmable in a certain range that is suitable for
standard signals and for special effects. Behind the
succeeding quadrature modulator, colour in a 10-bit
resolution is provided on the subcarrier.
The numeric ratio between Y and C outputs is in
accordance with the respective standards.
Output FADEx ln1× () 1 FADEx– () ln2× []+=
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
7.3.2 TELETEXT INSERTION AND ENCODING
Pin TTX receives a WST or NABTS teletext bitstream
sampled at the LLC clock. Two protocols are provided: At each rising edge of output signal (TTXRQ) a single
teletext bit has to be provided after a programmable
delay at input pin TTX The signalTTXRQ performs onlyasingle LOW-to-HIGH
transition and remainsat HIGH levelfor 360, 296or 288
teletext bits, depending on the chosen standard.
Phase variant interpolationis achievedon this bitstreamin
the internal teletext encoder, providing sufficient small
phase jitter on the output text lines.
TTXRQ provides a fully programmable request signal to
the teletext source, indicating the insertion period of
bitstream at lines which are selectable independently for
both fields. The internal insertion window for text is set to
360 (PAL-WST), 296 (NTSC-WST) or 288 (NABTS)
teletext bits including clock run-in bits. The protocol and
timing are illustrated in Fig.23.
7.3.3 VIDEO PROGRAMMING SYSTEM (VPS) ENCODING
Five bytes of VPS information can be loaded via the2 C-bus and willbe encodedin the appropriate format into
line 16.
7.3.4 CLOSED CAPTION ENCODER
Using this circuit, datain accordance with the specification
of closed caption or extended data service, delivered by
the control interface, can be encoded (line 21). Two
dedicated pairs of bytes (two bytes per field), each pair
precededby run-in clocks and framing code, are possible.
Theactualline number where dataistobe encodedin, can
be modified in a certain range.
The data clock frequency is in accordance with the
definition for NTSC-M standard 32 times horizontal line
frequency.
Data LOWat the outputof the DACscorrespondsto0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.is also possibleto encode closed caption datafor50Hz
field frequencies at 32 times horizontal line frequency.
7.3.5 ANTI-TAPING (SAA7128AH ONLY)
For more information contact your nearest Philips
Semiconductors sales office.
7.4 RGB processor
This block contains a dematrix in order to produce red,
green and blue signals to be fed to a SCART plug.
Before Y, CB and CR signals are de-matrixed, individual
gain adjustment for Y and colour difference signals and times oversampling for luminance and 4 times
oversampling for colour difference signals is performed.
The transfer curves of luminance and colour difference
components of RGB are illustrated in Figs12 and 13.
7.5 SECAM processor
SECAM specific pre-processing is achieved by a
pre-emphasis of colour difference signals (for gain and
phase see Figs14 and 15).
A baseband frequency modulator with a reference
frequency shifted from 4.286 MHz to DC carries out
SECAM modulation in accordance with appropriate
standard or optionally wide clipping limits.
After the HFpre-emphasis, also appliedona DC reference
carrier (anti-Cloche filter; see Figs16 and 17), line-by-line
sequential carriers with black referenceof 4.25 MHz (Db)
and 4.40625 MHz (Dr) are generated using specified
values for FSC programming bytes.
Alternating phase reset in accordance with SECAM
standard is carried out automatically. During vertical
blanking, the so-called “bottle pulses” are not provided.
7.6 Output interface/DACs
In the output interface, encoded Y and C signals are
converted from digital-to-analog in a 10-bit resolution. and C signals are also combined to a 10-bit CVBS
signal.
The CVBS output occurs with the same processing delay
(equal to 82 LLC clock periods, measured from MP input
to the analog outputs) as the Y, C and RGB outputs.
Absolute amplitude at the input of the DAC for CVBS is
reduced by15 ⁄16 with respect to Y and C DACs to make
maximum use of conversion ranges.
Red, green and blue signals are also converted from
digital-to-analog, each providing a 9-bit resolution.
Outputs of the DACs can be set together via software
control to minimum output voltage (approximately 0.2V
DC) for either purpose. Alternatively, the buffers can be
switched into 3-state output condition; this allows for a
‘wired AND’ configuration with other 3-state outputs and
can also be used as a power-save mode.
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
7.7 Synchronization
The synchronization of the SAA7128AH; SAA7129AH is
able to operate in two modes; slave mode and master
mode.
In master mode (see Fig.19), the circuit generates all
necessary timings in the video signal itself, and it can
provide timing signals at the RCV1 and RCV2 ports. slave mode,it accepts timing information either from the
RCV pins or from the embedded timing data of the
ITU-R BT.656 data stream.
For the SAA7128AH; SAA7129AH, the only difference
between master and slave mode is that it ignores the
timing informationatits inputsin master mode. Thus,ifin
slave mode, any timing information is missing, the IC will
continue running free without a visible effect. But there
must not be any additional pulses (with wrong phase)
because the circuit will not ignore them.
In slave mode (see Fig.18), an interface circuit decides,
which signal is expected at the RCV1 port and which
informationis taken fromits active slope. The polarity can
be chosen. If PRCV1 is logic 0, the rising slope will be
active.
The signal can be: A Vertical Sync (VS) pulse; the active slope sets the
vertical phase An odd/even signal; the active slope sets the vertical
phase, the internal field flag to odd and optionally sets
the horizontal phase A Field Sequence (FSEQ) signal; it marks the first field the4 (NTSC),8 (PAL) respectively12 (SECAM) field
sequences. In addition to the odd/even signal, it also
sets the PALphase andoptionally definesthesubcarrier
phase.
On the RCV2 port, the IC can provide a horizontal pulse
with programmable start and stop phase; this pulse canbe
inhibited in the vertical blanking period to build up, for
example, a composite blanking signal.
The horizontal phase can be set via a separate input
RCV2. In the event of VS pulses at RCV1, this is
mandatory.Itis alsopossibletoset the signal pathto blank
via this input.
From the ITU-R BT.656 data stream, the SAA7128AH;
SAA7129AH decodes only the start of the first line in the
odd field. All other information is ignored and may miss. this kind of slave mode is active, the RCV pins may be
switched to output mode.
In slave mode, the horizontal trigger phase can be
programmed to any point in the line, the vertical phase
from line0to line15 counted from the first serration pulse
in half line steps.
Whenever synchronization information cannotbe derived
directly from the inputs, the SAA7128AH; SAA7129AH will
calculate it from the internal horizontal, vertical and PAL
phase. This gives good flexibility with respect to external
synchronization, but the circuit does not suppress illegal
settings. In such an event, the odd/even information may
vanish as it does in the non-interlaced modes.
In master mode, the line lengths are fixed to 1728 clocks
at 50 Hz and 1716 clocks at 60 Hz. To allow
non-interlaced frames, the field lengths can be varied by
±0.5 lines.In the eventof non-interlace, the SAA7128AH;
SAA7129AH does not provide odd/even information and
the output signal does not contain the PAL ‘Bruch
sequence’.
At the RCV1 pin the IC can provide:A Vertical Sync (VS) signal with 2.5 (50 Hz)or3 (60 Hz)
lines duration An odd/even signal which is LOW in odd fields A Field Sequence (FSEQ) signal which is HIGH in the
first field of the 4, 8 respectively 12 field sequences.
At the RCV2 pin, there is a horizontal pulse of
programmable phase and duration available. This pulse
canbe suppressedin the programmable inactive partofa
field, giving a composite blank signal.
The directions and polarities of the RCV ports can be
chosen independently. Timing references canbe foundin
Tables52 and 60.
7.8 Clock
The input to LLC1 can either be an external clock source
or the buffered on-chip clock XCLK. The internal crystal
oscillator can be run with either a 3rd-harmonic or a
fundamental crystal frequency.
7.9 I2 C-bus interface
The I2 C-bus interface is a standard slave transceiver,
supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate.It uses 8-bit subaddressing with
an auto-increment function. All registers are write and
readable, except one read only status byte.
The I2 C-bus slave address is defined as 88H with pin21
(SA) tied LOW and as 8CH with pin 21 (SA) tied HIGH.
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
7.10 Input levels and formats
The SAA7128AH; SAA7129AH expects digital Y, CB
and CR data with levels (digital codes)in accordance with
“ITU-R BT.601”.
For C and CVBS outputs, deviating amplitudes of the
colour difference signals can be compensated by
independent gain control setting, while gainfor luminance
is set to predefined values, distinguishable for 7.5 IRE
set-up or without set-up.
The RGB, respectively CR-Y-CB path features a gain
setting individually for luminance (GY) and colour
difference signals (GCD).
Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.
Table 1 “ITU-R BT.601” signal component levels
Notes Transformation:R=Y+ 1.3707× (CR− 128)G=Y− 0.3365× (CB− 128)− 0.6982× (CR− 128)B=Y+ 1.7324× (CB− 128). Representation of R,G and B (or CR,Y and CB) at the output is 9 bits at 27 MHz.
Table 2 8-bit multiplexed format (similar to “ITU-R BT.601”)
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
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Bit allocation map
le 3Sla
receiv
er (sla
address 88H)
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
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Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
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All bits labelled ‘0’ are reserved. They must be programmed with logic
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
7.12I2 C-bus format
Table 4I2 C-bus address; see Table5
Table 5 Explanation of Table4
Notes X is the read/write control bit; X= logic 0 is order to write; X= logic 1 is order to read. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed.
7.13 Slave receiver
Table 6 Subaddress 26H
Table 7 Subaddress 27H
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
Table 8 Subaddress 28H
Table 9 Subaddress 29H
Table 10 Subaddress 2AH
Table 11 Subaddress 2BH
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
Table 12 Subaddress 2CH
Table 13 Subaddress 2DH
Table 14 Subaddress 38H
Table 15 Subaddress 39H
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
Table 16 Subaddress 3AH
Table 17 Subaddresses 42Hto 44H and 48Hto 4AH
Table 18 Subaddresses 45Hto 47H and 4BHto 4DH
Table 19 Subaddress 4EH
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
Table 20 Subaddress 4FH
Table 21 Subaddress 50H
Table 22 Subaddress 51H
Table 23 Subaddress 52H
Table 24 Subaddress 53H
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
Table 25 Subaddress 54H
Table 26 Subaddress 55H
Table 27 Subaddress 56H
Table 28 Subaddress 57H
Table 29 Subaddress 58H
Table 30 Subaddress 59H
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
Table 31 Subaddress 5AH
Table 32 Subaddress 5BH
Table 33 GAINU values
Note All IRE values are rounded up.
Table 34 Subaddress 5CH
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
Table 35 GAINV values
Note All IRE values are rounded up.
Table 36 Subaddress 5DH
Table 37 BLCKL values
Notes All IRE values are rounded up. Output black level/IRE= BLCKL× 2/6.29+ 28.9. Output black level/IRE= BLCKL× 2/6.18+ 26.5.
Table 38 Subaddress 5EH
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
Table 39 BLNNL values
Notes All IRE values are rounded up. Output black level/IRE= BLNNL× 2/6.29+ 25.4. Output black level/IRE= BLNNL× 2/6.18+ 25.9; default after reset: 35H.
Table 40 Subaddress 5FH
Table 41 Selection of cross-colour reduction filter
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
Table 42 Subaddress 61H
Table 43 Subaddress 62H
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
Table 44 BSTA values
Note All IRE values are rounded up.
Table 45 Subaddresses 63Hto 66H
Note Examples: NTSC-M:fsc= 227.5, fllc= 1716→ FSC= 569408543 (21F07C1FH). PAL-B/G:fsc= 283.7516, fllc= 1728→ FSC= 705268427 (2A098ACBH). SECAM:fsc= 274.304, fllc= 1728→ FSC= 681786290 (28A33BB2H).
Table 46 Subaddress 67H
Philips Semiconductors Product specification
Digital video encoder SAA7128AH; SAA7129AH
Table 47 Subaddress 68H
Table 48 Subaddress 69H
Table 49 Subaddress 6AH
