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Partno	Mfg	Dc	Qty	Available	Descript
RIVA128	ST	N/a	50	avai	128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128 ,128-BIT 3D MULTIMEDIA ACCELERATORTABLE OF CONTENTS1 REVISION HISTORY. 41 RIVA 128 300PBGA DEVICE PINOUT 52 PIN DESCRIPTIONS . 62.1 ..
RIVA128ZX ,128-BIT 3D MULTIMEDIA ACCELERATORTABLE OF CONTENTS1 RIVA128ZX 300PBGA DEVICE PINOUT...... 42 PIN DESCRIPTIONS . 52.1 ACCELERATED GRA ..
RIVA128ZX ,128-BIT 3D MULTIMEDIA ACCELERATORFEATURES ....... 458.2 BI-DIRECTIONAL MEDIA PORT POLLING COMMANDS USING MPC ... 468.3 TIMING DIAGRA ..
RJH60F5DPK , Silicon N Channel IGBT High Speed Power Switching
RJH60F7ADPK , Silicon N Channel IGBT High Speed Power Switching
RJJ0101DPD , P Channel Power MOS FET High Speed Switching
RSS085N05 , 4V Drive Nch MOSFET
RSS090 N03 , Switching (30V, 9A)
RSS090N03 , Switching (30V, 9A)
RSS090N03 , Switching (30V, 9A)
RSS120N03 , Switching (30V, 12A)
RSS125N03 , Switching (30V, 12.5A)

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RIVA128
128-BIT 3D MULTIMEDIA ACCELERATOR
BLOCK DIAGRAM
DESCRIPTION
The RIVA 128™ is the first 128-bit 3D Multimedia
Accelerator to offer unparalleled 2D and 3D perfor-
mance, meeting all the requirements of the main-
stream PC graphics market and Microsoft’s
PC’97. The RIVA 128 introduces the most ad-
vanced Direct3D™ acceleration solution and also
delivers leadership VGA, 2D and Video perfor-
mance, enabling a range of applications from 3D
games through to DVD, Intercast™ and video con-
ferencing.
KEY FEATURES Fast 32-bit VGA/SVGA High performance 128-bit 2D/GUI/DirectDraw
Acceleration Interactive, Photorealistic Direct3D Accelera-
tion with advanced effects Massive 1.6Gbytes/s, 100MHz 128-bit wide
frame buffer interface Video Acceleration for DirectDraw/DirectVideo,
MPEG-1/2 and Indeo® Planar 4:2:0 and packed 4:2:2 Color Space
Conversion X and Y smooth up and down scaling 230MHz Palette-DAC supporting up to
1600x1200@75Hz NTSC and PAL output with flicker-filter Multi-function Video Port and serial interface Bus mastering DMA 66MHz Accelerated
Graphics Port (AGP) 1.0 Interface Bus mastering DMA PCI 2.1 interface 0.35 micron 5LM CMOS 300 PBGA
TABLE OF CONTENTS REVISION HISTORY...................................................................................................................... 4 RIVA 128 300PBGA DEVICE PINOUT .......................................................................................... 5 PIN DESCRIPTIONS...................................................................................................................... 6
2.1 ACCELERATED GRAPHICS PORT (AGP) INTERFACE..................................................... 6
2.2 PCI 2.1 LOCAL BUS INTERFACE ........................................................................................ 6
2.3 SGRAM FRAMEBUFFER INTERFACE ................................................................................ 8
2.4 VIDEO PORT......................................................................................................................... 8
2.5 DEVICE ENABLE SIGNALS.................................................................................................. 9
2.6 DISPLAY INTERFACE .......................................................................................................... 9
2.7 VIDEO DAC AND PLL ANALOG SIGNALS .......................................................................... 9
2.8 POWER SUPPLY .................................................................................................................. 9
2.9 TEST...................................................................................................................................... 10 OVERVIEW OF THE RIVA 128...................................................................................................... 11
3.1 BALANCED PC SYSTEM...................................................................................................... 11
3.2 HOST INTERFACE ...............................................................................................................11
3.3 2D ACCELERATION ............................................................................................................. 12
3.4 3D ENGINE ........................................................................................................................... 12
3.5 VIDEO PROCESSOR............................................................................................................ 12
3.6 VIDEO PORT......................................................................................................................... 13
3.7 DIRECT RGB OUTPUT TO LOW COST PAL/NTSC ENCODER ......................................... 13
3.8 SUPPORT FOR STANDARDS.............................................................................................. 13
3.9 RESOLUTIONS SUPPORTED.............................................................................................. 13
3.10 CUSTOMER EVALUATION KIT............................................................................................ 14
3.11 TURNKEY MANUFACTURING PACKAGE........................................................................... 14 ACCELERATED GRAPHICS PORT (AGP) INTERFACE............................................................. 15
4.1 RIVA 128 AGP INTERFACE ................................................................................................. 16
4.2 AGP BUS TRANSACTIONS.................................................................................................. 16 PCI 2.1 LOCAL BUS INTERFACE................................................................................................. 22
5.1 RIVA 128 PCI INTERFACE ................................................................................................... 22
5.2 PCI TIMING SPECIFICATION............................................................................................... 23 SGRAM FRAMEBUFFER INTERFACE......................................................................................... 29
6.1 SGRAM INITIALIZATION...................................................................................................... 31
6.2 SGRAM MODE REGISTER .................................................................................................. 31
6.3 LAYOUT OF FRAMEBUFFER CLOCK SIGNALS ................................................................ 32
6.4 SGRAM INTERFACE TIMING SPECIFICATION.................................................................. 32 VIDEO PLAYBACK ARCHITECTURE........................................................................................... 37
7.1 VIDEO SCALER PIPELINE ................................................................................................... 38 VIDEO PORT.................................................................................................................................. 40
8.1 VIDEO INTERFACE PORT FEATURES ............................................................................... 40
8.2 BI-DIRECTIONAL MEDIA PORT POLLING COMMANDS USING MPC .............................. 41
8.3 TIMING DIAGRAMS..............................................................................................................42
8.4 656 MASTER MODE............................................................................................................. 46
8.5 VBI HANDLING IN THE VIDEO PORT ................................................................................. 47
8.6 SCALING IN THE VIDEO PORT........................................................................................... 47 BOOT ROM INTERFACE............................................................................................................... 48
POWER-ON RESET CONFIGURATION........................................................................................ 50 DISPLAY INTERFACE................................................................................................................... 5211.1 PALETTE-DAC...................................................................................................................... 52
11.2 PIXEL MODES SUPPORTED............................................................................................... 52
11.3 HARDWARE CURSOR ......................................................................................................... 53
11.4 I2C INTERFACE.................................................................................................................... 54
11.5 ANALOG INTERFACE .......................................................................................................... 55
11.6 TV OUTPUT SUPPORT ........................................................................................................ 56 IN-CIRCUIT BOARD TESTING......................................................................................................58
12.1 TEST MODES ....................................................................................................................... 58
12.2 CHECKSUM TEST................................................................................................................ 58 ELECTRICAL SPECIFICATIONS .................................................................................................. 59
13.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................ 59
13.2 OPERATING CONDITIONS .................................................................................................. 59
13.3 DC SPECIFICATIONS...........................................................................................................59
13.4 ELECTRICAL SPECIFICATIONS.......................................................................................... 60
13.5 DAC CHARACTERISTICS .................................................................................................... 60
13.6 FREQUENCY SYNTHESIS CHARACTERISTICS................................................................ 61 PACKAGE DIMENSION SPECIFICATION.................................................................................... 62
14.1 300 PIN BALL GRID ARRAY PACKAGE .............................................................................. 62 REFERENCES................................................................................................................................ 63 ORDERING INFORMATION ..........................................................................................................63
APPENDIX...................................................................................................................................... 64 PCI CONFIGURATION REGISTERS ............................................................................................. 64
A.1 REGISTER DESCRIPTIONS FOR PCI CONFIGURATION SPACE .................................... 64
REVISION HISTORY
RIVA 128 300PBGA DEVICE PINOUTNOTES NIC = No Internal Connection. Do not connect to these pins. VDD=3.3V Signals denoted with an asterisk are defined for future expansion. See Pin Descriptions, Section 2, page 6 for details.
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