PXAS30KFA ,XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address rangefeatures of the XA-S3• Active low reset output pin indicates all reset occurrences• 2.7 V to 5.5 V ..
PXAS30KFBE ,XA 16-bit microcontroller 32K/1K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16MB address rangeGENERAL DESCRIPTION• Three standard counter/timers with enhanced
PXAS37KBA ,XA 16-bit microcontroller 32K/1K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16MB address rangeGENERAL DESCRIPTION• Three standard counter/timers with enhanced
PXB4330E ,ICs for Communicationscharacteristics.Terms of delivery and rights to change design reserved.For questions on technology, ..
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PXAS30KFA
XA 16-bit microcontroller family
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
GENERAL DESCRIPTIONThe XA-S3 device is a member of NXP Semiconductors’ XA(eXtended Architecture) family of high performance 16-bitsingle-chip microcontrollers.
The XA-S3 device combines many powerful peripherals on onechip. With its high performance A/D converter, timers/counters,watchdog, Programmable Counter Array (PCA), I2 C interface, dualUARTs, and multiple general purpose I/O ports, it is suited for general multipurpose high performance embedded control functions.
Specific features of the XA-S3• 2.7 V to 5.5 V operation. 32 K bytes of on-chip EPROM/ROM program memory. 1024 bytes of on-chip data RAM. Supports off-chip addressing up to 16 megabytes (24 address
lines). A clock output reference is added to simplify external businterfacing.• High performance 8-channel 8-bit A/D converter with automatic
channel scan and repeated read functions. Completes a conversion in 4.46 microseconds at 30 MHz. Alternate operatingmode allows 10-bit conversion results. Three standard counter/timers with enhanced features. All timers
have a toggle output capability.• Watchdog timer. 5-channel 16-bit Programmable Counter Array (PCA). I2C-bus serial I/O port with byte-oriented master and slave
functions.• Two enhanced UARTs with independent baud rates. Seven software interrupts. Active low reset output pin indicates all reset occurrences
(external reset, watchdog reset and the RESET instruction). A reset source register allows program determination of the causeof the most recent reset.• 50 I/O pins, each with four programmable output configurations. 30 MHz operating frequency at 2.7 V to 5.5 V VDD. Power saving operating modes: Idle and Power-down. Wake-up
from power-down via an external interrupt is supported.• 68-pin PLCC and 80-pin PQFP packages.
ORDERING INFORMATION
NOTE: 1. Corrected SOT number; no physical change.
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
PIN CONFIGURATIONS
68-pin PLCC package
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
80-pin LQFP package
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
LOGIC SYMBOL
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
BLOCK DIAGRAMSFRbus
ProgramMemoryBus
DataBus
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
PIN DESCRIPTIONS
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
Table 1. Special Function Registers
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
NOTES:* SFRs are bit addressable.# SFRs are modified from or added to XA-G3 SFRs.1. At reset, the BCR is loaded with the binary value 00000a11, where “a’ is the value on the BUSW pin. This defaults the address bus size to 24 bits.2. SFR is loaded from the reset vector.3. All bits except F1, F0, and P are loaded from the reset vector. Those bits are all 0.4. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for otherpurposes in future XA derivatives. The reset value shown for these bits is 0.5. Port configurations default to quasi-bidirectional when the XA begins execution from internal code memory after reset, based on thecondition found on the EA pin. Thus, all PnCFGA registers will contain FF , and PnCFGB register will contain 00 when the XA beginsexecution using internal code memory. When the XA begins execution using external code memory , the default configuration for pins thatare associated with the external bus will be push-pull. The PnCFGA and PnCFGB register contents will reflect this dif ference.6. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes.7. The RSTSRC register reflects the cause of the last XA-S3 reset. One bit will be set to 1, the others will be cleared to 0.8. The XA guards writes to certain bits (typically interrupt flags) that may be altered directly by a peripheral function. This prevents loss of aninterrupt or other status if a bit was written directly by a peripheral action during the time between the read and write porti ons of aninstruction that performs a read-modify-write operation. Examples of such instructions are:and s0con,#$fbclr tr0setb ti_0 XA-S3 SFR bits that are guarded in this manner are: ADINT (in ADCON); CF, CCF4, CCF3, CCF2, CCF1, and CCF0 (in CCON); SI (in
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
Figure 1. XA-S3 program memory map
Figure 2. XA-S3 data memory map
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
FUNCTIONAL DESCRIPTIONDetails of XA-S3 functions will be described in the following sections.
Analog to Digital converterThe XA-S3 has an 8-channel, 8-bit A/D converter with 8 sets of resultregisters, single scan and multiple scan operating modes. The A/Dalso has a 10-bit conversion mode that provides greater result resolution. The A/D input range is limited to 0 to AVDD (3.3 V max.).The A/D inputs are on Port 5. Analog Power and Ground as well asAVREF+ and AVREF– must be supplied in order for the A/D converter tobe used. Prior to enabling the A/D converter or driving analog signalsinto the A/D inputs, the port configurations for the pins being used asA/D inputs must be set to the “off” (high impedance, input only) mode.
A/D timing can be adapted to the application clock frequency inorder to provide the fastest possible conversion.
A/D converter operation is controlled through the ADCON (A/D Control)register, see Figure 1. Bits in ADCON start and stop the A/D, flag conversion completion, and select the converter operating modes. When10-bit resolution is needed, the A/D mode may be set to give 10 resultbits by setting the ADRES bit to 1. In this mode, the A/D takes longer tocomplete a conversion, and the timing must be set differently in ADCFG.
A/D Conversion Modes The A/D converter supports a single scan mode and a continuousscan mode. In either mode, one or more A/D channels may beconverted. The ADCS register determines which channels are converted. If the corresponding bit in the ADCS register is set, thatchannel is selected for conversions, otherwise that channel isskipped. The ADCS register is detailed in Figure 2.
For any A/D conversion, the results are stored in ADRSHn,corresponding to the A/D channel just converted. For a 10-bit conversion, the two least significant bits are read from the upper end
of register ADRSL. These bits must be read before anotherconversion is begun.
A/D conversions are begun by setting the A/D Start and STatus bit inADCON. In the single scan mode, all of the channels selected bybits in the ADCS register will be converted once. The ADINT flag isset when the last channel is converted. In the continuous scanmode, the A/D converter continuously converts all A/D channels selected by bits in the ADCS register. The ADINT flag is set when allchannels have been converted once.
The A/D converter can generate an interrupt when the ADINT flag isset. This will occur if the A/D interrupt is enabled (via the EAD bit inIEL), the interrupt system is enabled (via the EA bit in IEL), and theA/D interrupt priority (specified in IPA3 bits 3 to 0) is higher than thecurrently running code (PSW bits IM3 through IM0) and any otherpending interrupt. ADINT must be cleared by software.
A/D Timing Configuration The A/D sampling and conversion timing may be optimized for theparticular oscillator frequency and input drive characteristics of theapplication. Because A/D operation is mostly dependent on real-timeeffects (charging time of sampling capacitors, settling time of thecomparator, etc.), A/D conversion times are not necessarily muchlonger at slower clock frequencies. The A/D timing is controlled bythe ADCFG register, as shown in Figure 3, T able 2 and Table 3.
The primary effect of ADCFG settings is to adjust the A/D sampleand hold time to be relatively constant over various clock
frequencies. Two settings (value 6 and B) are provided to allow fastconversions with a lower external source driving the A/D inputs.
These settings provide double the sample time at the same frequency. Of course, settings intended for lower frequencies mayalso be used at higher frequencies in order to increase the A/Dsampling time, but this method has the side effect of significantlyincreasing A/D conversion times.
Figure 1. A/D Control Register (ADCON)
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
Figure 2. A/D Channel Select Register (ADCS)
Figure 3. A/D Timing Configuration Register (ADCFG)
Table 2. A/D Timing Configuration
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
Table 3. A/D Timing Configuration for 10-bit Mode
A/D Inputs In order to obtain accurate measurements with the A/D Converter,the source drive must be sufficient to adequately charge the sampling capacitor during the sampling time. Figure 4 shows theequivalent resistance and capacitance related to the A/D inputs.A/D timing configurations indicated in Table 1 allow for full A/D
accuracy (according to the A/D specifications) assuming a sourceresistance of less than or equal to 20kΩ. Larger source resistancesmay be accommodated by increasing the sampling time with adifferent A/D timing configuration. CC
TO COMPARATOR
ADN
ADN+1 SmN+1
SmN
RmN+1
RmN
Multiplexer
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
A/D Accuracy The XA-S3 A/D in 10 -bit mode is specified with 16 samplesaveraged in order to factor out on-chip noise. In an applicationwhere averaging 16 samples is not practical, the accuracy specifications may be de-rated according to the number of samples
that are actually taken. The graph in Figure 5 shows the relationshipof additional A/D error to the number of samples that are averaged.For example, if a single A/D reading is used with no averaging, theA/D accuracy should be de-rated by ±1.25 LSB.
Figure 5. A/D accuracy by number of averaging samples (Pertains to 10-bit mode only. Note that 10-bit mode is only specified up to fC = 20 MHz.)
Figure 6. I2 C Control Register (I2CON)
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
2 C InterfaceThe I2 C interface on the XA-S3 is identical to the standard byte-styleI2 C interface found on devices such as the 8xC552 except for therate selection. The I2C interface conforms to the 100 kHz I2C
specification, but may be used at rates up to 400 kHz(non-conforming).
Important: Before the I2 C interface may be used, the port pinsP5.6 and 5.7, which correspond to the I2C functions SCL and SDArespectively, must be set to the open drain mode.
The processor interfaces to the I2C logic via the following four special function registers: I2CON (I2C control register), I2STA (I2Cstatus register), I2DAT (I2 C data register), and I2ADR (I2 C slaveaddress register). The I2C control logic interfaces to the external I2Cbus via two port 5 pins: P5.6/SCL (serial clock line) and P5.7/SDA(serial data line).
The Control Register, I2CON This register is shown in Figure 6. Two bits are affected by the I2Chardware: the SI bit is set when a serial interrupt is requested, andthe STO bit is cleared when a STOP condition is present on the I2Cbus. The STO bit is also cleared when ENA = “0”.
ENA, the I2C Enable BitENA = 0: When ENA is “0”, the SDA and SCL outputs are notdriven. SDA and SCL input signals are ignored, SIO1 is in the “notaddressed” slave state, and the STO bit in I2CON is forced to “0”.No other bits are affected. P5.6 and P5.7 may be used as opendrain I/O ports.
ENA = 1: When ENA is “1”, SIO1 is enabled. The P5.6 and P5.7port latches must be set to logic 1.
ENA should not be used to temporarily release the I2C-bus since,when ENA is reset, the I2C-bus status is lost. The AA flag should beused instead (see description of the AA flag in the following text).
In the following text, it is assumed the ENA = “1”.
STA, the START flagSTA = 1: When the STA bit is set to enter a master mode, the I2Chardware checks the status of the I2 C bus and generates a STARTcondition if the bus is free. If the bus is not free, the I2 C interfacewaits for a STOP condition (which will free the bus) and generates aSTART condition after a delay of a half clock period of the internalserial clock generator.
If STA is set while the I2C interface is already in a master mode andone or more bytes are transmitted or received, the hardware transmits a repeated START condition. STA may be set at any time.STA may also be set when the I2 C interface is an addressed slave.
STA = 0: When the STA bit is reset, no START condition orrepeated START condition will be generated.
STO, the STOP flagSTO = 1: When the STO bit is set while the I2C interface is in amaster mode, a STOP condition is transmitted to the I2C bus. Whenthe STOP condition is detected on the bus, the hardware clears theSTO flag. In a slave mode, the STO flag may be set to recover froman error condition. In this case, no STOP condition is transmitted tothe I2 C bus. However, the hardware behaves as if a STOP conditionhas been received and switches to the defined “not addressed” slavereceiver mode. The STO flag is automatically cleared by hardware.
If the STA and STO bits are both set, then a STOP condition istransmitted to the I2 C bus if the interface is in a master mode (in aslave mode, the hardware generates an internal STOP conditionwhich is not transmitted). The I2 C interface then transmits a STARTcondition.
STO = 0: When the STO bit is reset, no STOP condition will begenerated.
SI, the Serial Interrupt flagSI = 1: When the SI flag is set, and the EA (interrupt systemenable) and EI2 (I2C interrupt enable) bits are also set, an I2C interrupt is requested. SI is set by hardware when one of 25 of the26 possible I2C interface states is entered. The only state that doesnot cause SI to be set is state F8H, which indicates that no relevantstate information is available.
While SI is set, the low period of the serial clock on the SCL line isstretched, and the serial transfer is suspended. A high level on theSCL line is unaffected by the serial interrupt flag. SI must be resetby software.
SI = 0: When the SI flag is reset, no serial interrupt is requested,and there is no stretching of the serial clock on the SCL line.
AA, the Assert Acknowledge flagAA = 1: If the AA flag is set, an acknowledge (low level to SDA) willbe returned during the acknowledge clock pulse on the SCL line when: The “own slave address” has been received. The general call address has been received while the general call
bit (GC) in I2ADR is set. A data byte has been received while the I2C interface is in the
master receiver mode. A data byte has been received while the I2C interface is in the
addressed slave receiver mode.
AA = 0: If the AA flag is reset, a not acknowledge (high level toSDA) will be returned during the acknowledge clock pulse on theSCL line when:• A data byte has been received while the I2C interface is in the
master receiver mode. A data byte has been received while the I2 C interface is in the
addressed slave receiver mode.
When the I2C interface is in the addressed slave transmitter mode,state C8H will be entered after the last serial data byte is transmitted. When SI is cleared, the I2C interface leaves state C8H,enters the not addressed slave receiver mode, and the SDA lineremains at a high level. In state C8H, the AA flag can be set againfor future address recognition.
When the I2C interface is in the not addressed slave mode, its ownslave address and the general call address are ignored. Consequently,no acknowledge is returned, and a serial interrupt is not requested.Thus, the hardware can be temporarily released from the I2C bus while the bus status is monitored. While the hardware is released fromthe bus, START and STOP conditions are detected, and serial data isshifted in. Address recognition can be resumed at any time by settingthe AA flag. If the AA flag is set when the part’s own slave address orthe general call address has been partly received, the address will berecognized at the end of the byte transmission.
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
CR0, CR1, and CR2, the Clock Rate Bits These three bits determine the serial clock frequency when the I2Cinterface is in a master mode. An I2 C rate of 100kHz or lower istypical and can be derived from many oscillator frequencies. Thevarious serial rates are shown in Table 4. A variable bit rate mayalso be used if Timer 1 is not required for any other purpose whilethe I2C hardware is in a master mode. The frequencies shown inTable 4 are unimportant when the I2C hardware is in a slave mode.In the slave modes, the hardware will automatically synchronize withthe incoming clock frequency.
The I2 C Status Register, I2STAI2STA is an 8-bit read-only special function register. The three leastsignificant bits are always zero. The five most significant bits containthe status code. There are 26 possible status codes. When I2STAcontains F8H, no relevant state information is available and no serialinterrupt is requested. All other I2STA values correspond to definedhardware interface states. When each of these states is entered, aserial interrupt is requested (SI = “1”).
NOTE: A detailed I2 C interface description and usage information, including example driver code, will be provided ina separate document.
Table 4. I2 C Rate Control
NOTES:1. The XA-S3 I2C interface does not conform to the 400kHz I2C specification (which applies to rates greater than 100kHz) in all details, butmay be used with care where higher rates are required by the application.2. The timer 1 overflow is used to clock the I2C interface. The resulting bit rate is 1/2 of the timer overflow rate.
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
XA-S3 Timer/CountersThe XA-S3 has three general purpose counter/timers, two of which mayalso be used as baud rate generators for either or both of the UARTs.
Timer 0 and 1 These are identical to the standard XA-G3 timer 0 and 1.
Timer 2 This is identical to the standard XA-G3 timer 2.
Programmable Counter Array (PCA) The Programmable Counter Array available on the XA-S3 is aspecial 16-bit Timer that has five 16-bit capture/compare modulesassociated with it. Each of the modules can be programmed tooperate in one of four modes: rising and/or falling edge capture,software timer, high-speed output, or pulse width modulator. Eachmodule has a pin associated with it in port 1. Module 0 is connectedto P4.1(CEX0), module 1 to P4.2(CEX1), etc. The basic PCAconfiguration is shown in Figure 7.
The PCA timer is a common time base for all five modules and canbe programmed to run at: the TCLK rate (Osc/4, Osc/16, or Osc/64),the Timer 0 overflow, or the input on the ECI pin (P4.0). When theECI input is used, the falling edge clocks the PCA counter. The timercount source is determined from the CPS1 and CPS0 bits in theCMOD SFR as follows (see Figure 10):
CPS1 CPS0 PCA Timer Count Source0 X TCLK (Osc/4, Osc/16, or Osc/64)1 0 Timer 0 overflow1 1 ECI (PCA External Clock Input (max rate = Osc/4)
In the CMOD SFR are three additional bits associated with the PCA.They are CIDL which allows the PCA to stop during idle mode,WDTE which enables or disables the watchdog function on module 4, and ECF which when set causes an interrupt and thePCA overflow flag CF (in the CCON SFR) to be set when the PCAtimer overflows. These functions are shown in Figure 8. In addition,each PCA module may generate a separate interrupt.
The watchdog timer function is implemented in module 4 (seeFigure 17).
The CCON SFR contains the run control bit for the PCA and theflags for the PCA timer (CF) and each module (refer to Figure 11).To run the PCA the CR bit (CCON.6) must be set by software. ThePCA is shut off by clearing this bit. The CF bit (CCON.7) is set whenthe PCA counter overflows and an interrupt will be generated if theECF bit in the CMOD register is set, The CF bit can only be clearedby software. Bits 0 through 4 of the CCON register are the flags forthe modules (bit 0 for module 0, bit 1 for module 1, etc.) and are setby hardware when either a match or a capture occurs. These flagsalso can only be cleared by software. The PCA interrupt systemshown in Figure 9.
Each module in the PCA has a special function register associatedwith it. These registers are: CCAPM0 for module 0, CCAPM1 formodule 1, etc. (see Figure 12). The registers contain the bits thatcontrol the mode that each module will operate in. The ECCF bit(CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module)enables the CCF flag in the CCON SFR to generate an interruptwhen a match or compare occurs in the associated module. PWM(CCAPMn.1) enables the pulse width modulation mode. The TOGbit (CCAPMn.2) when set causes the CEX output associated withthe module to toggle when there is a match between the PCA counter and the module’s capture/compare register. The match bitMAT (CCAPMn.3) when set will cause the CCFn bit in the CCONregister to be set when there is a match between the PCA counterand the module’s capture/compare register.
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPNbit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and acapture will occur for either transition. The last bit in the registerECOM (CCAPMn.6) when set enables the comparator function.Figure 13 shows the CCAPMn settings for the various PCAfunctions.
There are two additional registers associated with each of the PCAmodules. They are CCAPnH and CCAPnL and these are theregisters that store the 16-bit count when a capture occurs or acompare should occur. When a module is used in the PWM modethese registers are used to control the duty cycle of the output.
Figure 7. Programmable Counter Array (PCA)
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
Figure 8. PCA Timer/Counter
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
Figure 10. CMOD: PCA Counter Mode Register
Figure 11. CCON: PCA Counter Control Register
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
Figure 12. CCAPMn: PCA Modules Compare/Capture Registers
Figure 13. PCA Module Modes (CCAPMn Register)
PCA Capture Mode To use one of the PCA modules in the capture mode either one orboth of the CCAPM bits CAPN and CAPP for that module must beset. The external CEX input for the module (on port 1) is sampled fora transition. When a valid transition occurs the PCA hardware loadsthe value of the PCA counter registers (CH and CL) into the module’s capture registers (CCAPnL and CCAPnH). If the CCFn bitfor the module in the CCON SFR and the ECCFn bit in the CCAPMnSFR are set then an interrupt will be generated. Refer to Figure 14.
16-bit Software Timer Mode The PCA modules can be used as software timers by setting boththe ECOM and MAT bits in the modules CCAPMn register. The PCAtimer will be compared to the module’s capture registers and when amatch occurs an interrupt will occur if the CCFn (CCON SFR) andthe ECCFn (CCAPMn SFR) bits for the module are both set (seeFigure 15).
counter and the module’s capture registers. To activate this modethe TOG, MAT, and ECOM bits in the module’s CCAPMn SFR mustbe set (see Figure 16).
Pulse Width Modulator Mode All of the PCA modules can be used as PWM outputs. Figure 17shows the PWM function. The frequency of the output depends onthe source for the PCA timer. All of the modules will have the samefrequency of output because they all share the PCA timer. The dutycycle of each module is independently variable using the module’scapture register CCAPLn. When the value of the PCA CL SFR isless than the value in the module’s CCAPLn SFR the output will below, when it is equal to or greater than the output will be high. WhenCL overflows from FF to 00, CCAPLn is reloaded with the value inCCAPHn. the allows updating the PWM without glitches. The PWMand ECOM bits in the module’s CCAPMn register must be set toenable the PWM mode.
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
Figure 14. PCA Capture Mode
Figure 15. PCA Compare Mode
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
Figure 16. PCA High Speed Output Mode
Figure 17. PCA PWM Mode
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
Figure 18. PCA Watchdog Timer m(Module 4 only)
PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improvethe reliability of the system without increasing chip count. Watchdogtimers are useful for systems that are susceptible to noise, powerglitches, or electrostatic discharge. Module 4 is the only PCAmodule that can be programmed as a watchdog. However, thismodule can still be used for other modes if the watchdog is notneeded.
Figure 18 shows a diagram of how the watchdog works. The userpre-loads a 16-bit value in the compare registers. Just like the othercompare modes, this 16-bit value is compared to the PCA timervalue. If a match is allowed to occur, an internal reset will begenerated. This will not cause the RST pin to be driven low.
In order to hold off the reset, the user has three options:1. periodically change the compare value so it will never match thePCA timer, periodically change the PCA timer value so it will never matchthe compare values, or disable the watchdog by clearing the WDTE bit before a matchoccurs and then re-enable it.
The first two options are more reliable because the watchdog timeris never disabled as in option #3. If the program counter ever goesastray, a match will eventually occur and cause an internal reset.The second option is also not recommended if other PCA modulesare being used. Remember, the PCA timer is the time base for allmodules; changing the time base for other modules would not be agood idea. Thus, in most applications the first solution is the bestoption.
Figure 19 shows the code for initializing the watchdog timer. Module4 can be configured in either compare mode, and the WDTE bit inCMOD must also be set. The user’s software then must periodicallychange (CCAP4H,CCAP4L) to keep a match from occurring with thePCA timer (CH,CL). This code is given in the WATCHDOG routine inFigure 19.
This routine should not be part of an interrupt service routine,because if the program counter goes astray and gets stuck in an
infinite loop, interrupts will still be serviced and the watchdog willkeep getting reset. Thus, the purpose of the watchdog would be
defeated. Instead, call this subroutine from the main program within216 count of the PCA timer.
NXP Semiconductors Product specification
XA-S3XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2 C, 2 UARTs, 16 MB address range
Figure 19. PCA Watchdog Timer Initialization Code
Watchdog Timer This is a standard XA-G3 watchdog timer. This watchdog timer always comes up running at reset. The watchdog acts the same onEPROM, ROM, and ROMless parts, as in the XA-G3.
UARTs Standard XA-S3 UART0 and UART1 with double buffered transmitregister. A flag has been added to SnSTAT that is set if any of thestatus flags (BRn, FEn, or OEn) is set for the corresponding UARTchannel. This allows polling for UART errors quickly at the interruptservice routine. Baud rate sources may be timer 1 or timer 2.
The XA-S3 includes 2 UART ports that are compatible with theenhanced UART used on the XA-G3.
The UART has separate interrupt vectors for each UART’s transmitand receive functions. The UART transmitter has been doublebuffered, allowing packed transmission of data with no gaps between bytes and less critical interrupt service routine timing. Abreak detect function has been added to the UART. This operatesindependently of the UART itself and provides a start-of-breakstatus bit that the program may test. An Overrun Error flag allowsdetection of missed characters in the received data stream. Thedouble buffered UART transmitter may require some softwarechanges if code is used that was written for the original XA-G3single buffered UART.
Each UART baud rate is determined by either a fixed division of theoscillator (in UART modes 0 and 2) or by the timer 1 or timer 2overflow rate (in UART modes 1 and 3).
Timer 1 defaults to clock both UART0 and UART1. Timer 2 can beprogrammed to clock either UART0 through T2CON (via bits R0CLKand T0CLK) or UART1 through T2MOD (via bits R1CLK and T1CLK). In this case, the UART not clocked by T2 could use T1 as
transmit register, and reading SnBUF accesses a physicallyseparate receive register.
The serial port can operate in 4 modes:
Mode 0: Serial I/O expansion mode. Serial data enters and exitsthrough RxDn. TxDn outputs the shift clock. 8 bits are transmitted/received (LSB first). (The baud rate is fixed at 1/16 theoscillator frequency.)
Mode 1: Standard 8-bit UART mode. 10 bits are transmitted(through TxDn) or received (through RxDn): a start bit (0), 8 databits (LSB first), and a stop bit (1). On receive, the stop bit goes intoRB8 in Special Function Register SnCON. The baud rate is variable.
Mode 2: Fixed rate 9-bit UART mode. 11 bits are transmitted(through TxD) or received (through RxD): start bit (0), 8 data bits(LSB first), a programmable 9th data bit, and a stop bit (1). OnTransmit, the 9th data bit (TB8_n in SnCON) can be assigned thevalue of 0 or 1. Or, for example, the parity bit (P, in the PSW) couldbe moved into TB8_n. On receive, the 9th data bit goes into RB8_nin Special Function Register SnCON, while the stop bit is ignored.The baud rate is programmable to 1/32 of the oscillator frequency.
Mode 3: Standard 9-bit UART mode. 11 bits are transmitted(through TxDn) or received (through RxDn): a start bit (0), 8 databits (LSB first), a programmable 9th data bit, and a stop bit (1).In fact, Mode 3 is the same as Mode 2 in all respects except baudrate. The baud rate in Mode 3 is variable.
In all four modes, transmission is initiated by any instruction thatuses SnBUF as a destination register. Reception is initiated inMode 0 by the condition RI_n = 0 and REN_n = 1. Reception isinitiated in the other modes by the incoming start bit if REN_n = 1.
