PXAS30KBBE ,XA 16-bit microcontroller familyINTEGRATED CIRCUITSXA-S3XA 16-bit microcontroller32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D,2low ..
PXAS30KFA ,XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address rangefeatures of the XA-S3• Active low reset output pin indicates all reset occurrences• 2.7 V to 5.5 V ..
PXAS30KFA ,XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address rangefeatures. All timersThe XA-S3 device is a member of NXP Semiconductors’ XAhave a toggle output capa ..
PXAS30KFA ,XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address rangefeatures of the XA-S3• Active low reset output pin indicates all reset occurrences• 2.7 V to 5.5 V ..
PXAS30KFBE ,XA 16-bit microcontroller 32K/1K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16MB address rangeGENERAL DESCRIPTION• Three standard counter/timers with enhanced
PXAS37KBA ,XA 16-bit microcontroller 32K/1K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16MB address rangeGENERAL DESCRIPTION• Three standard counter/timers with enhanced
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PXAS30KBA-PXAS30KBBE-PXAS30KFA-PXAS30KFBE-PXAS37KBA
XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address range
Preliminary specification
Supersedes data of 2000 Aug 22
2000 Dec 01
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
GENERAL DESCRIPTIONThe XA-S3 device is a member of Philips Semiconductors’ XA
(eXtended Architecture) family of high performance 16-bit
single-chip microcontrollers.
The XA-S3 device combines many powerful peripherals on one
chip. With its high performance A/D converter, timers/counters,
watchdog, Programmable Counter Array (PCA), I2 C interface, dual
UARTs, and multiple general purpose I/O ports, it is suited for
general multipurpose high performance embedded control functions.
Specific features of the XA-S3 2.7 V to 5.5 V operation. 32 K bytes of on-chip EPROM/ROM program memory. 1024 bytes of on-chip data RAM. Supports off-chip addressing up to 16 megabytes (24 address
lines). A clock output reference is added to simplify external bus
interfacing. High performance 8-channel 8-bit A/D converter with automatic
channel scan and repeated read functions. Completes a
conversion in 4.46 microseconds at 30 MHz. Alternate operating
mode allows 10-bit conversion results. Three standard counter/timers with enhanced features. All timers
have a toggle output capability. Watchdog timer. 5-channel 16-bit Programmable Counter Array (PCA). I2C-bus serial I/O port with byte-oriented master and slave
functions. Two enhanced UARTs with independent baud rates. Seven software interrupts. Active low reset output pin indicates all reset occurrences
(external reset, watchdog reset and the RESET instruction). A
reset source register allows program determination of the cause of
the most recent reset. 50 I/O pins, each with 4 programmable output configurations. 30 MHz operating frequency at 2.7–5.5 V VDD. Power saving operating modes: Idle and Power-down. Wake-up
from power-down via an external interrupt is supported. 68-pin PLCC and 80-pin PQFP packages.
ORDERING INFORMATION
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
PIN CONFIGURATIONS
68-pin PLCC package
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
80-pin LQFP package
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
LOGIC SYMBOL
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
BLOCK DIAGRAMSU00846
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
PIN DESCRIPTIONS
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
Table 1. Special Function Registers
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
NOTES: SFRs are bit addressable. SFRs are modified from or added to XA-G3 SFRs. At reset, the BCR is loaded with the binary value 00000a11, where “a’ is the value on the BUSW pin. This defaults the address bus size to 24 bits. SFR is loaded from the reset vector. All bits except F1, F0, and P are loaded from the reset vector. Those bits are all 0. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other
purposes in future XA derivatives. The reset value shown for these bits is 0. Port configurations default to quasi-bidirectional when the XA begins execution from internal code memory after reset, based on the
condition found on the EA pin. Thus, all PnCFGA registers will contain FF, and PnCFGB register will contain 00 when the XA begins
execution using internal code memory. When the XA begins execution using external code memory, the default configuration for pins that
are associated with the external bus will be push-pull. The PnCFGA and PnCFGB register contents will reflect this difference. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes. The RSTSRC register reflects the cause of the last XA-S3 reset. One bit will be set to 1, the others will be cleared to 0. The XA guards writes to certain bits (typically interrupt flags) that may be altered directly by a peripheral function. This prevents loss of an
interrupt or other status if a bit was written directly by a peripheral action during the time between the read and write portions of an
instruction that performs a read-modify-write operation. Examples of such instructions are:
and s0con,#$fb
clr tr0
setb ti_0
XA-S3 SFR bits that are guarded in this manner are: ADINT (in ADCON); CF, CCF4, CCF3, CCF2, CCF1, and CCF0 (in CCON); SI (in
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
Figure 1. XA-S3 program memory map
Figure 2. XA-S3 data memory map
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
FUNCTIONAL DESCRIPTIONDetails of XA-S3 functions will be described in the following sections.
Analog to Digital converterThe XA-S3 has an 8-channel, 8-bit A/D converter with 8 sets of result
registers, single scan and multiple scan operating modes. The A/D
also has a 10-bit conversion mode that provides greater result
resolution. The A/D input range is limited to 0 to AVDD (3.3 V max.).
The A/D inputs are on Port 5. Analog Power and Ground as well as
AVREF+ and AVREF– must be supplied in order for the A/D converter to
be used. Prior to enabling the A/D converter or driving analog signals
into the A/D inputs, the port configurations for the pins being used as
A/D inputs must be set to the “off” (high impedance, input only) mode.
A/D timing can be adapted to the application clock frequency in
order to provide the fastest possible conversion.
A/D converter operation is controlled through the ADCON (A/D Control)
register, see Figure 1. Bits in ADCON start and stop the A/D, flag
conversion completion, and select the converter operating modes. When
10-bit resolution is needed, the A/D mode may be set to give 10 result
bits by setting the ADRES bit to 1. In this mode, the A/D takes longer to
complete a conversion, and the timing must be set differently in ADCFG.
A/D Conversion ModesThe A/D converter supports a single scan mode and a continuous
scan mode. In either mode, one or more A/D channels may be
converted. The ADCS register determines which channels are
converted. If the corresponding bit in the ADCS register is set, that
channel is selected for conversions, otherwise that channel is
skipped. The ADCS register is detailed in Figure 2.
For any A/D conversion, the results are stored in ADRSHn,
corresponding to the A/D channel just converted. For a 10-bit
conversion, the two least significant bits are read from the upper end
of register ADRSL. These bits must be read before another
conversion is begun.
A/D conversions are begun by setting the A/D Start and STatus bit in
ADCON. In the single scan mode, all of the channels selected by
bits in the ADCS register will be converted once. The ADINT flag is
set when the last channel is converted. In the continuous scan
mode, the A/D converter continuously converts all A/D channels
selected by bits in the ADCS register. The ADINT flag is set when all
channels have been converted once.
The A/D converter can generate an interrupt when the ADINT flag is
set. This will occur if the A/D interrupt is enabled (via the EAD bit in
IEL), the interrupt system is enabled (via the EA bit in IEL), and the
A/D interrupt priority (specified in IPA3 bits 3 to 0) is higher than the
currently running code (PSW bits IM3 through IM0) and any other
pending interrupt. ADINT must be cleared by software.
A/D Timing ConfigurationThe A/D sampling and conversion timing may be optimized for the
particular oscillator frequency and input drive characteristics of the
application. Because A/D operation is mostly dependent on real-time
effects (charging time of sampling capacitors, settling time of the
comparator, etc.), A/D conversion times are not necessarily much
longer at slower clock frequencies. The A/D timing is controlled by
the ADCFG register, as shown in Figure 3, Table 2 and Table 3.
The primary effect of ADCFG settings is to adjust the A/D sample
and hold time to be relatively constant over various clock
frequencies. Two settings (value 6 and B) are provided to allow fast
conversions with a lower external source driving the A/D inputs.
These settings provide double the sample time at the same
frequency. Of course, settings intended for lower frequencies may
also be used at higher frequencies in order to increase the A/D
sampling time, but this method has the side effect of significantly
increasing A/D conversion times.
Figure 1. A/D Control Register (ADCON)
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
Figure 2. A/D Channel Select Register (ADCS)
Figure 3. A/D Timing Configuration Register (ADCFG)
Table 2. A/D Timing Configuration
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
Table 3. A/D Timing Configuration for 10-bit Mode
A/D InputsIn order to obtain accurate measurements with the A/D Converter,
the source drive must be sufficient to adequately charge the
sampling capacitor during the sampling time. Figure 4 shows the
equivalent resistance and capacitance related to the A/D inputs.
A/D timing configurations indicated in Table 1 allow for full A/D
accuracy (according to the A/D specifications) assuming a source
resistance of less than or equal to 20kΩ. Larger source resistances
may be accommodated by increasing the sampling time with a
different A/D timing configuration.
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
A/D AccuracyThe XA-S3 A/D in 10 -bit mode is specified with 16 samples
averaged in order to factor out on-chip noise. In an application
where averaging 16 samples is not practical, the accuracy
specifications may be de-rated according to the number of samples
that are actually taken. The graph in Figure 5 shows the relationship
of additional A/D error to the number of samples that are averaged.
For example, if a single A/D reading is used with no averaging, the
A/D accuracy should be de-rated by ±1.25 LSB.
Figure 5. A/D accuracy by number of averaging samples
(Pertains to 10-bit mode only. Note that 10-bit mode is only specified up to fC = 20 MHz.)
Figure 6. I2 C Control Register (I2CON)
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
2 C InterfaceThe I2 C interface on the XA-S3 is identical to the standard byte-style2 C interface found on devices such as the 8xC552 except for the
rate selection. The I2C interface conforms to the 100 kHz I2C
specification, but may be used at rates up to 400 kHz
(non-conforming).
Important: Before the I2 C interface may be used, the port pins
P5.6 and 5.7, which correspond to the I2C functions SCL and SDA
respectively, must be set to the open drain mode.
The processor interfaces to the I2C logic via the following four
special function registers: I2CON (I2C control register), I2STA (I2C
status register), I2DAT (I2 C data register), and I2ADR (I2 C slave
address register). The I2C control logic interfaces to the external I2C
bus via two port 5 pins: P5.6/SCL (serial clock line) and P5.7/SDA
(serial data line).
The Control Register, I2CONThis register is shown in Figure 6. Two bits are affected by the I2C
hardware: the SI bit is set when a serial interrupt is requested, and
the STO bit is cleared when a STOP condition is present on the I2C
bus. The STO bit is also cleared when ENA = “0”.
ENA, the I2C Enable Bit
ENA = 0: When ENA is “0”, the SDA and SCL outputs are not
driven. SDA and SCL input signals are ignored, SIO1 is in the “not
addressed” slave state, and the STO bit in I2CON is forced to “0”.
No other bits are affected. P5.6 and P5.7 may be used as open
drain I/O ports.
ENA = 1: When ENA is “1”, SIO1 is enabled. The P5.6 and P5.7
port latches must be set to logic 1.
ENA should not be used to temporarily release the I2C-bus since,
when ENA is reset, the I2C-bus status is lost. The AA flag should be
used instead (see description of the AA flag in the following text).
In the following text, it is assumed the ENA = “1”.
STA, the START flag
STA = 1: When the STA bit is set to enter a master mode, the I2C
hardware checks the status of the I2 C bus and generates a START
condition if the bus is free. If the bus is not free, the I2 C interface
waits for a STOP condition (which will free the bus) and generates a
START condition after a delay of a half clock period of the internal
serial clock generator.
If STA is set while the I2C interface is already in a master mode and
one or more bytes are transmitted or received, the hardware
transmits a repeated START condition. STA may be set at any time.
STA may also be set when the I2 C interface is an addressed slave.
STA = 0: When the STA bit is reset, no START condition or
repeated START condition will be generated.
STO, the STOP flag
STO = 1: When the STO bit is set while the I2C interface is in a
master mode, a STOP condition is transmitted to the I2C bus. When
the STOP condition is detected on the bus, the hardware clears the
STO flag. In a slave mode, the STO flag may be set to recover from
an error condition. In this case, no STOP condition is transmitted to
the I2 C bus. However, the hardware behaves as if a STOP condition
has been received and switches to the defined “not addressed” slave
receiver mode. The STO flag is automatically cleared by hardware.
If the STA and STO bits are both set, then a STOP condition is
transmitted to the I2 C bus if the interface is in a master mode (in a
slave mode, the hardware generates an internal STOP condition
which is not transmitted). The I2 C interface then transmits a START
condition.
STO = 0: When the STO bit is reset, no STOP condition will be
generated.
SI, the Serial Interrupt flag
SI = 1: When the SI flag is set, and the EA (interrupt system
enable) and EI2 (I 2C interrupt enable) bits are also set, an I2C
interrupt is requested. SI is set by hardware when one of 25 of the
26 possible I2C interface states is entered. The only state that does
not cause SI to be set is state F8H, which indicates that no relevant
state information is available.
While SI is set, the low period of the serial clock on the SCL line is
stretched, and the serial transfer is suspended. A high level on the
SCL line is unaffected by the serial interrupt flag. SI must be reset
by software.
SI = 0: When the SI flag is reset, no serial interrupt is requested,
and there is no stretching of the serial clock on the SCL line.
AA, the Assert Acknowledge flag
AA = 1: If the AA flag is set, an acknowledge (low level to SDA) will
be returned during the acknowledge clock pulse on the SCL line when: The “own slave address” has been received. The general call address has been received while the general call
bit (GC) in I2ADR is set. A data byte has been received while the I2C interface is in the
master receiver mode. A data byte has been received while the I2C interface is in the
addressed slave receiver mode.
AA = 0: If the AA flag is reset, a not acknowledge (high level to
SDA) will be returned during the acknowledge clock pulse on the
SCL line when:• A data byte has been received while the I2C interface is in the
master receiver mode. A data byte has been received while the I2 C interface is in the
addressed slave receiver mode.
When the I2C interface is in the addressed slave transmitter mode,
state C8H will be entered after the last serial data byte is
transmitted. When SI is cleared, the I2C interface leaves state C8H,
enters the not addressed slave receiver mode, and the SDA line
remains at a high level. In state C8H, the AA flag can be set again
for future address recognition.
When the I2C interface is in the not addressed slave mode, its own
slave address and the general call address are ignored. Consequently,
no acknowledge is returned, and a serial interrupt is not requested.
Thus, the hardware can be temporarily released from the I2C bus
while the bus status is monitored. While the hardware is released from
the bus, START and STOP conditions are detected, and serial data is
shifted in. Address recognition can be resumed at any time by setting
the AA flag. If the AA flag is set when the part’s own slave address or
the general call address has been partly received, the address will be
recognized at the end of the byte transmission.
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
CR0, CR1, and CR2, the Clock Rate BitsThese three bits determine the serial clock frequency when the I2C
interface is in a master mode. An I2 C rate of 100kHz or lower is
typical and can be derived from many oscillator frequencies. The
various serial rates are shown in Table 4. A variable bit rate may
also be used if Timer 1 is not required for any other purpose while
the I2C hardware is in a master mode. The frequencies shown in
Table 4 are unimportant when the I2C hardware is in a slave mode.
In the slave modes, the hardware will automatically synchronize with
the incoming clock frequency.
The I2 C Status Register, I2STAI2STA is an 8-bit read-only special function register. The three least
significant bits are always zero. The five most significant bits contain
the status code. There are 26 possible status codes. When I2STA
contains F8H, no relevant state information is available and no serial
interrupt is requested. All other I2STA values correspond to defined
hardware interface states. When each of these states is entered, a
serial interrupt is requested (SI = “1”).
NOTE: A detailed I2 C interface description and usage
information, including example driver code, will be provided in
a separate document.
Table 4. I2 C Rate Control
NOTES: The XA-S3 I2C interface does not conform to the 400kHz I2C specification (which applies to rates greater than 100kHz) in all details, but
may be used with care where higher rates are required by the application. The timer 1 overflow is used to clock the I2C interface. The resulting bit rate is 1/2 of the timer overflow rate.
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
XA-S3 Timer/CountersThe XA-S3 has three general purpose counter/timers, two of which may
also be used as baud rate generators for either or both of the UARTs.
Timer 0 and 1These are identical to the standard XA-G3 timer 0 and 1.
Timer 2This is identical to the standard XA-G3 timer 2.
Programmable Counter Array (PCA)The Programmable Counter Array available on the XA-S3 is a
special 16-bit Timer that has five 16-bit capture/compare modules
associated with it. Each of the modules can be programmed to
operate in one of four modes: rising and/or falling edge capture,
software timer, high-speed output, or pulse width modulator. Each
module has a pin associated with it in port 1. Module 0 is connected
to P4.1(CEX0), module 1 to P4.2(CEX1), etc. The basic PCA
configuration is shown in Figure 7.
The PCA timer is a common time base for all five modules and can
be programmed to run at: the TCLK rate (Osc/4, Osc/16, or Osc/64),
the Timer 0 overflow, or the input on the ECI pin (P4.0). When the
ECI input is used, the falling edge clocks the PCA counter. The timer
count source is determined from the CPS1 and CPS0 bits in the
CMOD SFR as follows (see Figure 10):
CPS1 CPS0 PCA Timer Count Source X TCLK (Osc/4, Osc/16, or Osc/64) 0 Timer 0 overflow 1 ECI (PCA External Clock Input (max rate = Osc/4)
In the CMOD SFR are three additional bits associated with the PCA.
They are CIDL which allows the PCA to stop during idle mode,
WDTE which enables or disables the watchdog function on
module 4, and ECF which when set causes an interrupt and the
PCA overflow flag CF (in the CCON SFR) to be set when the PCA
timer overflows. These functions are shown in Figure 8. In addition,
each PCA module may generate a separate interrupt.
The watchdog timer function is implemented in module 4 (see
Figure 17).
The CCON SFR contains the run control bit for the PCA and the
flags for the PCA timer (CF) and each module (refer to Figure 11).
To run the PCA the CR bit (CCON.6) must be set by software. The
PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when
the PCA counter overflows and an interrupt will be generated if the
ECF bit in the CMOD register is set, The CF bit can only be cleared
by software. Bits 0 through 4 of the CCON register are the flags for
the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set
by hardware when either a match or a capture occurs. These flags
also can only be cleared by software. The PCA interrupt system
shown in Figure 9.
Each module in the PCA has a special function register associated
with it. These registers are: CCAPM0 for module 0, CCAPM1 for
module 1, etc. (see Figure 12). The registers contain the bits that
control the mode that each module will operate in. The ECCF bit
(CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module)
enables the CCF flag in the CCON SFR to generate an interrupt
when a match or compare occurs in the associated module. PWM
(CCAPMn.1) enables the pulse width modulation mode. The TOG
bit (CCAPMn.2) when set causes the CEX output associated with
the module to toggle when there is a match between the PCA
counter and the module’s capture/compare register. The match bit
MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter
and the module’s capture/compare register.
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5)
determine the edge that a capture input will be active on. The CAPN
bit enables the negative edge, and the CAPP bit enables the
positive edge. If both bits are set both edges will be enabled and a
capture will occur for either transition. The last bit in the register
ECOM (CCAPMn.6) when set enables the comparator function.
Figure 13 shows the CCAPMn settings for the various PCA
functions.
There are two additional registers associated with each of the PCA
modules. They are CCAPnH and CCAPnL and these are the
registers that store the 16-bit count when a capture occurs or a
compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output.
Figure 7. Programmable Counter Array (PCA)
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
Figure 8. PCA Timer/Counter
Figure 9. PCA Interrupt System
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
Figure 10. CMOD: PCA Counter Mode Register
Figure 11. CCON: PCA Counter Control Register
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
Figure 12. CCAPMn: PCA Modules Compare/Capture Registers
Figure 13. PCA Module Modes (CCAPMn Register)
PCA Capture ModeTo use one of the PCA modules in the capture mode either one or
both of the CCAPM bits CAPN and CAPP for that module must be
set. The external CEX input for the module (on port 1) is sampled for
a transition. When a valid transition occurs the PCA hardware loads
the value of the PCA counter registers (CH and CL) into the
module’s capture registers (CCAPnL and CCAPnH). If the CCFn bit
for the module in the CCON SFR and the ECCFn bit in the CCAPMn
SFR are set then an interrupt will be generated. Refer to Figure 14.
16-bit Software Timer ModeThe PCA modules can be used as software timers by setting both
the ECOM and MAT bits in the modules CCAPMn register. The PCA
timer will be compared to the module’s capture registers and when a
match occurs an interrupt will occur if the CCFn (CCON SFR) and
the ECCFn (CCAPMn SFR) bits for the module are both set (see
Figure 15).
counter and the module’s capture registers. To activate this mode
the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must
be set (see Figure 16).
Pulse Width Modulator ModeAll of the PCA modules can be used as PWM outputs. Figure 17
shows the PWM function. The frequency of the output depends on
the source for the PCA timer. All of the modules will have the same
frequency of output because they all share the PCA timer. The duty
cycle of each module is independently variable using the module’s
capture register CCAPLn. When the value of the PCA CL SFR is
less than the value in the module’s CCAPLn SFR the output will be
low, when it is equal to or greater than the output will be high. When
CL overflows from FF to 00, CCAPLn is reloaded with the value in
CCAPHn. the allows updating the PWM without glitches. The PWM
and ECOM bits in the module’s CCAPMn register must be set to
enable the PWM mode.
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
Figure 14. PCA Capture Mode
Figure 15. PCA Compare Mode
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
Figure 16. PCA High Speed Output Mode
Figure 17. PCA PWM Mode
Philips Semiconductors Preliminary specification
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), 2 C, 2 UARTs, 16 MB address range
Figure 18. PCA Watchdog Timer m(Module 4 only)
PCA Watchdog TimerAn on-board watchdog timer is available with the PCA to improve
the reliability of the system without increasing chip count. Watchdog
timers are useful for systems that are susceptible to noise, power
glitches, or electrostatic discharge. Module 4 is the only PCA
module that can be programmed as a watchdog. However, this
module can still be used for other modes if the watchdog is not
needed.
Figure 18 shows a diagram of how the watchdog works. The user
pre-loads a 16-bit value in the compare registers. Just like the other
compare modes, this 16-bit value is compared to the PCA timer
value. If a match is allowed to occur, an internal reset will be
generated. This will not cause the RST pin to be driven low.
In order to hold off the reset, the user has three options: periodically change the compare value so it will never match the
PCA timer, periodically change the PCA timer value so it will never match
the compare values, or disable the watchdog by clearing the WDTE bit before a match
occurs and then re-enable it.
The first two options are more reliable because the watchdog timer
is never disabled as in option #3. If the program counter ever goes
astray, a match will eventually occur and cause an internal reset.
The second option is also not recommended if other PCA modules
are being used. Remember, the PCA timer is the time base for all
modules; changing the time base for other modules would not be a
good idea. Thus, in most applications the first solution is the best
option.
Figure 19 shows the code for initializing the watchdog timer. Module
4 can be configured in either compare mode, and the WDTE bit in
CMOD must also be set. The user’s software then must periodically
change (CCAP4H,CCAP4L) to keep a match from occurring with the
PCA timer (CH,CL). This code is given in the WATCHDOG routine in
Figure 19.
This routine should not be part of an interrupt service routine,
because if the program counter goes astray and gets stuck in an
infinite loop, interrupts will still be serviced and the watchdog will
keep getting reset. Thus, the purpose of the watchdog would be
defeated. Instead, call this subroutine from the main program within16 count of the PCA timer.
