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PXAH30KFBE
CMOS 16-bit highly integrated microcontroller
Preliminary specification
IC28 Data Handbook
1999 Sep 24
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
DESCRIPTIONThe powerful 16-bit XA CPU core and rich feature set make the
XA-H3 and XA-H4 devices ideal for high-performance real-time
applications such as industrial control and networking. By supporting
of up to 32 MB of external memory, these devices provide a low-cost
solution to embedded applications of any complexity. Features like
DMA, memory controller and four advanced UARTs help solve I/O
intensive tasks with a minimum of CPU load.
The XA-H3 feature set is a subset of the XA-H4 (see Table 1). The
XA-H3/H4 devices are members of the Philips XA (eXtended
Architecture) family of high performance 16-bit microcontrollers.
The XA-H3 and XA-H4 are designed to significantly minimize the
need for external components.
FEATURES Large Memory Support (up to 6 MB external) De-multiplexed Address/Data Bus Six Programmable Chip Selects
Support for Unified Memory – allows easy user modification of
all code
External ISP Flash support for easy code download Dynamic Bus Sizing – each of 6 Chip Selects can be programmed
for 8-bit or 16-bit bus. Dynamic Bus Timing – each of 6 chip selects has individual
programmable bus timing. 32 Programmable General Purpose I/O Pins Four UARTs with 230.4 kbps capability Eight DMA Channels
Table 1. XA-H3 and XA-H4 features comparison
NOTE: Can be used as additional counters if not needed as BRGs.
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
ORDERING INFORMATION
NOTEK=30 MHz, F = (–40 to +85), BE = LQFP
PIN CONFIGURATION
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
LOGIC SYMBOL XA-H3
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
XA-H3 BLOCK DIAGRAM
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
XA-H3 MEMORY MAPS
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
PIN DESCRIPTIONS
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
NOTES: See XA-H3 User Guide, “Pins Chapter,” for how to program selection of pin functions. RTClk input is usually used for Rx Clock if an external clock is needed, but can be used for either Rx or Tx or both. TRClk is usually used for
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
CONTROL REGISTER OVERVIEWThere are two types of control registers in the XA-H3, these are SFRs
(Special Function Registers), and MMRs (Memory Mapped Registers.)
The SFR registers, with the exception of MRBL, MRBH, MICFG, BCR,
BRTH, BRTL, and RSTSRC are the standard XA core registers. See
WARNINGs about BCR, BRTH, and BRTL in Table 2.SFRs are accessed by “direct addressing” only (see IC25 XA User
Manual for direct addressing.) The MMRs are specific to the XA-H3
on-chip peripherals, and can be accessed by any addressing mode
that can be used for off-chip data accesses. The MMRs are
implemented in a relocatable block. See the “Memory Controller”
chapter in the XA-H3 User Manual for details on how to relocate the
MMRs by writing a new base address into the MRBL and MRBH
(MMR Base Low and High) registers.
Table 2. Special Function Registers (SFR)
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
NOTES: SFRs marked with an asterisk (*) are bit addressable. SFRs marked with a pound sign (#) are additional SFR registers specific to the XA-H3 and XA-H4. The XA-H3 implements an 8-bit SFR bus, as stated in Chapter 8 of the IC25 Data Handbook XA User Guide. All SFR accesses must be
8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. 16-bit SFR reads will return undefined data in the
upper byte. SFR is loaded from the reset vector. F1, F0, and P reset to “0”. All other bits are loaded from the reset vector. Unimplemented bits in SFRs are “X” (unknown) at all times. “1”s should not be written to these bits since they may be used for other
purposes in future XA derivatives. The reset value shown for these bits is “0”. Port configurations default to quasi-bidirectional when the XA begins execution after reset. Thus all PnCFGA registers will contain FFh and
PnCFGB register will contain 00h. See warning in XA-H3 User Manual about P3.2_Timer0_ResetOut pin during first 258 clocks after power
up. Basically, during this period, this pin may output a strongly-driven low pulse. If the pulse does occur, it will terminate in a transition to high
at a time no later than the 259th system clock after valid VCC power up. The WDCON reset value is E6 for a Watchdog reset; E4 for all other reset causes. The RSTSRC register reflects the cause of the last XA reset. One bit will be set to “1”, the others will be “0”. RSTSRC[7] enables the ResetOut
function; “1” = Enabled, “0” = Disabled. See XA-H3 User Manual for details; RSTSRC[7] differs in function from most other XA derivatives. The XA guards writes to certain bits (typically interrupt flags) that may be written by a peripheral function. This prevents loss of an interrupt or
other status if a bit was written directly by a peripheral action between the read and write of an instruction that performs a read-modify-write
operation. XA-H3 SFR bits that are guarded in this manner are: TF1, TF0, IE1, and IE0 (in TCON), and WDTOF (in WDCON).
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
Table 3. Memory Mapped Registers (MMR)
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
FUNCTIONAL DESCRIPTIONThe XA-H3 functions are described in the following sections.
Because all blocks are thoroughly documented in either the IC25 XA
Data Handbook, or the XA-H3 User Manual, only brief descriptions
are given in this datasheet, in conjunction with references to the
appropriate document.
XA CPUThe CPU is a 30 MHz implementation of the standard XA CPU core.
See the XA Data Handbook (IC25) for details. The CPU core is
identical to the G3 core. See caveat in next paragraph about the Bus
Interface Unit.
Bus Interface Unit (BIU)This is the internal Bus, not the bus at the pins. This internal bus
connects the CPU to Memory Controller.
WARNING: Immediately after reset, always write BTRH = 51h,followed by BTRL = 40h, in that order. Once written, do not change
the values in these registers. Follow these two writes with five
NOPS. Never write to the BCR register, it comes out of reset
initialized to 07h, which is the only value that will work.
Figure 1. XA CPU Core BIU (Bus Interface Unit)
Philips Semiconductors Preliminary specification
XA-H3CMOS 16-bit highly integrated microcontroller
Timers 0 and 1Timers 0 and 1 are the standard XA-G3 timer 0 and 1. Each has an
associated I/O pin and interrupt. See the XA-G3 data sheet in the
IC25 XA Data Handbook for details. Many XA derivatives include a
standard XA Timer 2. The Timer 2 block has been removed in order
to provide other functions on the XA-H3.
Watchdog TimerThis timer is a standard XA-G3 Watchdog Timer. See the G3
datasheet in IC25. Also, if you intend to use the Watchdog Timer to
assert the ResetOut pin, see “ResetOut” in the XA-H3 User Manual.
The Watchdog Timer is enabled at reset, and must be periodically
fed to prevent timeout. If the watchdog times out, it will generate an
internal reset; and if ResetOut is enabled the internal reset will
generate a ResetOut pulse (active low pulse on ResetOut pin.)
ResetOn the XA-H3 there are two pins associated with reset. The ResetIn
pin provides an external reset into the XA-H3. The port pin
P3.2_Timer0_ResetOut output can be configured as ResetOut.
Because ResetOut does not reflect ResetIn, the ResetOut pin can
be tied directly back into the ResetIn pin without other PC board
logic. This configuration will make all resets (internal or external)
appear to the XA as external resets. See the XA-H3 User Manual for
a full discussion of the reset functions.
ResetInThe ResetIn function is the standard XA-G3 ResetIn function. The
ResetIn signal does NOT get passed on to ResetOut. See the
XA-H3 User Manual for details on reset.
ResetOutThe P3.2_Timer0_ResetOut pin provides an external indication (if the
ResetOut function is enabled in the RSRSRC register) via an active
low output when an internal reset occurs (internal reset is Reset
instruction or Watchdog time out.) If the ResetOut function is enabled,
the ResetOut pin will be driven low when a Watchdog reset occurs or
the Reset instruction is executed. This signal may be used to inform
other devices in the system that the XA-H3 has been internally reset.
The ResetIn signal does NOT get passed on to ResetOut. When
activated, the duration of the ResetOut pulse is 256 system clocks.
WARNING: At power on time, from the time that power coming up isvalid, the P3.2_Timer0_ResetOut pin may be driven low for any
period from zero nanoseconds up to 258 system clocks. This is true
independently of whether ResetIn is active or not.
Reset Source RegisterThe reset source identification register (RSTSRC) indicates the cause
of the most recent XA reset. The cause may have been an externally
applied reset signal, execution of the RESET instruction, or a
Watchdog reset. Figure 2 shows the fields in the RSTSRC register. If
the ResetOut function is tied back into the ResetIn pin, then all resets
will be external resets, and will thus appear as external resets in the
reset source register. RSTSRC[7] enables the ResetOut function; 1 =
Enabled, 0 = Disabled. See XA-H3 User Manual for details;
RSTSRC[7] differs in function from most other XA derivatives.
Figure 2. RSTSRC Reset Source Register
MEMORY CONTROLLER AND I/O BUS INTERFACEThe Memory Controller and bus interface generate bus cycles that are
interface with no external decode logic or interface chips. The bus
