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PX1011B-EL1
PCI Express stand-alone X1 PHY
1. General descriptionThe PX1011B is a high-performance, low-power, single-lane PCI Express electrical
PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The
PX1011B PCI Express PHY is compliant to the PCI Express Base Specification,
Rev. 1.0a, and Rev. 1.1. The PX1011B includes features such as Clock and Data
Recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers,
elastic buffer and receiver detection, and provides superior performance to the Media
Access Control (MAC) layer devices.
The PX1011B is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface. Its
PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE)
specification, enhanced and adapted for off-chip applications with the introduction of a
source synchronous clock for transmit and receive data. The 8-bit data interface operates
at 250 MHz with SSTL_2 signaling. The SSTL_2 signaling is compatible with the I/O
interfaces available in FPGA products.
The PX1011B PCI Express PHY supports advanced power management functions.
The PX1011BI is for the industrial temperature range (40 C to +85 C).
Automotive AEC-Q100 compliant version PX1011B-EL1/Q900 is available.
2. Features and benefits
2.1 PCI Express interface Compliant to PCI Express Base Specification 1.1 Single PCI Express 2.5 Gbit/s lane Data and clock recovery from serial stream Serializer and De-serializer (SerDes) Receiver detection 8b/10b coding and decoding, elastic buffer and word alignment Supports loopback Supports direct disparity control for use in transmitting compliance pattern Supports lane polarity inversion Low jitter and Bit Error Rate (BER)
2.2 PHY/MAC interface Based on Intel PHY Interface for PCI Express architecture v1.0 (PIPE) Adapted for off-chip with additional synchronous clock signals (PXPIPE) 8-bit parallel data interface for transmit and receive at 250 MHz 2.5 V SSTL_2 class I signaling
PX101 1B
PCI Express stand-alone X1 PHY
Rev. 6 — 27 June 2011 Product data sheet
NXP Semiconductors PX1011B
PCI Express stand-alone X1 PHY
2.3 JTAG interface JTAG (IEEE 1149.1) boundary scan interface Built-In Self Test (BIST) controller tests SerDes and I/O blocks at speed 3.3 V CMOS signaling
2.4 Power management Dissipates < 300 mW in L0 normal mode Support power management of L0, L0s and L1
2.5 Clock 100 MHz external reference clock with 300 ppm tolerance Supports spread spectrum clock to reduce EMI On-chip reference clock termination
2.6 Miscellaneous LFBGA81 leaded or lead-free packages Operating ambient temperature Commercial: 0 C to +70C Industrial: 40 C to +85C ESD protection voltage for Human Body Model (HBM): 2000V
3. Quick reference data Table 1. Quick reference dataVDDD1 digital supply voltage 1 for JTAGI/O 3.0 3.3 3.6 V
VDDD2 digital supply voltage 2 for SSTL_2 I/O 2.3 2.5 2.7 V
VDDD3 digital supply voltage 3 for core 1.15 1.2 1.3 V
VDD supply voltage for high-speed
serial I/O and PVT
1.15 1.2 1.3 V
VDDA1 analog supply voltage 1 for serializer 1.15 1.2 1.3 V
VDDA2 analog supply voltage 2 for serializer 3.0 3.3 3.6 V
fclk(ref) reference clock frequency 99.97 100 100.03 MHz
Tamb ambient temperature operating
commercial 0 - +70 C
industrial 40 - +85 C
NXP Semiconductors PX1011B
PCI Express stand-alone X1 PHY
4. Ordering information[1] PX1011B-EL1/Q900 is AEC-Q100 compliant. Contact i2c.support for PPAP.
5. Marking[1] Industrial temperature range.
Table 2. Ordering informationPX1011B-EL1/G Pb-free (SnAgCu
solder ball compound)
LFBGA81 plastic low profile fine-pitch ball grid array
package; 81 balls; body 9 9 1.05 mm
SOT643-1
PX1011B-EL1/N SnPb solder ball
compound
LFBGA81 plastic low profile fine-pitch ball grid array
package; 81 balls; body 9 9 1.05 mm
SOT643-1
PX1011BI-EL1/G Pb-free (SnAgCu
solder ball compound)
LFBGA81 plastic low profile fine-pitch ball grid array
package; 81 balls; body 9 9 1.05 mm
SOT643-1
PX1011B-EL1/Q900[1] Pb-free (SnAgCu
solder ball compound)
LFBGA81 plastic low profile fine-pitch ball grid array
package; 81 balls; body 9 9 1.05 mm
SOT643-1
Table 3. Leaded package marking PX1011B-EL1/N full basic type number xxxxxxx diffusion lot number 2PNyyww manufacturing code:
2 = diffusion site
P = assembly site
N = leaded
yy = year code
ww = week code
Table 4. Lead-free package marking PX1011B-EL1/G
PX1011BI-EL1/G[1]
PX1011B-EL1/Q[1]
full basic type number xxxxxxx diffusion lot number 2PGyyww manufacturing code:
2 = diffusion site
P = assembly site
G = lead-free
yy = year code
ww = week code
NXP Semiconductors PX1011B
PCI Express stand-alone X1 PHY
6. Block diagramNXP Semiconductors PX1011B
PCI Express stand-alone X1 PHY
7. Pinning information
7.1 PinningNXP Semiconductors PX1011B
PCI Express stand-alone X1 PHY
7.2 Pin descriptionThe PHY input and output pins are described in Table 5 to Table 12. Note that input and
output is defined from the perspective of the PHY. Thus a signal on a pin described as an
output is driven by the PHY and a signal on a pin described as an input is received by the
PHY. A basic description of each pin is provided.
Table 5. PCI Express serial data linesRX_P E1 input PCIe I/O differential input receive pair with 50
on-chip terminationRX_N F1 input PCIe I/O
TX_P H1 output PCIe I/O differential output transmit pair with on-chip terminationTX_N J1 output PCIe I/O
Table 6. PXPIPE interface transmit data signalsTXDATA[7:0] J9, H9, G8, G9,
F8, F9, E9, D9
input SSTL_2 8-bit transmit data input from the MAC
to the PHY
TXDATAK J7 input SSTL_2 selection input for the symbols of
transmit data; LOW= data byte;
HIGH= control byte
Table 7. PXPIPE interface receive data signalsRXDATA[7:0] B3, A3, B4, A4,
A5, B6, A6, B7
output SSTL_2 8-bit receive data output from the PHY
to the MAC
RXDATAK A7 output SSTL_2 selection output for the symbols of
receive data; LOW= data byte;
HIGH= control byte
Table 8. PXPIPE interface command signalsRXDET_ LOOPB H7 input SSTL_2 used to tell the PHY to begin a receiver
detection operation or to begin loopback;
LOW= reset state
TXIDLE H4 input SSTL_2 forces TX output to electrical idle. TXIDLE
should be asserted while in power states P0s
and P1.
TXCOMP J5 input SSTL_2 used when transmitting the compliance
pattern; HIGH-level sets the running disparity
to negative
RXPOL J4 input SSTL_2 signals the PHY to perform a polarity inversion
on the receive data; LOW= PHY does no
polarity inversion; HIGH= PHY does polarity
inversion
RESET_N J3 input SSTL_2 PHY reset input; active LOW
PWRDWN0 H6 input SSTL_2 transceiver power-up and power-down inputs
(see Table 13); 0x2= reset statePWRDWN1 J6 input SSTL_2
NXP Semiconductors PX1011B
PCI Express stand-alone X1 PHY
Table 9. PXPIPE interface status signalsRXVALID C8 output SSTL_2 indicates symbol lock and valid data on
RX_DATA and RX_DATAK
PHYSTATUS D8 output SSTL_2 used to communicate completion of several PHY
functions including power management state
transitions and receiver detection
RXIDLE A2 output SSTL_2 indicates receiver detection of an electrical idle;
this is an asynchronous signal
RXSTATUS0 A9 output SSTL_2 encodes receiver status and error codes for the
received data stream and receiver detection (see
Table 15)RXSTATUS1 B9 output SSTL_2
RXSTATUS2 C9 output SSTL_2
Table 10. Clock and reference signalsTXCLK J8 input SSTL_2 source synchronous 250 MHz transmit clock
input from MAC. All input data and signals to the
PHY are synchronized to this clock.
RXCLK A8 output SSTL_2 source synchronous 250 MHz clock output for
received data and status signals bound for the
MAC.
REFCLK_P B1 input PCIe I/O 100 MHz reference clock input. This is the
spread spectrum source clock for PCI Express.
Differential pair input with 50 on-chip
termination.
REFCLK_N C1 input PCIe I/O
PVT D6 - analog I/O input or output to create a compensation signal
internally that will adjust the I/O pads
characteristics as PVT drifts. Connect to VDD
through a 49.9 resistor.
VREFS J2 input reference voltage input for SSTL_2 classI
signaling. Connect to 1.25V.
Table 11. 3.3 V JTAG signalsTMS E4 input 3.3 V CMOS test mode select input
TRST_N F4 input 3.3 V CMOS test reset input for the JTAG interface;
active LOW
TCK F3 input 3.3 V CMOS test clock input for the JTAG interface
TDI G3 input 3.3 V CMOS test data input
TDO H3 output 3.3 V CMOS test data output
NXP Semiconductors PX1011B
PCI Express stand-alone X1 PHY
8. Functional descriptionThe main function of the PHY is to convert digital data into electrical signals and vice
versa. The PCI Express PHY handles the low level PCI Express protocol and signaling.
The PX1011B PCI Express PHY consists of the Physical Coding Sub-layer (PCS), a
Serializer and De-serializer (SerDes) and a set of I/Os (pads). The PCI Express PHY
handles the low level PCI Express protocol and signaling. This includes features such as
Clock and Data Recovery (CDR), data serialization and de-serialization, 8b/10b encoding,
analog buffers, elastic buffer and receiver detection.
The PXPIPE interface between the MAC and PX1011B is a superset of the PHY Interface
for the PCI Express (PIPE) specification. The following feature have been added:
Source synchronous clocks for RX and TX data to simplify timing closure.
The 8-bit data width PXPIPE interface operates at 250 MHz with SSTL_2 classI
signaling. PX1011B does not integrate SSTL_2 termination resistors inside the IC.
The PCI Express link consists of a differential input pair and a differential output pair. The
data rate of these signals is 2.5 Gbit/s.
8.1 Receiving dataIncoming data enters the chip at the RX interface. The receiver converts these signals
from small amplitude differential signals into rail-to-rail digital signals. The carrier detect
circuit detects whether data is present on the line and passes this information through to
the SerDes and PCS.
If a valid stream of data is present the Clock and Data Recovery unit (CDR) first recovers
the clock from the data and then uses this clock for re-timing the data (i.e., recovering the
data).
Table 12. PCI Express PHY power suppliesVDDA1 D5 power 1.2 V analog power supply for serializer and
de-serializer
VDDA2 D4 power 3.3 V analog power supply for serializer and
de-serializer
VDDD1 E3, E5 power 3.3 V power supply for JTAG I/O
VDDD2 C3, C5, C7, E7,
G5, G7
power 2.5 V power supply for SSTL_2 I/O
VDDD3 E6, F5, F6 power 1.2 V power supply for core
VDD D3 power 1.2 V power supply for high-speed serial
PCI Express I/O pads and PVT
VSS A1, B2, B5, B8,
C2, C4, C6, D1,
D2, D7, E2, E8,
F2, F7, G1, G2,
G4, G6, H2, H5,
ground ground
NXP Semiconductors PX1011B
PCI Express stand-alone X1 PHYThe de-serializer or Serial-to-Parallel converter (S2P) de-serializes this data into 10-bits
parallel data.
Since the S2P has no knowledge about the data, the word alignment is still random. This
is fixed in the digital domain by the PCS block. It first detects a 10-bit comma character
(K28.5) from the random data stream and aligns the bits. Then it converts the 10-bit raw
data into 8-bit words using 8b/10b decoding. An elastic buffer and FIFO brings the
resulting data to the right clock domain, which is the RX source synchronous clock
domain.
8.2 Transmitting dataWhen the PHY transmits, it receives 8-bit data from the MAC. This data is encoded using
an 8b/10b encoding algorithm. The 2 bits overhead of the 8b/10b encoding ensures the
serial data will be DC-balanced and has a sufficient 0-to-1 and 1-to-0 transition density for
clock recovery at the receiver side.
The serializer or Parallel-to-Serial converter (P2S) serializes the 10 bits data into serial
data streams. These data streams are latched into the transmitter, where they are
converted into small amplitude differential signals. The transmitter has built-in
de-emphasis for a larger eye opening at the receiver side.
The PLL has a sufficiently high bandwidth to handle a 100 MHz reference clock with a kHz to 33 kHz spread spectrum.
8.3 ClockingThere are three clock signals used by the PX1011B:
REFCLK is a 100 MHz external reference clock that the PHY uses to generate the
250 MHz data clock and the internal bit rate clock. This clock may have kHzto33 kHz spread spectrum modulation.
TXCLK is a reference clock that the PHY uses to clock the TXDATA and command.
This source synchronous clock is provided by the MAC. The PHY expects that the
rising edge of TXCLK is centered to the data. The TXCLK has to be synchronous with
RXCLK.
RXCLK is a source synchronous clock provided by the PHY. The RXDATA and status
signals are synchronous to this clock. The PHY aligns the rising edge of RXCLK to the
center of the data. RXCLK may be used by the MAC to clock its internal logic.
8.4 ResetThe PHY must be held in reset until power and REFCLK are stable. It takes the PHY s maximum to stabilize its internal clocks. RXCLK frequency is the same as REFCLK
frequency, 100 MHz, during this time. The PHY de-asserts PHYSTATUS when internal
clocks are stable.
The PIPE specification recommends that while RESET_N is asserted, the MAC should
have RXDET_LOOPB de-asserted, TXIDLE asserted, TXCOMP de-asserted, RXPOL
de-asserted and power state P1. The MAC can also assert a reset if it receives a physical
layer reset packet.
NXP Semiconductors PX1011B
PCI Express stand-alone X1 PHY
8.5 Power managementThe power management signals allow the PHY to manage power consumption. The PHY
meets all timing constraints provided in the PCI Express base specification regarding
clock recovery and link training for the various power states.
Four power states are defined: P0, P0s, P1 and P2. P0 state is the normal operational
state for the PHY . When directed from P0 to a lower power state, the PHY can
immediately take whatever power saving measures are appropriate.
In states P0, P0s and P1, the PHY keeps internal clocks operational. For all state
transitions between these three states, the PHY indicates successful transition into the
designated power state by a single cycle assertion of PHYSTATUS. For all power state
transitions, the MAC must not begin any operational sequences or further power state
transitions until the PHY has indicated that the initial state transition is completed. TXIDLE
should be asserted while in power states P0s and P1.
P0 state: All internal clocks in the PHY are operational. P0 is the only state where the PHY transmits and receives PCI Express signaling. P0 is the appropriate PHY power
management state for most states in the Link Training and Status State Machine
(LTSSM). Exceptions are listed for each lower power PHY state (P0s, P1 and P2).
P0s state: The MAC will move the PHY to this state only when the transmit channel is idle.
While the PHY is in either P0 or P0s power states, if the receiver is detecting an electrical
idle, the receiver portion of the PHY can take appropriate power saving measures. Note
that the PHY is capable of obtaining bit and symbol lock within the PHY-specified time
(N_FTS with or without common clock) upon resumption of signaling on the receive
channel. This requirement only applies if the receiver had previously been bit and symbol
locked while in P0 or P0s states.
P1 state: Selected internal clocks in the PHY are turned off. The MAC will move the PHY to this state only when both transmit and receive channels are idle. The PHY
indicates a successful entry into P1 (by asserting PHYSTATUS). P1 should be used
for the disabled state, all detect states, and L1.idle state of the Link Training and
Status State Machine (LTSSM).
P2 state: PHY will enter P1 instead.
NXP Semiconductors PX1011B
PCI Express stand-alone X1 PHY
[1] TXIDLE=0
[2] TXIDLE=1
8.6 Receiver detect
When the PHY is in the P1 state, it can be instructed to perform a receiver detection
operation to determine if there is a receiver at the other end of the link. Basic operation of
receiver detection is that the MAC requests the PHY to do a receiver detect sequence by
asserting RXDET_LOOPB. When the PHY has completed the receiver detect sequence,
it drives the RXSTATUS signals to the value of 011b if a receiver is present, and to 000b if
there is no receiver. Then the PHY will assert PHYSTATUS to indicate the completion of
receiver detect operation. The MAC uses the rising edge of PHYSTATUS to sample the
RXSTATUS signals and then de-asserts RXDET_LOOPB. A few cycles after the
RXDET_LOOPB de-asserts, the PHYSTATUS is also de-asserted.
8.7 Loopback
The PHY supports an internal loopback from the PCI Express receiver to the transmitter
with the following characteristics.
The PHY retransmits each 10-bit data and control symbol exactly as received, without
applying scrambling or descrambling or disparity corrections, with the following rules: If a received 10-bit symbol is determined to be an invalid 10-bit code (i.e., no legal
translation to a control or data value possible), the PHY still retransmits the symbol
exactly as it was received. If a SKP ordered set retransmission requires adding a SKP symbol to accommodate
timing tolerance correction, any disparity can be chosen for the SKP symbol.
Table 13. Summary of power management state
00b P0, normal operation on[1] on on on on
01b P0s, power saving state idle[2] idle on on on
10b P1, lower power state idle[2] idle on on off
11b illegal, PHY will enter P1 - - - - -
NXP Semiconductors PX1011B
PCI Express stand-alone X1 PHY The PHY continues to provide the received data on the PXPIPE interface, behaving
exactly like normal data reception. The PHY transitions from normal transmission of data from the PXPIPE interface to
looping back the received data at a symbol boundary.
The PHY begins to loopback data when the MAC asserts RXDET_LOOPB while doing
normal data transmission. The PHY stops transmitting data from the PXPIPE interface,
and begins to loopback received symbols. While doing loopback, the PHY continues to
present received data on the PXPIPE interface.
The PHY stops looping back received data when the MAC de-asserts RXDET_LOOPB.
Transmission of data on the parallel interface begins immediately.
The timing diagram of Figure 6 shows example timing for beginning loopback. In this
example, the receiver is receiving a repeating stream of bytes, Rx-a through Rx-z.
Similarly, the MAC is causing the PHY to transmit a repeating stream of bytes Tx-a
through Tx-z. When the MAC asserts RXDET_LOOPB to the PHY , the PHY begins to
loopback the received data to the differential TX_P and TX_N lines.
The timing diagram of Figure 7 shows an example of switching from loopback mode to
normal mode. As soon as the MAC detects an electrical idle ordered-set, the MAC
de-asserts RXDET_LOOPB, asserts TXIDLE and changes the POWERDOWN signals to
state P1.
NXP Semiconductors PX1011B
PCI Express stand-alone X1 PHY
8.8 Electrical idle
The PCI Express Base Specification requires that devices send an Electrical Idle
ordered-set before TX goes to the electrical idle state.
The timing diagram of Figure 8 shows an example of timing for entering electrical idle.
NXP Semiconductors PX1011B
PCI Express stand-alone X1 PHY
Table 14 summarizes the function of some PXPIPE control signals.
8.9 Clock tolerance compensation
The PHY receiver contains an elastic buffer used to compensate for differences in
frequencies between bit rates at the two ends of a link. The elastic buffer is capable of
holding at least seven symbols to handle worst case differences (600 ppm) in frequency
and worst case intervals between SKP ordered-sets. The PHY is responsible for inserting
or removing SKP symbols in the received data stream to avoid elastic buffer overflow or
underflow. The PHY monitors the receive data stream, and when a Skip ordered-set is
received, the PHY can add or remove one SKP symbol from each SKP ordered-set as
appropriate to manage its elastic buffer. Whenever a SKP symbol is added or removed,
the PHY will signal this to the MAC using the RXSTATUS signals. These signals have a
non-zero value for one clock cycle and indicate whether a SKP symbol was added or
removed from the received SKP ordered-set. RXSTATUS should be asserted during the
clock cycle when the COM symbol of the SKP ordered-set is moved across the parallel
interface. If the removal of a SKP symbol causes no SKP symbols to be transferred
across the parallel interface, then RXSTATUS is asserted at the same time that the COM
symbol (that was part of the received skip ordered-set) is transmitted across the parallel
interface.
Figure 9 shows a sequence where the PHY inserted a SKP symbol in the data stream.
Figure 10 shows a sequence where the PHY removed a SKP symbol from a SKP
ordered-set.
Table 14. Control signals function summary
P0: 00b 0 0 normal operation 1 transmitter in idle 0 loopback mode 1 illegal
P0s: 01b X 0 illegal transmitter in idle
P1: 10b X 0 illegal 1 transmitter in idle 1 receiver detect
NXP Semiconductors PX1011B
PCI Express stand-alone X1 PHY
8.10 Error detection
The PHY is responsible for detecting receive errors of several types. These errors are
signaled to the MAC layer using the receiver status signals RXSTATUS.
Because of higher level error detection mechanisms (like CRC) built into the data link
layer of PCI Express, there is no need to specifically identify symbols with errors.
However, timing information about when the error occurred in the data stream is
important. When a receive error occurs, the appropriate error code is asserted for one
clock cycle at the point closest to where the error actually occurred.
There are four error conditions that can be encoded on the RXSTATUS signals. If more
than one error should happen to occur on a received byte, the errors are signaled with the
priority shown below. 8b/10b decode error Elastic buffer overflow Elastic buffer underflow Disparity error
Table 15. Function table PXPIPE status interface signals
Received data OK L L L
One SKP added L L H
One SKP removed L H L
Receiver detected L H H
8b/10b decode error H L L
Elastic buffer overflow H L H
Elastic buffer underflow H H L
Receive disparity error H H H
NXP Semiconductors PX1011B
PCI Express stand-alone X1 PHY
8.10.1 8b/10b decode errors
For a detected 8b/10b decode error, the PHY places an EDB (EnD Bad) symbol in the
data stream in place of the bad byte, and encodes RXSTATUS with a decode error during
the clock cycle when the effected byte is transferred across the parallel interface. In
Figure 11 the receiver is receiving a stream of bytes Rx-a through Rx-z, and byte Rx-c has
an 8b/10b decode error. In place of that byte, the PHY places an EDB on the parallel
interface, and sets RXSTATUS to the 8b/10b decode error code. Note that a byte that
cannot be decoded may also have bad disparity, but the 8b/10b error has precedence.
8.10.2 Disparity errors
For a detected disparity error, the PHY asserts RXSTATUS with the disparity error code
during the clock cycle when the effected byte is transferred across the parallel interface. In
Figure 12 the receiver detected a disparity error on Rx-c data byte, and indicates this with
the assertion of RXSTATUS.
8.10.3 Elastic buffer
For elastic buffer errors, an underflow is signaled during the clock cycle when the spurious
symbol is moved across the parallel interface. The symbol moved across the interface is
the EDB symbol. In the timing diagram Figure 13, the PHY is receiving a repeating set of
symbols Rx-a through Rx-z. The elastic buffer underflow causing the EDB symbol to be
inserted between the Rx-c and Rx-d symbols. The PHY drives RXSTATUS to indicate
buffer underflow during the clock cycle when the EDB is presented on the parallel
interface.
