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PTN3361BBS
HDMI/DVI level shifter with dongle detect support and active DDC buffer
General descriptionThe PTN3361Bisa high-speed level shifter device which converts four lanesof low-swing
AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain
current-steering differential output signals,upto 1.65 Gbit/s per lane. Eachof these lanes
provides a level-shifting differential buffer to translate from low-swing AC-coupled
differential signaling on the source side, to TMDS-type DC-coupled differential
current-mode signaling terminated into 50 Ω to 3.3 V on the sink side. Additionally, the
PTN3361B providesa single-ended active bufferfor voltage translationof the HPD signal
from 5 V on the sink side to 3.3 V on the source side and provides a channel with active
buffering and level shifting of the DDC channel (consisting of a clock and a data line)
between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using
active I2 C-bus buffer technology providing capacitive isolation, redriving and level shifting
as well as disablement (isolation between source and sink) of the clock and data lines.
The low-swing AC-coupled differential input signalsto the PTN3361B typically come from
a display source with multi-mode I/O, which supports multiple display standards, e.g.,
DisplayPort, HDMI and DVI. While the input differential signals are conﬁguredto carry DVI HDMI coded data, theydo not comply with the electrical requirementsof the DVI v1.0or
HDMI v1.3a speciﬁcation. By using PTN3361B, chip set vendors are able to implement
such reconﬁgurable I/Os on multi-mode display source devices, allowing the support of
multiple display standards while keeping the number of chip set I/O pins low. See
Figure1.
The PTN3361B main high-speed differential lanes feature low-swing self-biasing
differential inputs which are compliant to the electrical speciﬁcations of DisplayPort
Standard v1.1 and/or PCI Express Standard v1.1, and open-drain current-steering
differential outputs compliant to DVI v1.0 and HDMI v1.3a electrical speciﬁcations. The2 C-bus channel actively buffers as well as level-translates the DDC signals for optimal
capacitive isolation. Its I2 C-bus control block also provides for optional software HDMI
dongle detect by issuing a predetermined code sequence upon a read command to an2 C-bus speciﬁed address. The PTN3361B also supports power-saving modesin orderto
minimize current consumption when no display is active or connected.
The PTN3361B is a fully featured HDMI as well as DVI level shifter. It is functionally
comparable to PTN3360B but provides additional features supporting HDMI dongle
detection and active DDC buffering. For HDMI dongles, supportof HDMI dongle detection
via the DDC channel is mandatory, hence HDMI dongle applications should enable this
feature for correct operation in accordance with DisplayPort interoperability guidelines.
PTN3361B is powered from a single 3.3 V power supply consuming a small amount of
power (90 mW typ.) and is offered in a 48-terminal HVQFN48 package.
PTN3361B
HDMI/DVI level shifter with dongle detect support and active
DDC buffer
Rev. 02 — 7 October 2009 Product data sheet
NXP Semiconductors PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
NXP Semiconductors PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer Features
2.1 High-speed TMDS level shifting Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and
HDMI v1.3a compliant open-drain current-steering differential output signals Pin-programmable pre-emphasis feature TMDS level shifting operation up to 1.65 Gbit/s per lane (165 MHz character clock) TMDS level shifting operation up to 2.25 Gbit/s per lane (225 MHz character clock)
using pre-emphasis feature Integrated 50 Ω termination resistors for self-biasing differential inputs Back-current safe outputs to disallow current when device power is off and monitor is Disable feature to turn off TMDS inputs and outputs and to enter low-power state
2.2 DDC level shifting Integrated active DDC buffering and level shifting (3.3 V source to 5 V sink side) Rise time accelerator on sink-side DDC ports0 Hz to 400 kHz I2 C-bus clock frequency Back-power safe sink-side terminalsto disallow backdrive current when powerisoffor
when DDC is not enabled
2.3 HDMI dongle detect support Incorporates I2 C slave ROM Responds to DDC read to address 81h with predetermined byte sequence Feature enabled by pin DDET (must be enabled for correct operation in accordance
with DisplayPort interoperability guideline
2.4 HPD level shifting HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or
from 5 V on the sink side to 3.3 V on the source side Integrated 200 kΩ pull-down resistor on HPD sink input guarantees ‘input LOW’ when
no display is plugged in Back-power safe designon HPD_SINKto disallow backdrive current when powerisoff
2.5 General Power supply 3.3V±10% ESD resilience to 7 kV HBM, 1 kV CDM Support for optional HDMI dongle detection via DDC/I2 C-bus channel Power-saving modes (using output enable) Back-current-safe design on all sink-side main link, DDC and HPD terminals Transparent operation: no re-timing or software conﬁguration required
NXP Semiconductors PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer Applications DisplayPort to HDMI adapters (must enable DDET) DisplayPort to DVI adapters required to drive long cables Ordering information
Table 1. Ordering information
PTN3361BBS HVQFN48 plastic thermal enhanced very thin quadﬂat package;no leads;48 terminals;
body7×7× 0.85 mm
SOT619-1
NXP Semiconductors PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer Functional diagram
NXP Semiconductors PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer Pinning information
6.1 Pinning
NXP Semiconductors PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
6.2 Pin description
Table 2. Pin description
OE_N, IN_Dx and OUT_Dx signals
OE_N 25 3.3 V low-voltage
CMOS single-ended
input
Output Enable and power saving function for
high-speed differential level shifter path.
When OE_N = HIGH:
IN_Dx termination = high-impedance
OUT_Dx outputs = high-impedance; zero
output current
When OE_N = LOW:
IN_Dx termination = 50Ω
OUT_Dx outputs = active
IN_D4+ 48 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signalling.
IN_D4+ makes a differential pair with IN_D4−.
The input to this pin must be AC coupled
externally.
IN_D4− 47 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signalling.
IN_D4− makes a differential pair with IN_D4+.
The input to this pin must be AC coupled
externally.
IN_D3+ 45 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signalling.
IN_D3+ makes a differential pair with IN_D3−.
The input to this pin must be AC coupled
externally.
IN_D3− 44 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signalling.
IN_D3− makes a differential pair with IN_D3+.
The input to this pin must be AC coupled
externally.
IN_D2+ 42 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signalling.
IN_D2+ makes a differential pair with IN_D2−.
The input to this pin must be AC coupled
externally.
IN_D2− 41 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signalling.
IN_D2− makes a differential pair with IN_D2+.
The input to this pin must be AC coupled
externally.
IN_D1+ 39 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signalling.
IN_D1+ makes a differential pair with IN_D1−.
The input to this pin must be AC coupled
externally.
NXP Semiconductors PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
IN_D1− 38 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signalling.
IN_D1− makes a differential pair with IN_D1+.
The input to this pin must be AC coupled
externally.
OUT_D4+ 13 TMDS differential
output
HDMI compliant TMDS output. OUT_D4+makes differential pair with OUT_D4−. OUT_D4+isin
phase with IN_D4+.
OUT_D4− 14 TMDS differential
output
HDMI compliant TMDS output. OUT_D4− makes differential pair with OUT_D4+. OUT_D4−isin
phase with IN_D4−.
OUT_D3+ 16 TMDS differential
output
HDMI compliant TMDS output. OUT_D3+makes differential pair with OUT_D3−. OUT_D3+isin
phase with IN_D3+.
OUT_D3− 17 TMDS differential
output
HDMI compliant TMDS output. OUT_D3− makes differential pair with OUT_D3+. OUT_D3−isin
phase with IN_D3−.
OUT_D2+ 19 TMDS differential
output
HDMI compliant TMDS output. OUT_D2+makes differential pair with OUT_D2−. OUT_D2+isin
phase with IN_D2+.
OUT_D2− 20 TMDS differential
output
HDMI compliant TMDS output. OUT_D2− makes differential pair with OUT_D2+. OUT_D2−isin
phase with IN_D2−.
OUT_D1+ 22 TMDS differential
output
HDMI compliant TMDS output. OUT_D1+makes differential pair with OUT_D1−. OUT_D1+isin
phase with IN_D1+.
OUT_D1− 23 TMDS differential
output
HDMI compliant TMDS output. OUT_D1− makes differential pair with OUT_D1+. OUT_D1−isin
phase with IN_D1−.
HPD and DDC signals
HPD_SINK 30 5 V CMOS
single-ended input V to 5 V (nominal) input signal. This signal
comes from the DVIor HDMI sink.A HIGH value
indicates that the sink is connected; a LOW
value indicates that the sink is disconnected.
HPD_SINK is pulled down by an integrated
200 kΩ pull-down resistor.
HPD_SOURCE7 3.3 V CMOS
single-ended output V to 3.3 V (nominal) output signal. This is
level-shifted version of the HPD_SINK signal.
SCL_SOURCE9 single-ended 3.3V
open-drain DDC I/O
3.3 V source-side DDC clock I/O. Pulled up by
external termination to 3.3V.
SDA_SOURCE8 single-ended 3.3V
open-drain DDC I/O
3.3 V source-side DDC data I/O. Pulled up by
external termination to 3.3V.
SCL_SINK 28 single-ended 5V
open-drain DDC I/O V sink-side DDC clock I/O. Pulled up by
external termination to 5 V. Provides rise time
acceleration for LOW-to-HIGH transitions.
SDA_SINK 29 single-ended 5V
open-drain DDC I/O V sink-side DDC data I/O. Pulled up by
external termination to 5 V. Provides rise time
acceleration for LOW-to-HIGH transitions.
Table 2. Pin description …continued
NXP Semiconductors PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
[1] HVQFN48 package supply groundis connectedto both GND pins and exposed center pad. GND pins must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal padthe board andfor proper heat conduction throughthe board, thermal vias needtobe incorporatedinthe
PCB in the thermal pad region.
DDC_EN 32 3.3 V CMOS input Enables the DDC buffer and level shifter.
When DDC_EN = LOW, buffer/level shifter is
disabled.
When DDC_EN = HIGH, buffer and level shifter
are enabled.
Supply and ground
VDD 2, 11,
15, 21,
26, 33,
40, 46
3.3 V DC supply Supply voltage; 3.3V±10%.
VCC -
GND[1] 1, 5,
12, 18,
24, 27,
31, 36,
37, 43
ground Supply ground.All GND pins mustbe connected
to ground for proper operation.
Feature control signals
REXT 6 analog I/O Current sense port used to provide an accurate
current reference for the differential outputs
OUT_Dx. For best output voltage swing
accuracy, useofa10kΩ resistor(1% tolerance)
from this terminalto GNDis recommended. May
also be left open-circuit or tied to either VDD or
GND. See Section 7.2 for details.
DDET 4 3.3 V input Dongle detect enable input. When HIGH, the
dongle detect function via I2 C is active. When
used in an HDMI dongle, this pin must be tied
HIGH for correct operation in accordance with
DisplayPort interoperability guidelines. When
usedina DVI dongle, thispin mustbe tied LOW.
When LOW, the dongle detect function will not
respondtoanI2 C-bus command. Mustbe tiedto
GNDor VDD either directlyorviaa resistor. Note
that this pin may not be left open-circuit.
PES1 10 3.3 V CMOS input Programming pins to activate the pre-emphasis
feature of the TMDS differential outputs. See
Section 7.3 for details. Must be tied either to
GND or VDD either directly or via a resistor. To
disable pre-emphasis, connect both to GND
(PES[1:0]= 00b). PES[1:0]= 11bis reservedfor
testing purposes and should not be used in
normal application. Note that these pins maynot
be left open-circuit.
PES0 3 3.3 V CMOS input
Miscellaneous
n.c. 34, 35 no connection the die
Not connected. Maybeleft open-circuitor tiedto
GND or VDD either directly or via a resistor.
Table 2. Pin description …continued
NXP Semiconductors PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer Functional description
Refer to Figure 2 “Functional diagram of PTN3361B”.
The PTN3361B level shifts four lanesof low-swing AC-coupled differential input signalsto
DVI and HDMI compliant open-drain current-steering differential output signals, up to
1.65 Gbit/s per lane. Speed of operation and cable length drive may be extended (by
using the programmable pre-emphasis feature) to up to 2.25 Gbit/s per lane. It has
integrated 50 Ω termination resistors for AC-coupled differential input signals. An enable
signal OE_N can be used to turn off the TMDS inputs and outputs, thereby minimizing
power consumption. The TMDS outputs are back-power safeto disallow current ﬂow from
a powered sink while the PTN3361B is unpowered.
The PTN3361B's DDC channel provides active level shifting and buffering, allowing 3.3V
source-side termination and 5 V sink-side termination. The sink-side DDC ports are
equipped with a rise time accelerator enabling drive of long cables or high bus
capacitance. This enables the system designer to isolate bus capacitance to meet HDMI
DDC version 1.3a distance speciﬁcation. Furthermore, the DDC channel is augmented
with an I2 C-bus slave ROM device that provides optional HDMI dongle detect response,
which can be enabled by dongle detect signal DDET. The PTN3361B offers back-power
safe sink-side I/Os to disallow backdrive current from the DDC clock and data lines when
power is off or when DDC is not enabled. An enable signal DCC_EN enables the DDC
level shifter block.
Remark: When used in an HDMI dongle, the DDET function must be enabled for correct
operation in accordance with DisplayPort interoperability guidelines. When used in a DVI
dongle, the DDET function must be disabled.
The PTN3361B also provides voltage translation for the Hot Plug Detect (HPD) signal
from 0 V to 5 V on the sink side to 0 V to 3.3 V on the source side.
The PTN3361B does not re-time any data. It contains no state machines except for the
DDC/I2 C-bus block. No inputs or outputs of the device are latched or clocked. Because
the PTN3361B acts as a transparent level shifter, no reset is required.
7.1 Enable and disable features
PTN3361B offers different waysto enableor disable functionality, using the Output Enable
(OE_N) and DDC Enable (DDC_EN) inputs. Whenever the PTN3361B is disabled, the
device will be in Standby mode and power consumption will be minimal; otherwise the
PTN3361B will be in Active mode and power consumption will be nominal. These two
inputs each affect the operation of PTN3361B differently: OE_N affects only the TMDS
channels, and DDC_EN affects only the DDC channel. HPD_SINK does not affect either
of the channels. The following sections and truth table describe their detailed operation.
7.1.1 Hot plug detect
The HPD channel of PTN3361B functions as a level-shifting buffer to pass the HPD logic
signal from the display sink device (via input HPD_SINK) on to the display source device
(via output HPD_SOURCE).
The output logic state of HPD_SOURCE output always follows the logic state of input
HPD_SINK, regardless of whether the device is in Active or Standby mode.
NXP Semiconductors PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
7.1.2 Output Enable function (OE_N)
When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully
functional. Input termination resistors are enabled and the internal bias circuits are turned
on.
When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a
high-impedance state and drive zero output current. The IN_Dx input buffers are disabled
and IN_Dx termination is disabled. Power consumption is minimized.
Remark: Note that OE_N has no inﬂuence on the HPD_SINK input, HPD_SOURCE
output, or the SCL and SDA level shifters. OE_N only affects the high-speed TMDS
channel.
7.1.3 DDC channel enable function (DDC_EN)
The DDC_EN pinis active HIGH and canbe usedto isolatea badly behaved slave. When
DDC_ENis LOW, the DDC channelis turned off. The DDC_EN input should never change
state duringanI2 C-bus operation. Note that disabling DDC_EN duringa bus operation will
hang the bus, while enabling DDC_EN during bus trafﬁc would corrupt the I2 C-bus
operation. Hence, DDC_EN should only be toggled while the bus is idle. (See I2 C-bus
speciﬁcation).
NXP Semiconductors PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
7.1.4 Enable/disable truth table
[1] A HIGH level on input OE_N disables only the TMDS channels.
[2] A LOW level on input DDC_EN disables only the DDC channel.
[3] OUT_Dx channels ‘enabled’ means outputs OUT_Dx toggling in accordance with IN_Dx differential input voltage switching.
[4] DDC channel ‘enabled’ means SDA_SINK is connected to SDA_SOURCE and SCL_SINK is connected to SCL_SOURCE.
[5] The HPD_SOURCE output logic state always follows the HPD_SINK input logic state.
Table 3. HPD_SINK, OE_N and DDC_EN enabling truth table
LOW LOW LOW 50Ω termination
to VRX(bias)
enabled high-impedance LOW Active; DDC
disabled
LOW LOW HIGH 50Ω termination
to VRX(bias)
enabled SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
LOW Active; DDC
enabled
LOW HIGH LOW high-impedance high-impedance;
zero output current
high-impedance LOW Standby
LOW HIGH HIGH high-impedance high-impedance;
zero output current
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
LOW Standby;
DDC
enabled
HIGH LOW LOW 50Ω termination
to VRX(bias)
enabled high-impedance HIGH Active; DDC
disabled
HIGH LOW HIGH 50Ω termination
to VRX(bias)
enabled SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
HIGH Active; DDC
enabled
HIGH HIGH LOW high-impedance high-impedance;
zero output current
high-impedance HIGH Standby
HIGH HIGH HIGH high-impedance high-impedance;
zero output current
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
HIGH Standby;
DDC
enabled
NXP Semiconductors PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
7.2 Analog current reference
The REXT pin (pin6)isan analog current sense port usedto providean accurate current
referencefor the differential outputs OUT_Dx. For best output voltage swing accuracy, use
of a 10 kΩ resistor (1 % tolerance) connected between this terminal and GND is
recommended.
If an external 10 kΩ±1 % resistor is not used, this pin can be left open-circuit, or
connected to GND or VDD, either directly (0 Ω) or using pull-up or pull-down resistors of
value less than 10 kΩ. In any of these cases, the output will function normally but at
reduced accuracy over voltage and temperatureof the following parameters: output levels
(VOL), differential output voltage swing, and rise and fall time accuracy.
7.3 Programmable pre-emphasis
PTN3361B includesan optional programmable pre-emphasis feature, allowing adaptoror
motherboard PCB designers to extend speed performance or support longer cable drive.
The pre-emphasis feature, when enabled, adds a selectable amount of pre-emphasis to
eachbit transitionby injectinga momentary current pulse (typically 200psto 400ps long)
to help overcome cable or trace losses.
Pre-emphasis is not needed for normal HDMI operation at speeds below 1.65 Gbit/s and not requiredto meet eye diagram compliance.At the user's discretion,it canbe enabled orderto provide additional signal boostin difﬁcultor lossy signaling environments such
as long cables or lossy media.
It should be noted that by enabling pre-emphasis, in addition to the AC effect of the
pre-emphasis pulse on the signal transition, also a constant DC current is added in order
to provide the necessary headroom, which will affect VOH and VOL static levels. This
should be taken into account when designing for HDMI or DVI single-ended (DC) voltage
compliance. For full HDMI or DVI compliance in normal applications, the default mode
(pre-emphasis off) is recommended.
The pre-emphasis feature is programmed by means of two CMOS input pins, PES1 and
PES0, according to Table4:
[1] Should not be used in normal application.
7.4 Backdrive current protection
The PTN3361B is designed for backdrive prevention on all sink-side TMDS outputs,
sink-side DDC I/Os and the HPD_SINK input. This supports user scenarios where the
display is connected and powered, but the PTN3361B is unpowered. In these cases, the
PTN3361B will sink no more than a negligible amount of leakage current, and will block
the display (sink) termination network from driving the power supply of the PTN3361B or
that of the inactive DVI or HDMI source.
Table 4. PTN3361B pre-emphasis logic table 0 0 dB (default 1 3.5 dB (150%) 0 6 dB (200%) 1 Test mode[1]
NXP Semiconductors PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
7.5 Active DDC buffer with rise time accelerator
The PTN3361B DDC channel, besides providing 3.3Vto5V level shifting, includes active
buffering and rise time acceleration which allows up to 18 meters bus extension for
reliable DDC applications. While retaining all the operating modes and features of the2 C-bus system during the level shifts, it permits extension of the I2 C-bus by providing
bidirectional buffering for both the data (SDA) and the clock (SCL) line as well as the
rise time accelerator on the sink-side port (SCL_SINK and SDA_SINK) enabling the bus
to drive a load up to 1400 pF or distance of 18 m on port A, and 400 pF on the
source-side port (SCL_SOURCE and SCA_SOURCE). Using the PTN3361B for DVI or
HDMI level shifting enables the system designerto isolate bus capacitanceto meet HDMI
DDC version 1.3 distance speciﬁcation. The SDA and SCL pins are overvoltage tolerant
and are high-impedance when the PTN3361B is unpowered or when DDC_EN is LOW.
PTN3361B has rise time accelerators on the sink-side port (SCL_SINK and SDA_SINK)
only. During positive bus transitions on the sink-side port, a current source is switched on
to quickly slew the SCL_SINK and SDA_SINK lines HIGH once the 5 V DDC bus VIL
threshold level of around 1.5 V is exceeded, and turns off as the 5 V DDC bus VIH
threshold voltage of approximately 3.5 V is approached.
7.6I2 C-bus based HDMI dongle detection
The PTN3361B includes an on-board I2 C-bus slave ROM which provides a means to
detect the presence of an HDMI dongle by the system through the DDC channel,
accessible via ports SDA_SOURCE and SCL_SOURCE. This allows system vendors to
detect HDMI dongle presence through the already available DDC/I2 C-bus port using a
predetermined bus sequence. Please see Section 8 for more information.
For theI2 C-bus HDMI Dongle Detect functiontobe active, input pin DDET (dongle detect)
should be tied HIGH. When DDET is LOW, the PTN3361B will not respond to an I2 C-bus
command. When usedinan HDMI dongle, the DDET function mustbe enabledfor correct
operation in accordance with DisplayPort interoperability guidelines. When used in a DVI
dongle, the DDET function must be disabled.
The HDMI dongle detection is accomplished by accessing the PTN3361B on-board2 C-bus slave ROM usinga simple sequentialI2 C-bus Read operationas described below.
7.6.1 Slave address
NXP Semiconductors PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
7.6.2 Read operation
The slave device address of PTN3361B is 80h. PTN3361B will respond to a Read
command to slave address 81h (PTN3361B will respond with an ACK to a Write
command to address 80h). Following the Read command, the PTN3361B will respond
with the contentsofits internal ROM,asa sequenceof16 bytes,foras longas the master
continues to issue clock edges with an acknowledge after each byte. The 16-byte
sequence represents the ‘DP-HDMI ADAPTOR’ symbol convertedto ASCII andis
documented in Table5.
The PTN3361B auto-incrementsits internal ROM address pointer (0h through Fh)as long
as it continues to receive clock edges from the master with an acknowledge after each
byte. If the master continues to issue clock edges past the 16th byte, the PTN3361B will
respond witha data byteof FFh.If the master does not acknowledgea received byte, the
PTN3361B internal address pointer willbe resetto0 anda new Read sequence shouldbe
started by the master. Access to the 16-byte is by sequential read only as described
above; there is no random-access possible to any speciﬁc byte in the ROM.
Remark: If the slave does not acknowledge the above transaction sequence, the entire
sequence should be retried by the source.
Table 5. DisplayPort - HDMI Adaptor Detection ROM content
Table 6. HDMI dongle detect transaction sequence outline

Partno	Mfg	Dc	Qty	Available	Descript
PTN3361BBS	NXP	N/a	50	avai	HDMI/DVI level shifter with dongle detect support and active DDC buffer