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PTN3360DBS
Enhanced performance HDMI/DVI level shifter with active DDC buffer, supporting 3 Gbit/s operation
1. General descriptionThe PTN3360D is a high-speed level shifter device which converts four lanes of low-swing
AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain
current-steering differential output signals, up to 3.0 Gbit/s per lane to support 36-bit
deep color mode, 4K 2K video format or 3D video data transport. Each of these lanes
provides a level-shifting differential buffer to translate from low-swing AC-coupled
differential signaling on the source side, to TMDS-type DC-coupled differential
current-mode signaling terminated into 50 to 3.3 V on the sink side. Additionally, the
PTN3360D provides a single-ended active buffer for voltage translation of the HPD signal
from 5 V on the sink side to 3.3 V on the source side and provides a channel with active
buffering and level shifting of the DDC channel (consisting of a clock and a data line)
between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using
active I2 C-bus buffer technology providing capacitive isolation, redriving and level shifting
as well as disablement (isolation between source and sink) of the clock and data lines.
The low-swing AC-coupled differential input signals to the PTN3360D typically come from
a display source with multi-mode I/O, which supports multiple display standards, for
example, DisplayPort, HDMI and DVI. While the input differential signals are configured to
carry DVI or HDMI coded data, they do not comply with the electrical requirements of the
DVI v1.0 or HDMI v1.4b specification. By using PTN3360D, chip set vendors are able to
implement such reconfigurable I/Os on multi-mode display source devices, allowing the
support of multiple display standards while keeping the number of chip set I/O pins low.
See Figure1.
The PTN3360D main high-speed differential lanes feature low-swing self-biasing
differential inputs which are compliant to the electrical specifications of DisplayPort
Standard v1.2 and/or PCI Express Standard v1.1, and open-drain current-steering
differential outputs compliant to DVI v1.0 and HDMI v1.4b electrical specifications. The 2 C-bus channel actively buffers as well as level-translates the DDC signals for optimal
capacitive isolation. The PTN3360D also supports power-saving modes in order to
minimize current consumption when no display is active or connected.
The PTN3360D is a fully featured HDMI as well as DVI level shifter. The PTN3360D
supersedes PTN3360B, and provides a better high speed performance with a
programmable equalizer.
PTN3360D is powered from a single 3.3 V power supply consuming a small amount of
power (230 mW typical) and is offered in a 48-terminal HVQFN48 package.
PTN3360D
Enhanced performance HDMI/DVI level shifter with active DDC
buffer, supporting 3 Gbit/s operation
Rev. 4 — 29 June 2012 Product data sheet
NXP Semiconductors PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
NXP Semiconductors PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
2. Features and benefits
2.1 High-speed TMDS level shifting Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and
HDMI v1.4b compliant open-drain current-steering differential output signals TMDS level shifting operation up to 3.0 Gbit/s per lane (300 MHz character clock)
supporting 4K 2K and 3D video formats Programmable equalizer Integrated 50 termination resistors for self-biasing differential inputs Back-current safe outputs to disallow current when device power is off and monitor is Disable feature to turn off TMDS inputs and outputs and to enter low-power state
2.2 DDC level shifting Integrated DDC buffering and level shifting (3.3 V source to 5 V sink side) Rise time accelerator on sink-side DDC ports 0Hz to 400kHz I2 C-bus clock frequency Back-power safe sink-side terminals to disallow backdrive current when power is off or
when DDC is not enabled
2.3 HPD level shifting HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or
from 5 V on the sink side to 3.3 V on the source side Integrated 200 k pull-down resistor on HPD sink input guarantees ‘input LOW’ when
no display is plugged in Back-power safe design on HPD_SINK to disallow backdrive current when power is off
2.4 General Power supply 3.0 V to 3.6V ESD resilience to 6 kV HBM, 1 kV CDM Power-saving modes (using output enable) Back-current-safe design on all sink-side main link, DDC and HPD terminals Transparent operation: no re-timing or software configuration required 48-terminal HVQFN48 package
3. Applications PC motherboard/graphics card Docking station DisplayPort to HDMI adapters supporting 4K 2K and 3D video formats DisplayPort to DVI adapters required to drive long cables
NXP Semiconductors PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
4. Ordering information
5. Functional diagram
Table 1. Ordering informationPTN3360DBS PTN3360DBS HVQFN48 plastic thermal enhanced very thin quad flat package; leads; 48 terminals; body77 0.85 mm
SOT619-1
NXP Semiconductors PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
6. Pinning information
6.1 PinningNXP Semiconductors PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
6.2 Pin description Table 2. Pin description
OE_N, IN_Dx and OUT_Dx signalsOE_N 25 3.3 V low-voltage
CMOS single-ended
input
Output Enable and power saving function for
high-speed differential level shifter path.
When OE_N = HIGH:
IN_Dx termination = high-impedance
OUT_Dx outputs = high-impedance; zero
output current
When OE_N = LOW:
IN_Dx termination = 50
OUT_Dx outputs = active
IN_D4+ 48 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D4+ makes a differential pair with IN_D4.
The input to this pin must be AC coupled
externally.
IN_D4 47 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D4 makes a differential pair with IN_D4+.
The input to this pin must be AC coupled
externally.
IN_D3+ 45 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D3+ makes a differential pair with IN_D3.
The input to this pin must be AC coupled
externally.
IN_D3 44 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D3 makes a differential pair with IN_D3+.
The input to this pin must be AC coupled
externally.
IN_D2+ 42 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D2+ makes a differential pair with IN_D2.
The input to this pin must be AC coupled
externally.
IN_D2 41 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D2 makes a differential pair with IN_D2+.
The input to this pin must be AC coupled
externally.
IN_D1+ 39 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D1+ makes a differential pair with IN_D1.
The input to this pin must be AC coupled
externally.
NXP Semiconductors PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operationIN_D1 38 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D1 makes a differential pair with IN_D1+.
The input to this pin must be AC coupled
externally.
OUT_D4+ 13 TMDS differential
output
HDMI compliant TMDS output. OUT_D4+ makes
a differential pair with OUT_D4. OUT_D4+ is in
phase with IN_D4+.
OUT_D4 14 TMDS differential
output
HDMI compliant TMDS output. OUT_D4 makes
a differential pair with OUT_D4+. OUT_D4 is in
phase with IN_D4.
OUT_D3+ 16 TMDS differential
output
HDMI compliant TMDS output. OUT_D3+ makes
a differential pair with OUT_D3. OUT_D3+ is in
phase with IN_D3+.
OUT_D3 17 TMDS differential
output
HDMI compliant TMDS output. OUT_D3 makes
a differential pair with OUT_D3+. OUT_D3 is in
phase with IN_D3.
OUT_D2+ 19 TMDS differential
output
HDMI compliant TMDS output. OUT_D2+ makes
a differential pair with OUT_D2. OUT_D2+ is in
phase with IN_D2+.
OUT_D2 20 TMDS differential
output
HDMI compliant TMDS output. OUT_D2 makes
a differential pair with OUT_D2+. OUT_D2 is in
phase with IN_D2.
OUT_D1+ 22 TMDS differential
output
HDMI compliant TMDS output. OUT_D1+ makes
a differential pair with OUT_D1. OUT_D1+ is in
phase with IN_D1+.
OUT_D1 23 TMDS differential
output
HDMI compliant TMDS output. OUT_D1 makes
a differential pair with OUT_D1+. OUT_D1 is in
phase with IN_D1.
HPD and DDC signalsHPD_SINK 30 5 V CMOS
single-ended input V to 5 V (nominal) input signal. This signal
comes from the DVI or HDMI sink. A HIGH value
indicates that the sink is connected; a LOW value
indicates that the sink is disconnected.
HPD_SINK is pulled down by an integrated
200 k pull-down resistor.
HPD_SOURCE7 3.3 V CMOS
single-ended output V to 3.3 V (nominal) output signal. This is
level-shifted version of the HPD_SINK signal.
SCL_SOURCE9 single-ended 3.3V
open-drain DDC I/O
3.3 V source-side DDC clock I/O. Pulled up by
external termination to 3.3 V. 5 V tolerant I/O.
SDA_SOURCE8 single-ended 3.3V
open-drain DDC I/O
3.3 V source-side DDC data I/O. Pulled up by
external termination to 3.3 V. 5 V tolerant I/O.
SCL_SINK 28 single-ended 5V
open-drain DDC I/O V sink-side DDC clock I/O. Pulled up by
external termination to 5 V. Provides rise time
acceleration for LOW-to-HIGH transitions.
SDA_SINK 29 single-ended 5V
open-drain DDC I/O V sink-side DDC data I/O. Pulled up by
external termination to 5 V. Provides rise time
acceleration for LOW-to-HIGH transitions.
Table 2. Pin description …continued
NXP Semiconductors PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation[1] HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins and
the exposed center pad must be connected to supply ground for proper device operation. For enhanced
thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using
a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
DDC_EN 32 3.3 V CMOS input Enables the DDC buffer and level shifter.
When DDC_EN = LOW, buffer/level shifter is
disabled.
When DDC_EN = HIGH, buffer and level shifter
are enabled.
Supply and groundVDD 2, 11,
15, 21,
26, 33,
40, 46
3.3 V DC supply Supply voltage; 3.3V10%.
GND[1] 1, 5,
12, 18,
24, 27,
31, 36,
37, 43
ground Supply ground. All GND pins must be connected
to ground for proper operation.
Feature control signalsREXT 6 analog I/O Current sense port used to provide an accurate
current reference for the differential outputs
OUT_Dx. For best output voltage swing
accuracy, use of a 10 k resistor (1 % tolerance)
from this terminal to GND is recommended. May
also be tied to either VDD or GND directly (0 ).
See Section 7.2 for details.
n.c. 4, 10,
34, 35 not connected
EQ5 3 3.3 V low-voltage
CMOS quinary input
Equalizer setting input pin. This pin can be
board-strapped to one of five decode values:
short to GND, resistor to GND, open-circuit,
resistor to VDD, short to VDD. See Table 4 for
truth table.
Table 2. Pin description …continued
NXP Semiconductors PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
7. Functional descriptionRefer to Figure 2 “Functional diagram of PTN3360D”.
The PTN3360D level shifts four lanes of low-swing AC-coupled differential input signals to
DVI and HDMI compliant open-drain current-steering differential output signals, up to
3.0 Gbit/s per lane to support 36-bit deep color mode. It has integrated 50 termination
resistors for AC-coupled differential input signals. An enable signal OE_N can be used to
turn off the TMDS inputs and outputs, thereby minimizing power consumption. The TMDS
outputs are back-power safe to disallow current flow from a powered sink while the
PTN3360D is unpowered.
The PTN3360D's DDC channel provides active level shifting and buffering, allowing 3.3V
source-side termination and 5 V sink-side termination. The sink-side DDC ports are
equipped with a rise time accelerator enabling drive of long cables or high bus
capacitance. This enables the system designer to isolate bus capacitance to meet/exceed
HDMI DDC specification. The PTN3360D offers back-power safe sink-side I/Os to
disallow backdrive current from the DDC clock and data lines when power is off or when
DDC is not enabled. An enable signal DCC_EN enables the DDC level shifter block.
The PTN3360D also provides voltage translation for the Hot Plug Detect (HPD) signal
from 0 V to 5 V on the sink side to 0 V to 3.3 V on the source side.
The PTN3360D does not re-time any data. It contains no state machines. No inputs or
outputs of the device are latched or clocked. Because the PTN3360D acts as a
transparent level shifter, no reset is required.
7.1 Enable and disable featuresPTN3360D offers different ways to enable or disable functionality, using the Output
Enable (OE_N), and DDC Enable (DDC_EN) inputs. Whenever the PTN3360D is
disabled, the device will be in Standby mode and power consumption will be minimal;
otherwise the PTN3360D will be in active mode and power consumption will be nominal.
These two inputs each affect the operation of PTN3360D differently: OE_N controls the
TMDS channels, DDC_EN affects only the DDC channel, and HPD_SINK does not affect
either of the channels. The following sections and truth table describe their detailed
operation.
7.1.1 Hot plug detect The HPD channel of PTN3360D functions as a level-shifting buffer to pass the HPD logic
signal from the display sink device (via input HPD_SINK) on to the display source device
(via output HPD_SOURCE).
The output logic state of HPD_SOURCE output always follows the logic state of input
HPD_SINK, regardless of whether the device is in Active mode or Standby mode.
NXP Semiconductors PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
7.1.2 Output Enable function (OE_N)When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully
functional. Input termination resistors are enabled and the internal bias circuits are turned
on.
When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a
high-impedance state and drive zero output current. The IN_Dx input buffers are disabled
and IN_Dx termination is disabled. Power consumption is minimized.
Remark: Note that OE_N signal level has no influence on the HPD_SINK input, HPD_SOURCE output, or the SCL and SDA level shifters. A transition from HIGH to LOW
at OE_N may disable the DDC channel for up to 20 s.
7.1.3 DDC channel enable function (DDC_EN)The DDC_EN pin is active HIGH and can be used to isolate a badly behaved slave. When
DDC_EN is LOW, the DDC channel is turned off. The DDC_EN input should never
change state during an I2 C-bus operation. Note that disabling DDC_EN during a bus
operation may hang the bus, while enabling DDC_EN during bus traffic would corrupt the 2 C-bus operation. Hence, DDC_EN should only be toggled while the bus is idle. (See 2 C-bus specification).
NXP Semiconductors PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
7.1.4 Enable/disable truth table[1] A HIGH level on input OE_N disables only the TMDS channels. A transition from HIGH to LOW at OE_N may disable the DDC channel
for up to 20s.
[2] A LOW level on input DDC_EN disables only the DDC channel.
[3] OUT_Dx channels ‘enabled’ means outputs OUT_Dx toggling in accordance with IN_Dx differential input voltage switching.
[4] DDC channel ‘enabled’ means SDA_SINK is connected to SDA_SOURCE and SCL_SINK is connected to SCL_SOURCE.
[5] The HPD_SOURCE output logic state always follows the HPD_SINK input logic state.
Table 3. HPD_SINK, OE_N and DDC_EN enabling truth tableLOW LOW LOW 50 termination
to VRX(bias)
enabled high-impedance LOW Active; DDC
disabled
LOW LOW HIGH 50 termination
to VRX(bias)
enabled SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
LOW Active; DDC
enabled
LOW HIGH LOW high-impedance high-impedance;
zero output current
high-impedance LOW Standby
LOW HIGH HIGH high-impedance high-impedance;
zero output current
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
LOW Standby;
DDC
enabled
HIGH LOW LOW 50 termination
to VRX(bias)
enabled high-impedance HIGH Active; DDC
disabled
HIGH LOW HIGH 50 termination
to VRX(bias)
enabled SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
HIGH Active; DDC
enabled
HIGH HIGH LOW high-impedance high-impedance;
zero output current
high-impedance HIGH Standby
HIGH HIGH HIGH high-impedance high-impedance;
zero output current
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
HIGH Standby;
DDC
enabled
NXP Semiconductors PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
7.2 Analog current referenceThe REXT pin (pin 6) is an analog current sense port used to provide an accurate current
reference for the differential outputs OUT_Dx. For best output voltage swing accuracy,
use of a 10 k resistor (1 % tolerance) connected between this terminal and GND is
recommended.
If an external 10 k1 % resistor is not used, this pin can be connected to GND or VDD
directly (0 ). In any of these cases, the output will function normally but at reduced
accuracy over voltage and temperature of the following parameters: output levels (VOL),
differential output voltage swing, and rise and fall time accuracy.
7.3 EqualizerThe PTN3360D supports 5 level equalization setting by the quinary input pin EQ5.
7.4 Backdrive current protectionThe PTN3360D is designed for backdrive prevention on all sink-side TMDS outputs,
sink-side DDC I/Os and the HPD_SINK input. This supports user scenarios where the
display is connected and powered, but the PTN3360D is unpowered. In these cases, the
PTN3360D will sink no more than a negligible amount of leakage current, and will block
the display (sink) termination network from driving the power supply of the PTN3360D or
that of the inactive DVI or HDMI source.
7.5 Active DDC buffer with rise time acceleratorThe PTN3360D DDC channel, besides providing 3.3 V to 5 V level shifting, includes
active buffering and rise time acceleration which allows up to 18 meters bus extension for
reliable DDC applications. While retaining all the operating modes and features of the 2 C-bus system during the level shifts, it permits extension of the I2 C-bus by providing
bidirectional buffering for both the data (SDA) and the clock (SCL) line as well as the
rise time accelerator on the sink-side port (SCL_SINK and SDA_SINK) enabling the bus
to drive a load up to 1400 pF or distance of 18 m on the sink-side port, and 400 pF on the
source-side port (SCL_SOURCE and SCA_SOURCE). Using the PTN3360D for DVI or
HDMI level shifting enables the system designer to isolate bus capacitance to
meet/exceed HDMI DDC specification. The SDA and SCL pins are overvoltage tolerant
and are high-impedance when the PTN3360D is unpowered or when DDC_EN is LOW.
Table 4. Equalizer settingsshort to GND 05 0dB k resistor to GND 15 2dB
open-circuit 25 3.5dB k resistor to VDD 35 9dB
short to VDD 45 7dB
