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PTN3360ABS
Enhanced performance HDMI/DVI level shifter with inverting HPD
General descriptionThe PTN3360Aisa high-speed level shifter device which converts four lanesof low-swing
AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain
current-steering differential output signals, up to 2.5 Gbit/s per lane. Each of these lanes
provides a level-shifting differential buffer to translate from low-swing AC-coupled
differential signaling on the source side, to TMDS-type DC-coupled differential
current-mode signaling terminated into 50 Ω to 3.3 V on the sink side. Additionally, the
PTN3360A providesa single-ended active bufferfor voltage translationof the HPD signal
from 5 V on the sink side to 1.1 V on the source side and provides a channel for level
shifting of the DDC channel (consisting of a clock and a data line) between 3.3V
source-side and 5 V sink-side. The DDC channel is implemented using pass-gate
technology providing level shifting as well as disablement (isolation between source and
sink) of the clock and data lines.
The low-swing AC-coupled differential input signalsto the PTN3360A typically come from
a display source with multi-mode I/O, which supports multiple display standards, e.g.,
DisplayPort, HDMI and DVI. While the input differential signals are conﬁguredto carry DVI HDMI coded data, theydo not comply with the electrical requirementsof the DVI v1.0or
HDMI v1.3a speciﬁcation. By using PTN3360A, chip set vendors are able to implement
such reconﬁgurable I/Os on multi-mode display source devices, allowing the support of
multiple display standards while keeping the number of chip set I/O pins low. See
Figure1.
The PTN3360A main high-speed differential lanes feature low-swing self-biasing
differential inputs which are compliant to the electrical speciﬁcations of DisplayPort
Standard v1.1 and/or PCI Express Standard v1.1, and open-drain current-steering
differential outputs compliant to DVI v1.0 and HDMI v1.3a electrical speciﬁcations. The2 C-bus channel level-translates the DDC signals between 3.3V (source) and 5.0V (sink).
The PTN3360A is a fully featured HDMI as well as DVI level shifter. It is functionally
equivalent to PTN3300A but provides higher speed performance and higher ESD
robustness. The PTN3360A is also equivalent to PTN3360B with the exception that
PTN3360A provides inverting level shifting on the HPD channel.
PTN3360A is powered from a single 3.3 V power supply consuming a small amount of
power (120 mW typ.) and is offered in a 48-terminal HVQFN48 package.
PTN3360A
Enhanced performance HDMI/DVI level shifter with inverting
HPD
Rev. 02 — 8 October 2009 Product data sheet
NXP Semiconductors PTN3360A
Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD
NXP Semiconductors PTN3360A
Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD Features
2.1 High-speed TMDS level shifting Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and
HDMI v1.3a compliant open-drain current-steering differential output signals TMDS level shifting operation up to 2.5 Gbit/s per lane (250 MHz character clock) Integrated 50 Ω termination resistors for self-biasing differential inputs Back-current safe outputs to disallow current when device power is off and monitor is Disable feature to turn off TMDS inputs and outputs and to enter low-power state
2.2 DDC level shifting Integrated DDC level shifting (3.3 V source to 5 V sink side)0 Hz to 400 kHz I2 C-bus clock frequency Back-power safe sink-side terminalsto disallow backdrive current when powerisoffor
when DDC is not enabled
2.3 HPD level shifting HPD inverting level shift from 0 V on the sink side to 1.1 V on the source side, or from V on the sink side to 0 V on the source side Integrated 200 kΩ pull-down resistor on HPD sink input guarantees ‘input LOW’ when
no display is plugged in Back-power safe designon HPD_SINKto disallow backdrive current when powerisoff
2.4 General Power supply 3.3V±10% ESD resilience to 8 kV HBM, 500 V CDM Power-saving modes (using output enable) Back-current-safe design on all sink-side main link, DDC and HPD terminals Transparent operation: no re-timing or software conﬁguration required Ordering information
Table 1. Ordering information
PTN3360ABS HVQFN48 plastic thermal enhanced very thin quadﬂat package;no leads;48 terminals;
body7×7× 0.85 mm
SOT619-1
NXP Semiconductors PTN3360A
Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD Functional diagram
NXP Semiconductors PTN3360A
Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD Pinning information
5.1 Pinning
NXP Semiconductors PTN3360A
Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD
5.2 Pin description
Table 2. Pin description
OE_N, IN_Dx and OUT_Dx signals
OE_N 25 3.3 V low-voltage
CMOS single-ended
input
Output Enable and power saving functionfor high-speed differential
level shifter path.
When OE_N = HIGH:
IN_Dx termination = high-impedance
OUT_Dx outputs = high-impedance; zero output current
When OE_N = LOW:
IN_Dx termination = 50Ω
OUT_Dx outputs = active
IN_D4+ 48 Self-biasing
differential input
Low-swing differential input from display source with PCI Express
electrical signalling. IN_D4+ makes a differential pair with IN_D4−.
The input to this pin must be AC coupled externally.
IN_D4− 47 Self-biasing
differential input
Low-swing differential input from display source with PCI Express
electrical signalling. IN_D4− makes a differential pair with IN_D4+.
The input to this pin must be AC coupled externally.
IN_D3+ 45 Self-biasing
differential input
Low-swing differential input from display source with PCI Express
electrical signalling. IN_D3+ makes a differential pair with IN_D3−.
The input to this pin must be AC coupled externally.
IN_D3− 44 Self-biasing
differential input
Low-swing differential input from display source with PCI Express
electrical signalling. IN_D3− makes a differential pair with IN_D3+.
The input to this pin must be AC coupled externally.
IN_D2+ 42 Self-biasing
differential input
Low-swing differential input from display source with PCI Express
electrical signalling. IN_D2+ makes a differential pair with IN_D2−.
The input to this pin must be AC coupled externally.
IN_D2− 41 Self-biasing
differential input
Low-swing differential input from display source with PCI Express
electrical signalling. IN_D2− makes a differential pair with IN_D2+.
The input to this pin must be AC coupled externally.
IN_D1+ 39 Self-biasing
differential input
Low-swing differential input from display source with PCI Express
electrical signalling. IN_D1+ makes a differential pair with IN_D1−.
The input to this pin must be AC coupled externally.
IN_D1− 38 Self-biasing
differential input
Low-swing differential input from display source with PCI Express
electrical signalling. IN_D1− makes a differential pair with IN_D1+.
The input to this pin must be AC coupled externally.
OUT_D4+ 13 TMDS differential
output
HDMI compliant TMDS output. OUT_D4+ makes a differential pair
with OUT_D4−. OUT_D4+ is in phase with IN_D4+.
OUT_D4− 14 TMDS differential
output
HDMI compliant TMDS output. OUT_D4− makes a differential pair
with OUT_D4+. OUT_D4− is in phase with IN_D4−.
OUT_D3+ 16 TMDS differential
output
HDMI compliant TMDS output. OUT_D3+ makes a differential pair
with OUT_D3−. OUT_D3+ is in phase with IN_D3+.
OUT_D3− 17 TMDS differential
output
HDMI compliant TMDS output. OUT_D3− makes a differential pair
with OUT_D3+. OUT_D3− is in phase with IN_D3−.
OUT_D2+ 19 TMDS differential
output
HDMI compliant TMDS output. OUT_D2+ makes a differential pair
with OUT_D2−. OUT_D2+ is in phase with IN_D2+.
OUT_D2− 20 TMDS differential
output
HDMI compliant TMDS output. OUT_D2− makes a differential pair
with OUT_D2+. OUT_D2− is in phase with IN_D2−.
NXP Semiconductors PTN3360A
Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD
[1] HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
OUT_D1+ 22 TMDS differential
output
HDMI compliant TMDS output. OUT_D1+ makes a differential pair
with OUT_D1−. OUT_D1+ is in phase with IN_D1+.
OUT_D1− 23 TMDS differential
output
HDMI compliant TMDS output. OUT_D1− makes a differential pair
with OUT_D1+. OUT_D1− is in phase with IN_D1−.
HPD and DDC signals
HPD_SINK 30 5 V CMOS
single-ended inputVto5V (nominal) input signal. This signal comes from the DVIor
HDMI sink. A HIGH value indicates that the sink is connected; a
LOW value indicates that the sink is disconnected. HPD_SINK is
pulled down by an integrated 200 kΩ pull-down resistor.
HPD_SOURCE_ 1.1 V CMOS
single-ended output V to 1.1 V (nominal) output signal. This is level-shifted
logic-inverted version of the HPD_SINK signal.
SCL_SOURCE 9 single-ended 3.3V
open-drain DDC I/O
3.3 V source-side DDC clock I/O. Pulled up by external termination
to 3.3V.
SDA_SOURCE 8 single-ended 3.3V
open-drain DDC I/O
3.3 V source-side DDC data I/O. Pulled up by external termination
to 3.3V.
SCL_SINK 28 single-ended 5V
open-drain DDC I/O V sink-side DDC clock I/O. Pulled up by external termination to
5V.
SDA_SINK 29 single-ended 5V
open-drain DDC I/OV sink-side DDC data I/O. Pulledupby external terminationto5V.
DDC_EN 32 3.3 V CMOS input Enables the DDC buffer and level shifter.
When DDC_EN = LOW, buffer/level shifter is disabled.
When DDC_EN = HIGH, buffer and level shifter are enabled.
Supply and ground
VDD 2, 11, 15,
21, 26,33,
40, 46
3.3 V DC supply Supply voltage; 3.3V±10%.
VCC -
GND[1] 1, 5, 12,
18, 24,27,
31, 36,37,
ground Supply ground. All GND pins must be connected to ground for
proper operation.
Feature control signals
REXT 6 analog I/O Current sense port used to provide an accurate current reference
for the differential outputs OUT_Dx. For best output voltage swing
accuracy, use of a 10 kΩ resistor (1 % tolerance) from this terminal
to GND is recommended. May also be left open-circuit or tied to
either VDD or GND. See Section 6.2 for details.
Miscellaneous
n.c. 3, 4, 10,
34, 35
no connection the die
Not connected. Maybeleft open-circuitor tiedto GNDor VDD either
directly or via a resistor.
Table 2. Pin description …continued
NXP Semiconductors PTN3360A
Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD Functional description
Refer to Figure 2 “Functional diagram of PTN3360A”.
The PTN3360A level shifts four lanesof low-swing AC-coupled differential input signalsto
DVI and HDMI compliant open-drain current-steering differential output signals, up to
2.5 Gbit/s per lane.It has integrated50Ω termination resistorsfor AC-coupled differential
input signals. An enable signal OE_N can be used to turn off the TMDS inputs and
outputs, thereby minimizing power consumption. The TMDS outputs, HPD_SINK input
and DDC_SINK I/Os are back-power safe to disallow current ﬂow from a powered sink
while the PTN3360A is unpowered.
The PTN3360A's DDC channel provides active level shifting and buffering, allowing 3.3V
source-side termination and 5 V sink-side termination. The sink-side DDC ports are
equipped with a rise time accelerator enabling drive of long cables or high bus
capacitance. This enables the system designer to isolate bus capacitance to meet HDMI
DDC version 1.3a distance speciﬁcation. The PTN3360A offers back-power safe sink-side
I/Osto disallow backdrive current from the DDC clock and data lines when powerisoffor
when DDCis not enabled. An enable signal DCC_EN enables the DDC level shifter block.
The PTN3360A also provides voltage translation for the Hot Plug Detect (HPD) signal
from0Vto5Von the sink side, inverting and level-shiftingto 1.1V/0Von the source side.
The PTN3360A does not re-time any data. It contains no state machines except for the
DDC/I2 C-bus block. No inputs or outputs of the device are latched or clocked. Because
the PTN3360A acts as a transparent level shifter, no reset is required.
6.1 Enable and disable features
PTN3360A offers different waysto enableor disable functionality, using the Output Enable
(OE_N) and DDC Enable (DDC_EN) inputs. Whenever the PTN3360A is disabled, the
device will be in Standby mode and power consumption will be minimal; otherwise the
PTN3360A will be in Active mode and power consumption will be nominal. These two
inputs each affect the operation of PTN3360A differently: OE_N affects only the TMDS
channels, and DDC_EN affects only the DDC channel. HPD_SINK does not affect either
of the channels. The following sections and truth table describe their detailed operation.
6.1.1 Hot plug detect
The HPD channel of PTN3360A functions as a level-shifting buffer to pass the HPD logic
signal from the display sink device (via input HPD_SINK) on to the display source device
(via output HPD_SOURCE_N).
The output logic stateof HPD_SOURCE_N output always follows the inverse logic stateof
input HPD_SINK, regardless of whether the device is in Active or Standby mode.
NXP Semiconductors PTN3360A
Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD
6.1.2 Output Enable function (OE_N)
When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully
functional. Input termination resistors are enabled and the internal bias circuits are turned
on.
When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a
high-impedance state and drive zero output current. The IN_Dx input buffers are disabled
and IN_Dx termination is disabled. Power consumption is minimized.
Remark: Note that OE_N has no inﬂuence on the HPD_SINK input, HPD_SOURCE_N
output, or the SCL and SDA level shifters. OE_N only affects the high-speed TMDS
channel.
6.1.3 DDC channel enable function (DDC_EN)
The DDC_EN pinis active HIGH and canbe usedto isolatea badly behaved slave. When
DDC_ENis LOW, the DDC channelis turned off. The DDC_EN input should never change
state duringanI2 C-bus operation. Note that disabling DDC_EN duringa bus operation will
hang the bus, while enabling DDC_EN during bus trafﬁc would corrupt the I2 C-bus
operation. Hence, DDC_EN should only be toggled while the bus is idle. (See I2 C-bus
speciﬁcation).
NXP Semiconductors PTN3360A
Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD
6.1.4 Enable/disable truth table
[1] A HIGH level on input OE_N disables only the TMDS channels.
[2] A LOW level on input DDC_EN disables only the DDC channel.
[3] OUT_Dx channels ‘enabled’ means outputs OUT_Dx toggling in accordance with IN_Dx differential input voltage switching.
[4] DDC channel ‘enabled’ means SDA_SINK is connected to SDA_SOURCE and SCL_SINK is connected to SCL_SOURCE.
[5] The HPD_SOURCE_N output logic state always follows the inverse of the HPD_SINK input logic state.
Table 3. HPD_SINK, OE_N and DDC_EN enabling truth table
LOW LOW LOW 50Ω termination
to VRX(bias)
enabled high-impedance HIGH Active;
DDC
disabled
LOW LOW HIGH 50Ω termination
to VRX(bias)
enabled SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
HIGH Active;
DDC
enabled
LOW HIGH LOW high-impedance high-impedance;
zero output current
high-impedance HIGH Standby
LOW HIGH HIGH high-impedance high-impedance;
zero output current
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
HIGH Standby;
DDC
enabled
HIGH LOW LOW 50Ω termination
to VRX(bias)
enabled high-impedance LOW Active;
DDC
disabled
HIGH LOW HIGH 50Ω termination
to VRX(bias)
enabled SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
LOW Active;
DDC
enabled
HIGH HIGH LOW high-impedance high-impedance;
zero output current
high-impedance LOW Standby
HIGH HIGH HIGH high-impedance high-impedance;
zero output current
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
LOW Standby;
DDC
enabled
NXP Semiconductors PTN3360A
Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD
6.2 Analog current reference
The REXT pin (pin6)isan analog current sense port usedto providean accurate current
referencefor the differential outputs OUT_Dx. For best output voltage swing accuracy, use
of a 10 kΩ resistor (1 % tolerance) connected between this terminal and GND is
recommended.
If an external 10 kΩ±1 % resistor is not used, this pin can be left open-circuit, or
connected to GND or VDD, either directly (0 Ω) or using pull-up or pull-down resistors of
value less than 10 kΩ. In any of these cases, the output will function normally but at
reduced accuracy over voltage and temperatureof the following parameters: output levels
(VOL), differential output voltage swing, and rise and fall time accuracy.
6.3 Backdrive current protection
The PTN3360A is designed for backdrive prevention on all sink-side TMDS outputs,
sink-side DDC I/Os and the HPD_SINK input. This supports user scenarios where the
display is connected and powered, but the PTN3360A is unpowered. In these cases, the
PTN3360A will sink no more than a negligible amount of leakage current, and will block
the display (sink) termination network from driving the power supply of the PTN3360A or
that of the inactive DVI or HDMI source.

Partno	Mfg	Dc	Qty	Available	Descript
PTN3360ABS	NXP	N/a	1635	avai	Enhanced performance HDMI/DVI level shifter with inverting HPD