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PSMN7R0-30YL |PSMN7R030YLNXPN/a1500avaiN-channel 30 V 7 m鈩?logic level MOSFET in LFPAK


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PSMN7R0-30YL
N-channel 30 V 7 m鈩?logic level MOSFET in LFPAK
Product profile1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits High efficiency due to low switching
and conduction losses Suitable for logic level gate drive
sources
1.3 Applications Class-D amplifiers DC-to-DC converter Motor control Server power supplies
1.4 Quick reference data
PSMN7R0-30YL
N-channel 30 V 7 mΩ logic level MOSFET in LFPAK
Rev. 04 — 9 March 2011 Product data sheet
Table 1. Quick reference data
VDS drain-source voltage Tj≥25 °C; Tj≤ 175°C --30 V drain current Tmb =25°C; VGS =10V;see Figure 1 --76 A
Ptot total power
dissipation
Tmb=25 °C; see Figure 2 --51 W junction temperature -55 - 175 °C
Static characteristics
RDSon drain-source on-state
resistance
VGS =10V; ID =15A; =25°C
-4.927 mΩ
Dynamic characteristics
QGD gate-drain charge VGS =4.5 V; ID =10A; VDS =12V; see Figure 14;
see Figure 15
-2.9 -nC
QG(tot) total gate charge - 10 - nC
Avalanche ruggedness
EDS(AL)S non-repetitive
drain-source
avalanche energy
VGS =10V; Tj(init) =25°C; =65 A; Vsup≤30V; RGS =50 Ω; unclamped
--21 mJ
NXP Semiconductors PSMN7R0-30YL
N-channel 30 V 7 mΩ logic level MOSFET in LFPAK Pinning information Ordering information Limiting values
Table 2. Pinning information
Table 3. Ordering information
PSMN7R0-30YL LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage Tj≥25 °C; Tj≤ 175°C - 30 V
VDSM peak drain-source voltage tp≤25 ns; f≤ 500 kHz; EDS(AL)≤90 nJ;
pulsed
-35 V
VDGR drain-gate voltage Tj≥25 °C; Tj≤ 175 °C; RGS =20kΩ -30 V
VGS gate-source voltage -20 20 V drain current VGS =10V; Tmb= 100 °C; see Figure 1 -53 A
VGS =10V; Tmb =25°C; see Figure 1 -76 A
IDM peak drain current pulsed; tp≤10 µs; Tmb =25°C;
see Figure 3 260 A
Ptot total power dissipation Tmb =25°C; see Figure 2 -51 W
Tstg storage temperature -55 175 °C junction temperature -55 175 °C
Source-drain diode source current Tmb =25°C - 65 A
ISM peak source current pulsed; tp≤10 µs; Tmb=25°C - 260 A
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
VGS =10V; Tj(init) =25°C; ID =65A;
Vsup≤30 V; RGS =50 Ω; unclamped
-21 mJ
NXP Semiconductors PSMN7R0-30YL
N-channel 30 V 7 mΩ logic level MOSFET in LFPAK
NXP Semiconductors PSMN7R0-30YL
N-channel 30 V 7 mΩ logic level MOSFET in LFPAK Thermal characteristics
Table 5. Thermal characteristics
Rth(j-mb) thermal resistance from
junction to mounting base
see Figure 4 - 1.4 2.45 K/W
NXP Semiconductors PSMN7R0-30YL
N-channel 30 V 7 mΩ logic level MOSFET in LFPAK CharacteristicsTable 6. Characteristics
Tested to JEDEC standards where applicable.
Static characteristics
V(BR)DSS drain-source
breakdown voltage =250 µA; VGS =0V; Tj=25°C 30 --V =250 µA; VGS =0V; Tj= -55°C 27 - - V
VGS(th) gate-source threshold
voltage =1mA; VDS =VGS; Tj =25°C;
see Figure 11; see Figure 12
1.3 1.7 2.15 V =1mA; VDS =VGS; Tj= 150 °C;
see Figure 12
0.65 - - V =1mA; VDS =VGS; Tj =-55 °C;
see Figure 12
--2.45 V
IDSS drain leakage current VDS =30V; VGS =0V; Tj=25°C --1 µA
VDS =30V; VGS =0V; Tj= 150°C - - 100 µA
IGSS gate leakage current VGS =16V; VDS =0V; Tj=25°C - - 100 nA
VGS =-16 V; VDS =0V; Tj=25°C - - 100 nA
RDSon drain-source on-state
resistance
VGS =4.5 V; ID =15A; Tj=25°C - 6.97 9.1 mΩ
VGS =10V; ID =15A; Tj= 150 °C;
see Figure 13 - 12.2 mΩ
VGS =10V; ID =15A; Tj=25°C - 4.92 7 mΩ gate resistance f=1 MHz - 0.6 1.5 Ω
Dynamic characteristics
QG(tot) total gate charge ID =10A; VDS =12V; VGS =4.5V;
see Figure 14; see Figure 15
-10 -nC =0A; VDS =0V; VGS =10V - 20 - nC =10A; VDS =12V; VGS =10V;
see Figure 14; see Figure 15
-22 -nC
QGS gate-source charge ID =10A; VDS =12V; VGS =4.5V;
see Figure 14; see Figure 15
-3.7 -nC
QGS(th) pre-threshold
gate-source charge
-2.1 -nC
QGS(th-pl) post-threshold
gate-source charge
-1.6 -nC
QGD gate-drain charge - 2.9 - nC
VGS(pl) gate-source plateau
voltage
VDS =12V; see Figure 14;
see Figure 15
-2.6 -V
Ciss input capacitance VDS =12V; VGS=0 V; f=1 MHz; =25°C; see Figure 16 1270 - pF
Coss output capacitance - 255 - pF
Crss reverse transfer
capacitance 145 - pF
td(on) turn-on delay time VDS =12V; RL =0.5 Ω; VGS =4.5V;
RG(ext) =4.7Ω
-24 -ns rise time - 39 - ns
td(off) turn-off delay time - 30 - ns fall time - 11 - ns
NXP Semiconductors PSMN7R0-30YL
N-channel 30 V 7 mΩ logic level MOSFET in LFPAK
Source-drain diode
VSD source-drain voltage IS =25A; VGS =0V; Tj =25°C;
see Figure 17 0.88 1.2 V
trr reverse recovery time IS =20A; dIS/dt= -100 A/µs; VGS =0V;
VDS =20V
-30 -ns recovered charge - 22 - nC
Table 6. Characteristics …continued
Tested to JEDEC standards where applicable.
NXP Semiconductors PSMN7R0-30YL
N-channel 30 V 7 mΩ logic level MOSFET in LFPAK
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