PSMN057-200B ,N-channel TrenchMOS(tm) transistorELECTRICAL CHARACTERISTICST= 25˚C unless otherwise specifiedjSYMBOL PARAMETER CONDITIONS MIN. TYP. ..
PSMN057-200B ,N-channel TrenchMOS(tm) transistor
PSMN057-200B ,N-channel TrenchMOS(tm) transistor
PSMN057-200P ,N-channel TrenchMOS(tm) transistor
PSMN057-200P ,N-channel TrenchMOS(tm) transistorELECTRICAL CHARACTERISTICST= 25˚C unless otherwise specifiedjSYMBOL PARAMETER CONDITIONS MIN. TYP. ..
PSMN057-200P ,N-channel TrenchMOS(tm) transistorLimiting values in accordance with the Absolute Maximum System (IEC 134)SYMBOL PARAMETER CONDITIONS ..
QL4009-1PF100C , 9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM
QL4009-1PF100C , 9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM
QL4009-1PF100I , 9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM
QL4016-0PF144C , 16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM
QL4016-0PF144C , 16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM
QL4016-0PF144C , 16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM
PSMN057-200B
N-channel TrenchMOS(tm) transistor
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN057-200B
FEATURES SYMBOL QUICK REFERENCE DATA ’Trench’ technology Very low on-state resistance VDSS = 200 V
Fast switching
Low thermal resistance ID = 39 A
RDS(ON) ≤ 57 mΩ
GENERAL DESCRIPTION
SiliconMAX products use the latest Philips Trench technologyto achieve the lowest possible on-state resistancein
each packageat each voltage rating.
Applications:- d.c.to d.c. converters switched mode power supplies
The PSMN057-200Bis suppliedin the SOT404(D2 PAK) surface mounted package.
PINNING - SOT404 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION gate drain
(no connection possible) source drain
LIMITING VALUESLimiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNITVDSS Drain-source voltage Tj = 25 ˚C to 175˚C - 200 V
VDGR Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ - 200 V
VGS Gate-source voltage - ± 20 V Continuous drain current Tmb = 25 ˚C - 39 A
Tmb = 100 ˚C - 27.5 A
IDM Pulsed drain current Tmb = 25 ˚C - 156 A Total power dissipation Tmb = 25 ˚C - 250 W
Tj, Tstg Operating junction and - 55 175 ˚C
storage temperature13
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN057-200B
AVALANCHE ENERGY LIMITING VALUESLimiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNITEAS Non-repetitive avalanche Unclamped inductive load, IAS = 35 A; - 300 mJ
energy tp = 100 μs; Tj prior to avalanche = 25˚C;
VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V;
IAS Non-repetitive avalanche - 35 A
current
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNITRth j-mb Thermal resistance junction - 0.6 K/W
to mounting base
Rth j-a Thermal resistance junction Minimum footprint, FR4 board 50 - K/W
to ambient
ELECTRICAL CHARACTERISTICSTj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITV(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 200 - - V
voltage Tj = -55˚C 178 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 2.0 3.0 4.0 V
Tj = 175˚C 1.0 - - Vj = -55˚C - - 6 V DS(ON) Drain-source on-state VGS = 10 V; ID = 17 A - 41 57 mΩ
resistance Tj = 175˚C - - 165 mΩ
IGSS Gate source leakage current VGS = ±10 V; VDS = 0 V - 2 100 nA
IDSS Zero gate voltage drain VDS = 200 V; VGS = 0 V; - 0.03 10 μA
current Tj = 175˚C - - 500 μA
Qg(tot) Total gate charge ID = 39 A; VDD = 160 V; VGS = 10 V - 96 - nC
Qgs Gate-source charge - 13 - nC
Qgd Gate-drain (Miller) charge - 37 50 nC
td on Turn-on delay time VDD = 100 V; RD = 2.7 Ω; - 18 - ns Turn-on rise time VGS = 10 V; RG = 5.6 Ω -58 - ns
td off Turn-off delay time Resistive load - 105 - ns Turn-off fall time - 78 - ns Internal drain inductance Measured from tab to centre of die - 3.5 - nH Internal source inductance Measured from source lead to source - 7.5 - nH
bond pad
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 3750 - pF
Coss Output capacitance - 385 - pF
Crss Feedback capacitance - 180 - pF
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN057-200B
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICSTj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Continuous source current - - 39 A
(body diode)
ISM Pulsed source current (body - - 156 A
diode)
VSD Diode forward voltage IF = 25 A; VGS = 0 V - 0.85 1.2 V
trr Reverse recovery time IF = 20 A; -dIF/dt = 100 A/μs; - 133 - ns
Qrr Reverse recovery charge VGS = 0 V; VR = 30 V - 895 - nC
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN057-200B
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); VGS ≥ 10 V
Fig.3. Safe operating area
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS)
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
Normalised Power Derating, PD (%)
100 25 50 75 100 125 150 175
Mounting Base temperature, Tmb (C)
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00
Pulse width, tp (s)
Transient thermal impedance, Zth j-mb (K/W)
Normalised Current Derating, ID (%)
100 25 50 75 100 125 150 175
Mounting Base temperature, Tmb (C) 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
1000 10 100 1000Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
0.14 5 10 15 20 25 30 35 40 45 50Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN057-200B
Fig.7. Typical transfer characteristics.
ID = f(VGS)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
Fig.9. Normalised drain-source on-state resistance.
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C
Fig.12. Typical capacitances, Ciss, Coss, Crss.
234 56
Gate-source voltage, VGS (V)
Drain current, ID (A)
Threshold Voltage, VGS(TO) (V)
-60 -40 -200 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C) 5 10 15 20 25 30 35 40
Drain current, ID (A)
Transconductance, gfs (S)
Drain current, ID (A)
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Gate-source voltage, VGS (V)
Normalised On-state Resistance
-60 -40 -200 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
0.1 1 10 100
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN057-200B
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tAV);
unclamped inductive load
10 20 30 40 50 60 70 80 90 100 110 120 130 140
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
0.001 0.01 0.1 1 10
Avalanche time, tAV (ms)
Maximum Avalanche Current, IAS (A) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.91 1.1 1.2
Source-Drain Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
