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PSMN017-30BL |PSMN01730BLNXP/PHN/a10000avaiN-channel 30 V 17 m鈩?logic level MOSFET in D2PAK


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PSMN017-30BL
N-channel 30 V 17 m鈩?logic level MOSFET in D2PAK
Product profile1.1 General description
Logic level N-channel MOSFET in D2PAK package qualified to 175 °C. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses Suitable for logic level gate drive
sources
1.3 Applications
DC-to-DC converters Load switching Motor control Server power supplies
1.4 Quick reference data

[1] Continuous current is limited by package.
PSMN017-30BL
N-channel 30 V 17 mΩ logic level MOSFET in D2PAK
Rev. 2 — 3 April 2012 Product data sheet
Table 1. Quick reference data

VDS drain-source voltage Tj≥25 °C; Tj≤ 175°C --30 V drain current Tmb =25°C; VGS=10 V; see Figure 1 [1] --32 A
Ptot total power dissipation Tmb=25 °C; see Figure 2 --47 W junction temperature -55 - 175 °C
Static characteristics

RDSon drain-source on-state resistance VGS =4.5 V; ID =10A; Tj =25 °C; see Figure 13 - 18.6 23.3 mΩ
VGS =10V; ID =10 A; Tj =25°C;
see Figure 13 13.3 17 mΩ
Dynamic characteristics

QGD gate-drain charge VGS =4.5 V; ID =10A; VDS =15V;
see Figure 14; see Figure 15
-1.94 -nC
QG(tot) total gate charge - 5.1 - nC
Avalanche ruggedness

EDS(AL)S non-repetitive drain-source
avalanche energy
VGS =10V; Tj(init) =25°C; ID =32A;
Vsup≤30 V; RGS =50 Ω; unclamped
--13 mJ
NXP Semiconductors PSMN017-30BL
N-channel 30 V 17 mΩ logic level MOSFET in D2PAK Pinning information
Ordering information Limiting values
[1] Continuous current is limited by package.
Table 2. Pinning information
Table 3. Ordering information

PSMN017-30BL D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads
(one lead cropped)
SOT404
Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage Tj≥25 °C; Tj≤ 175°C - 30 V
VDGR drain-gate voltage Tj≥25 °C; Tj≤ 175 °C; RGS =20kΩ -30 V
VGS gate-source voltage -20 20 V drain current VGS =10V; Tmb =100 °C; see Figure 1 [1] - 25.5 A
VGS =10V; Tmb=25 °C; see Figure 1 [1] -32 A
IDM peak drain current pulsed; tp≤10 µs; Tmb =25°C;
see Figure 3 154 A
Ptot total power dissipation Tmb=25 °C; see Figure 2 -47 W
Tstg storage temperature -55 175 °C junction temperature -55 175 °C
Source-drain diode
source current Tmb =25°C - 32 A
ISM peak source current pulsed; tp≤10 µs; Tmb=25°C - 154 A
Avalanche ruggedness

EDS(AL)S non-repetitive drain-source
avalanche energy
VGS =10V; Tj(init) =25°C; ID =32A;
Vsup≤30 V; RGS =50 Ω; unclamped
-13 mJ
NXP Semiconductors PSMN017-30BL
N-channel 30 V 17 mΩ logic level MOSFET in D2PAK
NXP Semiconductors PSMN017-30BL
N-channel 30 V 17 mΩ logic level MOSFET in D2PAK Thermal characteristics

Table 5. Thermal characteristics

Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - 3.18 3.2 K/W
Rth(j-a) thermal resistance from junction to ambient - 50 - K/W
NXP Semiconductors PSMN017-30BL
N-channel 30 V 17 mΩ logic level MOSFET in D2PAK Characteristics
Table 6. Characteristics
Static characteristics

V(BR)DSS drain-source breakdown
voltage= 250 µA; VGS =0V; Tj=25°C 30 --V= 250 µA; VGS =0V; Tj= -55°C 27 - - V
VGS(th) gate-source threshold voltage ID =1mA; VDS =VGS; Tj =25°C;
see Figure 10; see Figure 11
1.3 1.7 2.15 V =1mA; VDS =VGS; Tj =175 °C;
see Figure 11
0.5 --V =1mA; VDS =VGS; Tj =-55 °C;
see Figure 11
--2.45 V
IDSS drain leakage current VDS =30V; VGS =0V; Tj=25°C - 0.3 1 µA
VDS =30V; VGS =0V; Tj= 125°C - - 50 µA
IGSS gate leakage current VGS =16 V; VDS =0V; Tj=25°C - 10 100 nA
VGS =-16 V; VDS =0V; Tj=25°C - 10 100 nA
RDSon drain-source on-state
resistance
VGS =4.5 V; ID =10A; Tj =175 °C;
see Figure 12
--43 mΩ
VGS =4.5 V; ID =10A; Tj =25°C;
see Figure 13 18.6 23.3 mΩ
VGS =10 V; ID =10A; Tj =175 °C;
see Figure 12 24 31.5 mΩ
VGS =10 V; ID =10A; Tj =100 °C;
see Figure 12 - 23.5 mΩ
VGS =10 V; ID =10A; Tj =25°C;
see Figure 13 13.3 17 mΩ gate resistance f=1 MHz - 2.03 - Ω
Dynamic characteristics

QG(tot) total gate charge ID =10A; VDS =15V; VGS =10V;
see Figure 14; see Figure 15 10.7 - nC =0A; VDS =0V; VGS =10V;
see Figure 14; see Figure 15
-9.55 -nC =10A; VDS =15V; VGS =4.5V;
see Figure 14; see Figure 15
-5.1 -nC
QGS gate-source charge - 1.52 - nC
QGS(th) pre-threshold gate-source
charge -nC
QGS(th-pl) post-threshold gate-source
charge
-0.5 -nC
QGD gate-drain charge - 1.94 - nC
VGS(pl) gate-source plateau voltage ID =10A; VDS=15 V; see Figure 14;
see Figure 15
-2.86 -V
Ciss input capacitance VDS =15V; VGS =0V; f=1MHz; =25 °C; see Figure 16 552 - pF
Coss output capacitance - 127 - pF
Crss reverse transfer capacitance - 64 - pF
NXP Semiconductors PSMN017-30BL
N-channel 30 V 17 mΩ logic level MOSFET in D2PAK

td(on) turn-on delay time VDS =15V; RL =1.5 Ω; VGS =4.5V;
RG(ext) =5Ω 10.7 - ns rise time - 9.2 - ns
td(off) turn-off delay time - 11.4 - ns fall time - 5.1 - ns
Source-drain diode

VSD source-drain voltage IS =10 A; VGS =0V; Tj =25°C;
see Figure 17 0.89 1.2 V
trr reverse recovery time IS =10 A; dIS/dt= -100 A/µs;
VGS =0V; VDS =15V 17.3 - ns recovered charge - 6.5 - nC
Table 6. Characteristics …continued
NXP Semiconductors PSMN017-30BL
N-channel 30 V 17 mΩ logic level MOSFET in D2PAK
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