PSD913F2-90M ,Flash In-System Programmable ISP Peripherals For 8-bit MCUsTable of ContentsPower Management.....54Automatic Power Down (APD) Unit and Power Down Mode 54Other ..
PSD913F2-90M ,Flash In-System Programmable ISP Peripherals For 8-bit MCUsBlock Diagram ......4PSD9XX Family....5Architectural Overview...6Memory........6Page Register ..... ..
PSD913F2V-15J ,Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 150nsAbsolute Maximum Ratings..62Operating Range 62Recommended Operating Conditions ....62AC/DC Paramete ..
PSD913F2V-15M ,Flash In-System Programmable ISP Peripherals For 8-bit MCUsBlock Diagram ......4PSD9XX Family....5Architectural Overview...6Memory........6Page Register ..... ..
PSD913F2V-20MI ,Flash In-System Programmable ISP Peripherals For 8-bit MCUsFeatures ........3
PSD934F2-15J , Flash In-System Programmable ISP Peripherals For 8-bit MCUs
QL16X24B-1PL84C , pASIC 1 Family Very-High-Speed CMOS FPGA
QL16X24B-1PL84C , pASIC 1 Family Very-High-Speed CMOS FPGA
QL2003-1PF144C , 3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility
QL2003-1PF144C , 3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility
QL2007-0PF144C , 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility
QL2007-0PF144C , 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility
PSD913F1-15J-PSD913F1-90J-PSD913F1-90JI-PSD913F1-90M-PSD913F2-15J-PSD913F2-15M-PSD913F2-70J-PSD913F2-90J-PSD913F2-90JI-PSD913F2-90M-PSD913F2V-15J-PSD913F2V-15M-PSD913F2V-20MI-PSD934F2-70J-PSD934F2-90J-PSD934F2-90M-PSD934F2V-15J-PSD934F2V-15M-PSD954F2-90MI
Flash In-System Programmable ISP Peripherals For 8-bit MCUs
1/3
PRELIMINARY DATAJanuary 2002
PSD913F2
PSD934F2 PSD954F2Flash In-System Programmable (ISP) Peripherals
For 8-bit MCUs
FEATURES SUMMARY Single Supply Voltage:5 V±10% for PSD9xxF2 3.3 V±10% for PSD9xxF2-V Up to 2Mbit of Primary Flash Memory (8 uniform
sectors) 256Kbit Secondary Flash Memory (4 uniform
sectors) Up to 256Kbit SRAM Over 2,000 Gates of PLD: DPLD 27 Reconfigurable I/O ports Enhanced JTAG Serial Port Programmable power management High Endurance: 100,000 Erase/Write Cycles of Flash Memory 1,000 Erase/Write Cycles of PLD
Figure 1. Packages
PSD9XX Family
PSD913F2 PSD934F2 PSD954F2
Configurable Memory System on a Chip for 8-Bit Microcontrollers
Table of ContentsIntroduction....................................................................................................................................................................1
In-System Programming (ISP) JTAG....................................................................................................................2
In-Application Programming (IAP) ........................................................................................................................2
Key Features .................................................................................................................................................................3
Block Diagram...............................................................................................................................................................4
PSD9XX Family.............................................................................................................................................................5
Architectural Overview...................................................................................................................................................6
Memory.................................................................................................................................................................6
Page Register.......................................................................................................................................................6
PLDs .....................................................................................................................................................................6
I/O Ports................................................................................................................................................................7
Microcontroller Bus Interface................................................................................................................................7
JTAG Port .............................................................................................................................................................7
In-System Programming .......................................................................................................................................8
Power Management Unit ......................................................................................................................................8
Development System ....................................................................................................................................................9
Pin Descriptions...........................................................................................................................................................10
Register Description and Address Offset ....................................................................................................................14
Functional Blocks ........................................................................................................................................................15
Memory Blocks ...................................................................................................................................................15
Main Flash and Secondary Flash Memory Description.................................................................................15
SRAM............................................................................................................................................................27
Memory Chip Selects....................................................................................................................................27
Page Register ...............................................................................................................................................30
PLDs ...................................................................................................................................................................31
Decode PLD (DPLD).....................................................................................................................................33
General Purpose PLD (GPLD)......................................................................................................................33
Microcontroller Bus Interface..............................................................................................................................35
Interface to a Multiplexed 8-bit Bus...............................................................................................................35
Interface to a Non-multiplexed 8-bit Bus.......................................................................................................35
Microcontroller Interface Examples...............................................................................................................37
I/O Ports..............................................................................................................................................................42
General Port Architecture..............................................................................................................................42
Port Operating Modes...................................................................................................................................44
Port Configuration Registers (PCRs)............................................................................................................47
Port Data Registers.......................................................................................................................................49
Ports A and B – Functionality and Structure .................................................................................................49
Port C – Functionality and Structure .............................................................................................................51
Port D – Functionality and Structure .............................................................................................................51
PSD9XX Family
PSD913F2 PSD934F2 PSD954F2
Configurable Memory System on a Chip for 8-Bit Microcontrollers
Table of ContentsPower Management............................................................................................................................................54
Automatic Power Down (APD) Unit and Power Down Mode........................................................................54
Other Power Savings Options.......................................................................................................................58
Reset and Power On Requirement ...............................................................................................................59
Programming In-Circuit using the JTAG Interface ..............................................................................................60
Standard JTAG Signals.................................................................................................................................61
JTAG Extensions ..........................................................................................................................................61
Security and Flash Memories Protection ......................................................................................................61
Absolute Maximum Ratings.........................................................................................................................................62
Operating Range .........................................................................................................................................................62
Recommended Operating Conditions .........................................................................................................................62
AC/DC Parameters......................................................................................................................................................63
Example of Typical Power Calculation at Vcc = 5..0 V .......................................................................................64
Example of Typical Power Calculation at Vcc = 5..0 V in Turbo Off Mode.........................................................65
DC Characteristics (5 V ± 10% versions) ....................................................................................................................66
Microcontroller Interface – AC/DC Parameters (5 V ± 10% versions).........................................................................67
Read Timing .......................................................................................................................................................68
Write Timing........................................................................................................................................................69
PLD Combinatorial Timing..................................................................................................................................69
Power Down Timing............................................................................................................................................70
Vstbyon Timing ...................................................................................................................................................70
Reset Pin Timing ................................................................................................................................................70
Flash Program, Write and Erase Times..............................................................................................................71
ISC Timing..........................................................................................................................................................71
PSD9XXFV DC Characteristics (3.0 V to 3.6 V Versions) Advance Information.......................................................72
Microcontroller Interface – AC/DC Parameters (3 V versions)....................................................................................73
Read Timing (3 V versions) ................................................................................................................................73
Write Timing (3 V versions) ................................................................................................................................74
PLD Combinatorial Timing (3 V versions)...........................................................................................................74
Power Down Timing (3 V Versions) ..................................................................................................................75
Vstbyon Timing (3 V Versions) .........................................................................................................................75
Reset Pin Timing (3 V Versions).......................................................................................................................75
Flash Program, Write and Erase Times (3 V Versions)....................................................................................76
ISC Timing (3 V Versions) ................................................................................................................................76
PSD9XX Family
PSD913F2 PSD934F2 PSD954F2
Configurable Memory System on a Chip for 8-Bit Microcontrollers
Table of ContentsTiming Diagrams .........................................................................................................................................................77
Pin Capacitance ..........................................................................................................................................................81
AC Testing Input/Output Waveforms...........................................................................................................................81
AC Testing Load Circuit...............................................................................................................................................81
Programming...............................................................................................................................................................81
Pin Assignments..........................................................................................................................................................82
Package Information....................................................................................................................................................84
Selector Guide.............................................................................................................................................................87
Part Number Construction...........................................................................................................................................87
Ordering Information....................................................................................................................................................88
Document Revisions....................................................................................................................................................89
1.0
Introduction
Preliminary Information
PSD913F2, PSD934F2,
PSD954F2
Configurable Memory System
on a Chip for 8-Bit MicrocontrollersThe PSD9XX family of Programmable System Devices (for 8-bit microcontrollers) brings
In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a
simple and flexible solution for embedded designs. PSD9XX devices combine many of the
peripheral functions found in MCU based applications: Up to 2 Mbit of Flash memory A secondary 256 Kbit Flash memory Over 2,000 gates of Flash programmable logic Up to 256 Kbit SRAM Reconfigurable I/O ports Programmable power management.
PSD9XX Family Preliminary Information
Introduction
(Cont.)The PSD9XX family offers two methods to program PSD Flash memory while the PSD is
soldered to a circuit board.
In-System Programming (ISP) JTAGAn IEEE 1149.1 compliant JTAG interface is included on the PSD enabling the entire
device (both flash memories, the PLD, and all configuration) to be rapidly programmed
while soldered to the circuit board. This requires no MCU participation, which means
the PSD can be programmed anytime, even while completely blank.
The innovative JTAG interface to flash memories is an industry first, solving key
problems faced by designers and manufacturing houses, such as:
First time programming – How do I get firmware into the flash the very first timeJTAG is the answer, program the PSD while blank with no MCU involvement.
Inventory build-up of pre-programmed devices – How do I maintain an accuratecount of pre-programmed flash memory and PLD devices based on customer
demand How many and what version JTAG is the answer, build your hardware
with blank PSDs soldered directly to the board and then custom program just before
they are shipped to customer. No more labels on chips and no more wasted
inventory.
Expensive sockets – How do I eliminate the need for expensive and unreliable sockets JTAG is the answer. Solder the PSD directly to the circuit board. Program
first time and subsequent times with JTAG. No need to handle devices and bend the
fragile leads.
In-Application Programming (IAP)Two independent flash memory arrays are included so the MCU can execute code
from one memory while erasing and programming the other. Robust product firmware
updates in the field are possible over any communication channel (CAN, Ethernet,
UART, J1850, etc) using this unique architecture. Designers are relieved of these
problems:
Simultaneous read and write to flash memory – How can the MCU program the same memory from which it is executing code It cannot. The PSD allows the MCU
to operate the two flash memories concurrently, reading code from one while erasing
and programming the other during IAP.
Complex memory mapping – I have only a 64K-byte address space to start with.How can I map these two memories efficiently A Programmable Decode PLD is the
answer. The concurrent PSD memories can be mapped anywhere in MCU address
space, segment by segment with extremely high address resolution. As an option,
the secondary flash memory can be swapped out of the system memory map when
IAP is complete. A built-in page register breaks the 64K-byte address limit.
Separate program and data space – How can I write to flash memory while it resides in “program” space during field firmware updates, my MCU won’t allow it!
The flash PSD provides means to “reclassify” flash memory as “data” space during
IAP, then back to “program” space when complete.
PSDsoft Express – ST’s software development tool – guides you through the design
process step-by-step making it possible to complete an embedded MCU design capable of
ISP/IAP in just hours. Select your MCU and PSDsoft Express will take you through the
remainder of the design with point and click entry, covering...PSD selection, pin definitions,
programmable logic inputs and outputs, MCU memory map definition, ANSI C code gener-
ation for your MCU, and merging your MCU firmware with the PSD design. When com-
plete, two different device programmers are supported directly from PSDsoft – FlashLINK
(JTAG) and PSDpro.
The PSD9XX is available in 52-pin PLCC and PQFP packages as well as a 64-pin TQFP
Preliminary Information PSD9XX Family A simple interface to 8-bit microcontrollers that use either multiplexed or
non-multiplexed busses. The bus interface logic uses the control signals generated by
the microcontroller automatically when the address is decoded and a read or write is
performed. A partial list of the MCU families supported include: Intel 8031, 80196, 80186, 80C251 Motorola 68HC11, 68HC16, 68HC12, and 683XX Philips 8031 and 8051XA Zilog Z80, Z8, and Z180 Internal 1 or 2 Mbit flash memory. This is the main Flash memory. It is divided into
eight equal-sized blocks that can be accessed with user-specified addresses. Internal secondary 256 Kbit Flash memory. It is divided into four equal-sized
blocks that can be accessed with user-specified addresses. This secondary memory
brings the ability to execute code and update the main Flash concurrently. 16, 64 or 256 Kbit SRAM. The SRAM’s contents can be protected from a
power failure by connecting an external battery. General Purpose PLD (GPLD) with 19 outputs. The GPLD may be used to implement
external chip selects or combinatorial logic function. Decode PLD (DPLD) that decodes address for selection of internal memory blocks. 27 individually configurable I/O port pins that can be used for the following functions: MCU I/Os PLD I/Os Latched MCU address output Special function I/Os. 16 of the I/O ports may be configured as open-drain outputs. Standby current as low as 50 µA for 5 V devices. Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the
field. Internal page register that can be used to expand the microcontroller address space by
a factor of 256. Internal programmable Power Management Unit (PMU) that supports a low power
mode called Power Down Mode. The PMU can automatically detect a lack of
microcontroller activity and put the PSD9XX into Power Down Mode. Erase/Write cycles: Flash memory – 100,000 minimum PLD – 1,000 minimum Data Retention: 15 years
Key Features
PSD9XX Family Preliminary Information
Figure 1. PSD9XX Block Diagram
Preliminary Information PSD9XX Family
PSD9XX
FamilyThere are 2 variants in the PSD9XX family. All PSD9XX devices provide these base
features: 1 or 2 Mbit main Flash Memory, JTAG port, GPLD, DPLD, power management,
and 27 I/O pins. The following table summarizes all the devices in the PSD9XX family.
Additional devices will be introduced.
Table 1. PSD9XX Product Matrix
PSD9XX Family Preliminary InformationPSD9XX devices contain several major functional blocks. Figure 1 shows the
architecture of the PSD9XX device family. The functions of each block are described
briefly in the following sections. Many of the blocks perform multiple functions and are
user configurable.
5.1 MemoryThe PSD9XX contains the following memories: A 1 or 2 Mbit Flash A secondary 256 Kbit Flash memory 16, 64 or 256 Kbit SRAM.
Each of the memories is briefly discussed in the following paragraphs. A more detailed
discussion can be found in section 9.
The 1 or 2 Mbit Flash is the main memory of the PSD9XX. It is divided into eight
equally-sized sectors that are individually selectable.
The 256 Kbit secondary Flash memory is divided into four equally-sized sectors. Each
sector is individually selectable. This memory can hold boot code or data.
The SRAM is intended for use as a scratchpad memory or as an extension to the
microcontroller SRAM. If an external battery is connected to the PSD9XX’s Vstby pin, data
will be retained in the event of a power failure.
Each block of memory can be located in a different address space as defined by the user.
The access times for all memory types includes the address latching and DPLD decoding
time.
5.2 Page RegisterThe eight-bit Page Register expands the address range of the microcontroller by up to
256 times.The paged address can be used as part of the address space to access
external memory and peripherals or internal memory and I/O. The Page Register can also
be used to change the address mapping of blocks of Flash memory into different memory
spaces IAP.
5.3 PLDsThe device contains two combinatorial PLD blocks, each optimized for a different function,
as shown in Table 2. The functional partitioning of the PLDs reduces power consumption,
optimizes cost/performance, and eases design entry.
The Decode PLD (DPLD) is used to decode addresses and generate chip selects for the
PSD9XX internal memory and registers. The General Purpose PLD (GPLD) can
implement user-defined external chip selects and logic functions. The PLDs receive their
inputs from the PLD Input Bus and are differentiated by their output destinations, number
of Product Terms.
The PLDs consume minimal power by using Zero-Power design techniques. The speed
and power consumption of the PLD is controlled by the Turbo Bit in the PMMR0 register
and other bits in the PMMR2 registers. These registers are set by the microcontroller at
runtime. There is a slight penalty to PLD propagation time when invoking the non-Turbo
bit.
5.0
PSD9XX
Architectural
Overview
Table 2. PLD I/O Table
Preliminary Information PSD9XX Family
PSD9XX
Architectural
Overview
(cont.)
5.4 I/O PortsThe PSD9XX has 27 I/O pins divided among four ports (Port A, B, C, and D). Each
I/O pin can be individually configured for different functions. Ports A, B, C and D can
be configured as standard MCU I/O ports, PLD I/O, or latched address outputs for
microcontrollers using multiplexed address/data busses.
The JTAG pins can be enabled on Port C for In-System Programming (ISP).
Port A can also be configured as a data port for a non-multiplexed bus.
5.5 Microcontroller Bus InterfaceThe PSD9XX easily interfaces with most 8-bit microcontrollers that have either
multiplexed or non-multiplexed address/data busses. The device is configured to respond
to the microcontroller’s control signals, which are also used as inputs to the PLDs. Section
9.3.5 contains microcontroller interface examples.
5.6 JTAG PortIn-System Programming can be performed through the JTAG pins on Port C. This serial
interface allows complete programming of the entire PSD9XX device. A blank device can
be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) are
enabled on Port C when selected or when a device is blank. Table 3 indicates the JTAG
signals pin assignments.
Table 3. JTAG Signals on Port C
PSD9XX Family Preliminary Information
5.7 In-System ProgrammingUsing the JTAG signals on Port C, the entire PSD9XX device can be programmed or
erased without the use of the microcontroller (ISP). The main Flash memory can also be
programmed in-system by the microcontroller executing the programming algorithms out of
the Secondary Flash memory, or SRAM (IAP). The Secondary Flash memory can be
programmed the same way by executing out of the main Flash memory. The PLD logic
or other PSD9XX configuration can be programmed through the JTAG port or a device
programmer. Table 4 indicates which programming methods can program different
functional blocks of the PSD9XX.
PSD9XX
Architectural
Overview
(cont.)
Table 4. Methods of Programming Different Functional Blocks of the PSD9XX
5.8 Power Management UnitThe Power Management Unit (PMU) in the PSD9XX gives the user control of the power
consumption on selected functional blocks based on system requirements. The PMU
includes an Automatic Power Down unit (APD) that will turn off device functions due to
microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce power
consumption.
The PSD9XX also has some bits that are configured at run-time by the MCU to reduce
power consumption of the PLD. The turbo bit in the PMMR0 register can be turned off and
the PLD will latch its outputs and go to sleep until the next transition on its inputs.
Additionally, bits in the PMMR2 register can be set by the MCU to block signals from
entering the PLD to reduce power consumption. See section 9.5.
Preliminary Information PSD9XX Family
Figure 2. PSDsoft Development Tools
Development
SystemThe PSD9XX family is supported by PSDsoft Express, a Windows-based (95, 98, NT)
software development tool. A PSD design is quickly and easily produced in a point and
click environment. The designer does not need to enter Hardware Definition Language
(HDL) equations to define PSD pin functions and memory map information. The general
design flow is shown in Figure 2 below. PSDsoft Express is available free from our web
site (www.psdst.com) or the Literature CD.
PSDsoft Express directly supports two low cost device programmers from ST, PSDpro
and FlashLINK (JTAG). Both of these programmers may be purchased through your
local rep/distributor, or directly from our web site using a credit card. The PSD9XX is also
supported by third party device programmers, see web site for current list.
PSD9XX Family Preliminary InformationThe following table describes the pin names and pin functions of the PSD9XX. Pins that
have multiple names and/or functions are defined using PSDsoft.
7.0
Table 5.
PSD9XX
Pin
Descriptions
Preliminary Information PSD9XX Family
Table 5.
PSD9XX
Pin
Descriptions
(cont.)
PSD9XX Family Preliminary Information
Table 5.
PSD9XX
Pin
Descriptions
(cont.)
Preliminary Information PSD9XX Family
Table 5.
PSD9XX
Pin
Descriptions
(cont.)
Table 6. I/O Port Latched Address Output Assignments*N/A = Not Applicable
**Refer to the I/O Port Section on how to enable the Latched Address Output function.
*The pin numbers in this table are for the PLCC package only. See the package information section for pin
numbers on other package types.
PSD9XX Family Preliminary InformationTable 7 shows the offset addresses to the PSD9XX registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD9XX registers. Table 7 provides brief descriptions of the registers in CSIOP
space. For a more detailed description, refer to section 9.
PSD9XX
Register
Description
and Address
Offset
Table 7. Register Address Offset*Other registers that are not part of the I/O ports.
Preliminary Information PSD9XX Family
The
PSD9XX
Functional
BlocksAs shown in Figure 1, the PSD9XX consists of six major types of functional blocks:
Memory Blocks PLD Blocks Bus Interface I/O Ports Power Management Unit JTAG InterfaceThe functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable.
9.1 Memory BlocksThe PSD9XX has the following memory blocks: The main Flash memory Secondary Flash memory SRAM.
The memory select signals for these blocks originate from the Decode PLD (DPLD) and
are user-defined in PSDsoft.
Table 8 summarizes which versions of the PSD9XX contain which memory blocks.
Table 8. Memory Blocks
9.1.1 Main Flash and Secondary Flash Memory DescriptionThe main Flash memory block is divided evenly into eight sectors. The secondary Flash
memory is divided into four sectors of eight Kbytes each. Each sector of either memory
can be separately protected from program and erase operations.
Flash memory may be erased on a sector-by-sector basis and programmed byte-by-byte.
Flash sector erasure may be suspended while data is read from other sectors of memory
and then resumed after reading.
During a program or erase of Flash, the status can be output on the Rdy/Bsy pin of Port
C3. This pin is set up using PSDsoft.
PSD9XX Family Preliminary Information
9.1.1.1 Memory Block SelectsThe decode PLD in the PSD9XX generates the chip selects for all the internal memory
blocks (refer to the PLD section). Each of the eight Flash memory sectors have a
Flash Select signal (FS0-FS7) which can contain up to three product terms. Each of the
four secondary Flash memory sectors have a Select signal (CSBOOT0-3) which can
contain up to three product terms. Having three product terms for each sector select signal
allows a given sector to be mapped in different areas of system memory. When using a
microcontroller with separate Program and Data space, these flexible select signals allow
dynamic re-mapping of sectors from one space to the other when used with the VM
Register (see section 9.1.3.1).
9.1.1.2 The Ready/Busy Pin (PC3)Pin PC3 can be used to output the Ready/Busy status of the PSD9XX. The output on the
pin will be a ‘0’ (Busy) when Flash memory blocks are being written to, or when the Flash
memory block is being erased. The output will be a ‘1’ (Ready) when no write or erase
operation is in progress.
9.1.1.3 Memory OperationThe main Flash and secondary Flash memories are addressed through the microcontroller
interface on the PSD9XX device. The microcontroller can access these memories in one of
two ways: The microcontroller can execute a typical bus write or read operation just as it would
if accessing a RAM or ROM device using standard bus cycles. The microcontroller can execute a specific instruction that consists of several write
and read operations. This involves writing specific data patterns to special addresses
within the Flash to invoke an embedded algorithm. These instructions are summarized
in Table 9.
Typically, Flash memory can be read by the microcontroller using read operations, just
as it would read a ROM device. However, Flash memory can only be erased and
programmed with specific instructions. For example, the microcontroller cannot write a
single byte directly to Flash memory as one would write a byte to RAM. To program a byte
into Flash memory, the microcontroller must execute a program instruction sequence, then
test the status of the programming event. This status test is achieved by a read operation
or polling the Rdy/Busy pin (PC3).
The Flash memory can also be read by using special instructions to retrieve particular
Flash device information (sector protect status and ID).
The
PSD9XX
Functional
Blocks
(cont.)
Preliminary Information PSD9XX Family
The
PSD9XX
Functional
Blocks
(cont.)
9.1.1.3.1 InstructionsAn instruction is defined as a sequence of specific operations. Each received byte is
sequentially decoded by the PSD and not executed as a standard write operation. The
instruction is executed when the correct number of bytes are properly received and the
time between two consecutive bytes is shorter than the time-out value. Some instructions
are structured to include read operations after the initial write operations.
The sequencing of any instruction must be followed exactly. Any invalid combination of
instruction bytes or time-out between two consecutive bytes while addressing Flash
memory will reset the device logic into a read array mode (Flash memory reads like a
ROM device).
The PSD9XX main Flash and Secondary Flash support these instructions (see Table 9): Erase memory by chip or sector Suspend or resume sector erase Program a byte Reset to read array mode Read Main Flash Identifier value Read sector protection status Bypass Instruction (PSD934F2 and PSD954F2 only)
These instructions are detailed in Table 9. For efficient decoding of the instructions, the
first two bytes of an instruction are the coded cycles and are followed by a command byte
or confirmation byte. The coded cycles consist of writing the data AAh to address X555h
during the first cycle and data 55h to address XAAAh during the second cycle. Address
lines A15-A12 are don’t care during the instruction write cycles. However, the appropriate
sector select signal (FSi or CSBOOTi) must be selected.
The main Flash and the Secondary Flash Block have the same set of instructions (except
Read main Flash ID). The chip selects of the Flash memory will determine which Flash will
receive and execute the instruction. The main Flash is selected if any one of the FS0-7 is
active, and the secondary Flash Block is selected if any one of the CSBOOT0-3 is active.
PSD9XX Family Preliminary Information
Table 9. Instructions= Don’t Care.= Address of the memory location to be read.= Data read from location RA during read operation.= Address of the memory location to be programmed. Addresses are latched on the falling edge of the WR#
(CNTL0) pulse.= Data to be programmed at location PA. Data is latched o the rising edge of WR# (CNTL0) pulse.= Address of the sector to be erased or verified. The chip select (FS0-7 or CSBOOT0-3) of the sector to be
erased must be active (high).
NOTES: All bus cycles are write bus cycle except the ones with the “read” label. All values are in hexadecimal. FS0-7 and CSBOOT0-3 are active high and are defined in PSDsoft. Only Address bits A11-A0 are used in Instruction decoding. A15-12 (or A16-A12) are don’t care. No unlock or command cycles required when device is in read mode. The Reset command is required to return to the read mode after reading the Flash ID, Sector Protect status
or if DQ5 (error flag) goes high. Additional sectors to be erased must be entered within 80µs. The data is 00h for an unprotected sector and 01h for a protected sector. In the fourth cycle, the sector chip
select is active and (A1 = 1, A0 = 0). The Unlock Bypass command is required prior to the Unlock Bypass Program command.
10. The Unlock Bypass Reset command is required to return to reading array data when the device is in the
Unlock Bypass mode.
11. The system may read and program functions in non-erasing sectors, read the Flash ID or read the Sector
Protect status, when in the Erase Suspend mode. The erase Suspend command is valid only during a sector
erase operation.
12. The Erase Resume command is valid only during the Erase Suspend mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory for which the
instruction is intended. The MCU must fetch, for example, codes from the secondary block when reading the
Sector Protection Status of the main Flash.
14. Available to PSD934F2 and PSD954F2 devices only.
The
PSD9XX
Functional
Blocks
(cont.)
Preliminary Information PSD9XX Family
The
PSD9XX
Functional
Blocks
(cont.)
9.1.1.4 Power-Up ConditionThe PSD9XX Flash memory is reset upon power-up to the read array mode. The FSi and
CSBOOTi select signals, along with the write strobe signal, must be in the false state
during power-up for maximum security of the data contents and to remove the possibility of
a byte being written on the first edge of a write strobe signal. Any write cycle initiation is
locked when VCC is below VLKO.
9.1.1.5 ReadUnder typical conditions, the microcontroller may read the Flash, or Secondary Flash
memories using read operations just as it would a ROM or RAM device. Alternately, the
microcontoller may use read operations to obtain status information about a program or
erase operation in progress. Lastly, the microcontroller may use instructions to read
special data from these memories. The following sections describe these read functions.
9.1.1.5.1 Read the Contents of MemoryMain Flash and Secondary Flash memories are placed in the read array mode after
power-up, chip reset, or a Reset Flash instruction (see Table 9). The microcontroller can
read the memory contents of main Flash or Secondary Flash by using read operations any
time the read operation is not part of an instruction sequence.
9.1.1.5.2 Read the Main Flash Memory IdentifierThe main Flash memory identifier is read with an instruction composed of 4 operations:
3 specific write operations and a read operation (see Table 9). During the read operation,
address bits A6, A1, and A0 must be 0,0,1, respectively, and the appropriate sector select
signal (FSi) must be active. The PSD9XX main Flash memory ID is E7h (PSD934/954F2)
and E4h (PSD913F2).
9.1.1.5.3 Read the Flash Memory Sector Protection StatusThe Flash memory sector protection status is read with an instruction composed of 4
operations: 3 specific write operations and a read operation (see Table 9). During the read
operation, address bits A6, A1, and A0 must be 0,1,0, respectively, while the chip select
(FSi or CSBOOTi) designates the Flash sector whose protection has to be verified. The
read operation will produce 01h if the Flash sector is protected, or 00h if the sector is not
protected.
The sector protection status for all NVM blocks (main Flash or Secondary Flash) can also
be read by the microcontroller accessing the Flash Protection and Secondary Flash
Protection registers in PSD I/O space. See section 9.1.1.9.1 for register definitions.
9.1.1.5.4 Read the Erase/Program Status BitsThe PSD9XX provides several status bits to be used by the microcontroller to confirm
the completion of an erase or programming instruction of Flash memory. These status bits
minimize the time that the microcontroller spends performing these tasks and are defined
in Table 10. The status bits can be read as many times as needed.
Table 10. Status Bits
NOTES:1. X = Not guaranteed value, can be read either 1 or 0. DQ7-DQ0 represent the Data Bus bits, D7-D0.
3. FSi/CSBOOTi are active high.
For Flash memory, the microcontroller can perform a read operation to obtain these status
bits while an erase or program instruction is being executed by the embedded algorithm.
See section 9.1.1.7 for details.
The
PSD9XX
Functional
Blocks
(cont.)
9.1.1.5.5 Data Polling Flag DQ7When Erasing or Programming the Flash memory bit DQ7 outputs the complement of the
bit being entered for Programming/Writing on DQ7. Once the Program instruction or the
Write operation is completed, the true logic value is read on DQ7 (in a Read operation).
Flash memory specific features: Data Polling is effective after the fourth Write pulse (for programming) or after the
sixth Write pulse (for Erase). It must be performed at the address being programmed
or at an address within the Flash sector being erased. During an Erase instruction, DQ7 outputs a ‘0’. After completion of the instruction,
DQ7 will output the last bit programmed (it is a ‘1’ after erasing). If the byte to be programmed is in a protected Flash sector, the instruction is
ignored. If all the Flash sectors to be erased are protected, DQ7 will be set to ‘0’ for
about 100 µs, and then return to the previous addressed byte. No erasure will be
performed.
9.1.1.5.6 Toggle Flag DQ6The PSD9XX offers another way for determining when the Flash memory Program
instruction is completed. During the internal Write operation and when either the FSi or
CSBOOTi is true, the DQ6 will toggle from ‘0’ to ‘1’ and ‘1’ to ‘0’ on subsequent attempts to
read any byte of the memory.
When the internal cycle is complete, the toggling will stop and the data read on the
Data Bus D0-7 is the addressed memory byte. The device is now accessible for a new
Read or Write operation. The operation is finished when two successive reads yield the
same output data. Flash memory specific features: The Toggle bit is effective after the fourth Write pulse (for programming) or after the
sixth Write pulse (for Erase). If the byte to be programmed belongs to a protected Flash sector, the instruction is
ignored. If all the Flash sectors selected for erasure are protected, DQ6 will toggle to ‘0’ for
about 100 µs and then return to the previous addressed byte.
9.1.1.5.7 Error Flag DQ5During a correct Program or Erase, the Error bit will set to ‘0’. This bit is set to ‘1’ when
there is a failure during Flash byte programming, Sector erase, or Bulk Erase.
In the case of Flash programming, the Error Bit indicates the attempt to program a Flash
bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation.
The Error bit may also indicate a timeout condition while attempting to program a byte.
In case of an error in Flash sector erase or byte program, the Flash sector in which the
error occurred or to which the programmed byte belongs must no longer be used.
Other Flash sectors may still be used. The Error bit resets after the Reset instruction.
9.1.1.5.8 Erase Time-out Flag DQ3The Erase Timer bit reflects the time-out period allowed between two consecutive Sector
Erase instructions. The Erase timer bit is set to ‘0’ after a Sector Erase instruction for a
time period of 100 µs + 20% unless an additional Sector Erase instruction is decoded.
After this time period or when the additional Sector Erase instruction is decoded, DQ3 is
set to ‘1’.
PSD9XX Family Preliminary Information
Preliminary Information PSD9XX Family
9.1.1.6 Programming Flash MemoryFlash memory must be erased prior to being programmed. The MCU may erase Flash
memory all at once or by-sector, but not byte-by-byte. A byte of Flash memory erases to all
logic ones (FF hex), and its bits are programmed to logic zeros. Although erasing Flash
memory occurs on a sector basis, programming Flash memory occurs on a byte basis.
The PSD9XX main Flash and Secondary Flash memories require the MCU to send an
instruction to program a byte or perform an erase function (see Table 9).
Once the MCU issues a Flash memory program or erase instruction, it must check for the
status of completion. The embedded algorithms that are invoked inside the PSD9XX
support several means to provide status to the MCU. Status may be checked using any of
three methods: Data Polling, Data Toggle, or the Ready/Busy output pin.
9.1.1.6.1 Data PollingPolling on DQ7 is a method of checking whether a Program or Erase instruction is in
progress or has completed. Figure 3 shows the Data Polling algorithm.
When the MCU issues a programming instruction, the embedded algorithm within the
PSD9XX begins. The MCU then reads the location of the byte to be programmed in Flash
to check status. Data bit DQ7 of this location becomes the compliment of data bit 7of the
original data byte to be programmed. The MCU continues to poll this location, comparing
DQ7 and monitoring the Error bit on DQ5. When the DQ7 matches data bit 7 of the original
data, and the Error bit at DQ5 remains ‘0’, then the embedded algorithm is complete.
If the Error bit at DQ5 is ‘1’, the MCU should test DQ7 again since DQ7 may have changed
simultaneously with DQ5 (see Figure 3).
The Error bit at DQ5 will be set if either an internal timeout occurred while the embedded
algorithm attempted to program the byte or if the MCU attempted to program a ‘1’ to a bit
that was not erased (not erased is logic ‘0’).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed to compare the byte that was written to Flash with
the byte that was intended to be written.
When using the Data Polling method after an erase instruction, Figure 3 still applies.
However, DQ7 will be ‘0’ until the erase operation is complete. A ‘1’ on DQ5 will indicate
a timeout failure of the erase operation, a ‘0’ indicates no error. The MCU can read any
location within the sector being erased to get DQ7 and DQ5.
PSDsoft will generate ANSI C code functions which implement these Data Polling
algorithms.
The
PSD9XX
Functional
Blocks
(cont.)
PSD9XX Family Preliminary Information
Figure 3. Data Polling Flow Chart
The
PSD9XX
Functional
Blocks
(cont.)
9.1.1.6.2 Data ToggleChecking the Data Toggle bit on DQ6 is a method of determining whether a Program or
Erase instruction is in progress or has completed. Figure 4 shows the Data Toggle
algorithm.
When the MCU issues a programming instruction, the embedded algorithm within the
PSD9XX begins. The MCU then reads the location of the byte to be programmed in
Flash to check status. Data bit DQ6 of this location will toggle each time the MCU reads
this location until the embedded algorithm is complete. The MCU continues to read this
location, checking DQ6 and monitoring the Error bit on DQ5. When DQ6 stops toggling
(two consecutive reads yield the same value), and the Error bit on DQ5 remains ‘0’, then
the embedded algorithm is complete. If the Error bit on DQ5 is ‘1’, the MCU should test
DQ6 again, since DQ6 may have changed simultaneously with DQ5 (see Figure 4).
The Error bit at DQ5 will be set if either an internal timeout occurred while the embedded
algorithm attempted to program the byte, or if the MCU attempted to program a ‘1’ to a bit
that was not erased (not erased is logic ‘0’).
Preliminary Information PSD9XX Family
9.1.1.6.2 Data Toggle (cont.)It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed to compare the byte that was written to Flash with
the byte that was intended to be written.
When using the Data Toggle method after an erase instructin, Figure 4 still applies. DQ6
will toggle until the erase operation is complete. A ‘1’ on DQ5 will indicate a timeout failure
of the erase operation, a ‘0’ indicates no error. The MCU can read any location within the
sector being erased to get DQ6 and DQ5.
PSDsoft will generate ANSI C code functions which implement these Data Toggling
algorithms.
The
PSD9XX
Functional
Blocks
(cont.)
Figure 4. Data Toggle Flow Chart
PSD9XX Family Preliminary Information
The
PSD9XX
Functional
Blocks
(cont.)
9.1.1.7 Unlock Bypass Instruction (PSD934F2 and PSD954F2 only)The unlock bypass feature allows the system to program bytes to the flash memories
faster than using the standard program instruction. The unlock bypass instruction is
initiated by first writing two unlock cycles. This is followed by a third write cycle containing
the unlock bypass command, 20h (see Table 9). The flash memory then enters the unlock
bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required to
program in this mode. The first cycle in this instruction contains the unlock bypass
programm command, A0h; the second cycle contains the program address and data.
Additional data is programmed in the same manner. This mode dispenses with the initial
two unlock cycles requiredc in the standard program instruction, resulting in faster total
programming time. During the unlock bypass mode, only the Unlock Bypass Program and
Unlock Bypass Reset instructions are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset instruction. The first cycle must contain the
data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The
falsh memory then returns to reading array data mode.
9.1.1.8 Erasing Flash Memory
9.1.1.8.1. Flash Bulk Erase InstructionThe Flash Bulk Erase instruction uses six write operations followed by a Read operation of
the status register, as described in Table 9. If any byte of the Bulk Erase instruction is
wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory
status.
During a Bulk Erase, the memory status may be checked by reading status bits DQ5, DQ6,
and DQ7, as detailed in section 9.1.1.6. The Error bit (DQ5) returns a ‘1’ if there has been
an Erase Failure (maximum number of erase cycles have been executed).
It is not necessary to program the array with 00h because the PSD9XX will automatically
do this before erasing to 0FFh.
During execution of the Bulk Erase instruction, the Flash memory will not accept any
instructions.
9.1.1.8.2 Flash Sector Erase InstructionThe Sector Erase instruction uses six write operations, as described in Table 9. Additional
Flash Sector Erase confirm commands and Flash sector addresses can be written
subsequently to erase other Flash sectors in parallel, without further coded cycles, if the
additional instruction is transmitted in a shorter time than the timeout period of about
100 μs. The input of a new Sector Erase instruction will restart the time-out period.
The status of the internal timer can be monitored through the level of DQ3 (Erase time-out
bit). If DQ3 is ‘0’, the Sector Erase instruction has been received and the timeout is
counting. If DQ3 is ‘1’, the timeout has expired and the PSD9XX is busy erasing the Flash
sector(s). Before and during Erase timeout, any instruction other than Erase suspend and
Erase Resume will abort the instruction and reset the device to Read Array mode.
It is not necessary to program the Flash sector with 00h as the PSD9XX will do this
automatically before erasing (byte=FFh).
During a Sector Erase, the memory status may be checked by reading status bits DQ5,
DQ6, and DQ7, as detailed in section 9.1.1.6.
During execution of the erase instruction, the Flash block logic accepts only Reset and
Erase Suspend instructions. Erasure of one Flash sector may be suspended, in order to
read data from another Flash sector, and then resumed.
Preliminary Information PSD9XX Family
The
PSD9XX
Functional
Blocks
(cont.)
9.1.1.8.3 Flash Erase Suspend InstructionWhen a Flash Sector Erase operation is in progress, the Erase Suspend instruction will
suspend the operation by writing 0B0h to any address when an appropriate Chip Select
(FSi or CSBOOTi) is true. (See Table 9). This allows reading of data from another Flash
sector after the Erase operation has been suspended. Erase suspend is accepted only
during the Flash Sector Erase instruction execution and defaults to read array mode. An
Erase Suspend instruction executed during an Erase timeout will, in addition to suspending
the erase, terminate the time out.
The Toggle Bit DQ6 stops toggling when the PSD9XX internal logic is suspended. The
toggle Bit status must be monitored at an address within the Flash sector being erased.
The Toggle Bit will stop toggling between 0.1 μs and 15 μs after the Erase Suspend
instruction has been executed. The PSD9XX will then automatically be set to Read Flash
Block Memory Array mode.
If an Erase Suspend instruction was executed, the following rules apply: Attempting to read from a Flash sector that was being erased will output invalid data. Reading from a Flash sector that was not being erased is valid. The Flash memory cannot be programmed, and will only respond to Erase Resume
and Reset instructions (read is an operation and is OK). If a Reset instruction is received, data in the Flash sector that was being erased will
be invalid.
9.1.1.8.4 Flash Erase Resume InstructionIf an Erase Suspend instruction was previously executed, the erase operation may be
resumed by this instruction. The Erase Resume instruction consists of writing 030h to any
address while an appropriate Chip Select (FSi or CSBOOTi) is true. (See Table 9.)
9.1.1.9 Specific Features
9.1.1.9.1 Flash and Secondary Flash Sector ProtectEach Flash and Secondary Flash sector can be separately protected against Program and
Erase functions. Sector Protection provides additional data security because it disables all
program or erase operations. This mode can be activated through the JTAG Port or a
Device Programmer.
Sector protection can be selected for each sector using the PSDsoft Configuration
program. This will automatically protect selected sectors when the device is programmed
through the JTAG Port or a Device Programmer. Flash sectors can be unprotected to
allow updating of their contents using the JTAG Port or a Device Programmer. The
microcontroller can read (but cannot change) the sector protection bits.
Any attempt to program or erase a protected Flash sector will be ignored by the device.
The Verify operation will result in a read of the protected data. This allows a guarantee of
the retention of the Protection status.
The sector protection status can be read by the MCU through the Flash protection and
Secondary Flash protection registers (CSIOP). See Table 11.
The
PSD9XX
Functional
Blocks
(cont.)
Flash Protection Register
9.1.1.9.2 Reset Instruction – PSD913F2The Reset instruction consists of one write cycle (see Table 9). It can also be optionally
preceded by the standard two write decoding cycles (writing AAh to 555h and 55h to
AAAh).
The Reset instruction must be executed after: Reading the Flash Protection status or Flash ID When an error condition occurs (DQ5 goes high) during a Flash programming or erase
cycle.
The Reset instruction will reset the Flash to normal Read Mode. It may take the Flash
memory up to few msec to complete the reset cycle.
The Reset instruction is ignored when it is issued during a Flash programming or Bulk
Erase cycle. During Sector Erase cycle, the Reset instruction will abort the on going sector
erase cycle and return the Flash to normal Read Mode in up to few msec.
9.1.1.9.3 Reset Instruction – PSD934F2, PSD954F2The Reset instruction consists of one write cycle (see Table 9). It can also be optionally
preceded by the standard two write decoding cycles (writing AAh to 555h and 55h to
AAAh).
The Reset instruction must be executed after: Reading the Flash Protection status or Flash ID When an error condition occurs (DQ5 goes high) during a Flash programming or erase
cycle.
The Reset instruction will immediately reset the Flash to normal Read Mode. However,
if there is an error condition (DQ5 goes high), the Flash memory will return to the Read
Mode in 25 μsec after the Reset instruction is issued.
The Reset instruction is ignored when it is issued during a Flash programming or Bulk
Erase cycle. The Reset instruction will abort the on going sector erase cycle and return the
Flash memory to normal Read Mode in 25 μsec.
Bit Definitions:
Sec_Prot 1 = Main Flash Sector
is write protected.
Sec_Prot 0 = Main Flash Sector is not write protected.
Secondary Flash Protection Register
Bit Definitions:
Sec_Prot 1 = Secondary Flash Sector is write protected.
Sec_Prot 0 = Secondary Flash Sector is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
Table 11. Sector Protection/Security Bit Definition Not used.
PSD9XX Family Preliminary Information
Preliminary Information PSD9XX Family
The
PSD9XX
Functional
Blocks
(cont.)
9.1.1.9.4 Reset Pin Input – PSD934F2, PSD954F2
The reset pulse input from the pin will abort any operation in progress and reset the Flash
memory to Read Mode. When the reset occurs during a programming or erase cycle, the
Flash memory will take up to 25 μsec to return to Read Mode. It is recommended that the
reset pulse (except power on reset, see Reset Section) be at least 25 μSec such that the
Flash memory will always be ready for the MCU to fetch the boot codes after reset is over.
9.1.2 SRAM
The SRAM is enabled when RS0—the SRAM chip select output from the DPLD—is high.
RS0 can contain up to two product terms, allowing flexible memory mapping.
The SRAM can be backed up using an external battery. The external battery should be
connected to the Vstby pin (PC2). If you have an external battery connected to the
PSD9XX, the contents of the SRAM will be retained in the event of a power loss. The
contents of the SRAM will be retained so long as the battery voltage remains at 2V or
greater. If the supply voltage falls below the battery voltage, an internal power switchover
to the battery occurs.
Pin PC4 can be configured as an output that indicates when power is being drawn from the
external battery. This Vbaton signal will be high with the supply voltage falls below the bat-
tery voltage and the battery on PC2 is supplying power to the internal SRAM.
The chip select signal (RS0) for the SRAM, Vstby, and Vbaton are all configured using
PSDsoft.
9.1.3 Memory Select Signals
The main Flash (FSi), Secondary Flash (CSBOOTi), and SRAM (RS0) memory select
signals are all outputs of the DPLD. They are setup by entering equations for them in
PSDsoft. The following rules apply to the equations for the internal chip select signals: Main Flash memory and Secondary Flash memory sector select signals must not be
larger than the physical sector size. Any main Flash memory sector must not be mapped in the same memory space as
another Main Flash sector. A Secondary Flash memory sector must not be mapped in the same memory space as
another Secondary Flash sector. SRAM, I/O, and Peripheral I/O spaces must not overlap. A Secondary Flash memory sector may overlap a main Flash memory sector. In case
of overlap, priority will be given to the Secondary Flash sector. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority
will be given to the SRAM, I/O, or Peripheral I/O.
Example
FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0
will always access the SRAM. Any address in the range of CSBOOT0 greater than 87FFh
(and less than 9FFFh) will automatically address Boot memory segment 0. Any address
greater than 9FFFh will access the Flash memory segment 0. You can see that half of the
Flash memory segment 0 and one-fourth of Boot segment 0 can not be accessed in this
example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to
BFFFh would not be valid.
Figure 5 shows the priority levels for all memory components. Any component on a higher
level can overlap and has priority over any component on a lower level. Components on
the same level must not overlap. Level one has the highest priority and level 3 has the
lowest.
The
PSD9XX
Functional
Blocks
(cont.)
Figure 5. Priority Level of Memory and I/O Components
9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces
The 8031 and compatible family of microcontrollers, which includes the 80C51, 80C151,
80C251, 80C51XA, and the C500 family have separate address spaces for code memory
(selected using PSEN) and data memory (selected using RD). Any of the memories
within the PSD9XX can reside in either space or both spaces. This is controlled through
manipulation of the VM register that resides in the PSD’s CSIOP space.
The VM register is set using PSDsoft to have an initial value. It can subsequently be
changed by the microcontroller so that memory mapping can be changed on-the-fly.
For example, you may wish to have SRAM and Flash in Data Space at boot, and Boot
Block in Program Space at boot, and later swap Boot Block and Flash. This is easily done
with the VM register by using PSDsoft to configure it for boot up and having the microcon-
troller change it when desired.
Table 13 describes the VM Register.
Table 13. VM Register
NOTE: Bits 5-7 are not used, should set to “0”.
PSD9XX Family Preliminary Information
Preliminary Information PSD9XX Family
The
PSD9XX
Functional
Blocks
(cont.)
Figure 6. 8031 Memory Modes – Separate Space Mode
Figure 7. 80C31 Memory Mode – Combined Space Mode
9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces
9.1.3.2.1 Separate Space Modes
Code memory space is separated from data memory space. For example, the PSEN
signal is used to access the program code from the Flash Memory, while the RD signal is
used to access data from the Boot memory, SRAM and I/O Ports. This configuration
requires the VM register to be set to 0Ch.
9.1.3.2.2 . Combined Space Modes
The program and data memory spaces are combined into one space that allows the main
Flash Memory, Boot memory, and SRAM to be accessed by either PSEN or RD. For
example, to configure the main Flash memory in combined space mode, bits 2 and 4 of the
VM register are set to “1”.
9.1.3.3 80C31 Memory Map Example
See Application Note for examples.
Figure 8. Page Register
The
PSD9XX
Functional
Blocks
(cont.)
9.1.4 Page Register
The eight bit Page Register increases the addressing capability of the microcontroller by a
factor of up to 256. The contents of the register can also be read by the microcontroller.
The outputs of the Page Register (PGR0-PGR7) are inputs to the PLD and can be
included in the Flash Memory, Secondary Flash Block, and SRAM chip select equations.
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the PLD for general logic. See Application
Note.
Figure 8 shows the Page Register. The eight flip flops in the register are connected to the
internal data bus D0-D7. The microcontroller can write to or read from the Page Register.
The Page Register can be accessed at address location CSIOP + E0h.
PSD9XX Family Preliminary Information
Preliminary Information PSD9XX Family
The
PSD9XX
Functional
Blocks
(cont.)
9.2 PLDs
The PLDs bring programmable logic functionality to the PSD9XX. After specifying the
chip selects or logic equations for the PLDs in PSDsoft, the logic is programmed into the
device and available upon power-up.
The PSD9XX contains two PLDs: the Decode PLD (DPLD), and the General Purpose PLD
(GPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in
sections 9.2.1 and 9.2.2. Figure 10 shows the configuration of the PLDs.
The DPLD performs address decoding for internal components, such as memory,
registers, and I/O port selects.
The GPLD can be used to generate external chip selects, control signals or logic functions.
The GPLD has 19 outputs that are connected to Ports A, B and D.
The AND array is used to form product terms. These product terms are specified using
PSsoft. An Input Bus consisting of 57 signals is connected to the PLDs. The signals are
shown in Table 15. The complement of the 57 signals are also available as input to the
AND array.
Table 15. DPLD and GPLD Inputs
NOTE: The address inputs are A[19:4] in 80C51XA mode.
The Turbo Bit
The PLDs in the PSD9XX can minimize power consumption by switching off when inputs
remain unchanged for an extended time of about 70 ns. Setting the Turbo mode bit to off
(Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs
are changing. Turbo-off mode increases propagation delays while reducing power
consumption. Refer to the Power Management Unit section on how to set the Turbo Bit.
Additionally, five bits are available in the PMMR2 register to block MCU control signals
from entering the PLDs. This reduces power consumption and can be used only when
these MCU control signals are not used in PLD logic equations.
Figure 9. PLD Block Diagrams
PSD9XX Family Preliminary Information
Figure 10. DPLD Logic Array
Preliminary Information PSD9XX Family
9.2.1 Decode PLD (DPLD)
The DPLD, shown in Figure 10, is used for decoding the address for internal PSD
components. The DPLD can generate the following chip selects: 8 sector selects for the main Flash memory (three product terms each) 4 sector selects for the Secondary Flash memory (three product terms each) 1 internal SRAM select (two product terms) 1 internal CSIOP select (select PSD registers, one product term)
Inputs to the DPLD chip selects may include address inputs, Page Register inputs and
other user defined external inputs from Ports A, B, C or D.
9.2.2 General Purpose PLD (GPLD)
The General Purpose PLD implements user defined system combinatorial logic function
or chip selects for external devices. Figure 11 shows how the GPLD is connected to the
I/O Ports. The GPLD has 19 outputs and each are routed to a port pin. The port pin can
also be configured as input tot eh GPLD. When it is not used as GPLD output or input, the
pin can be configured to perform other I/O functions.
The GPLD outputs are identical except in the number of available product terms for logic
implementation. Select the pin that can best meet the product term requirement of your
logic function or chip selects. The outputs can be configured as active high or low outputs.
Table 16 shows the number of product terms that are assigned to the PLD outputs on the
I/O Ports. When PSD9XX is connected to a MCU with non-multiplexed bus, Port A will be
configured as the Data Port and the GPLD outputs will not be available.
The
PSD9XX
Functional
Blocks
(cont.)
Table 16. GPLD Output Product Term
PSD9XX Family Preliminary Information
Figure 11. General Purpose PLD and I/O Port
Preliminary Information PSD9XX Family
The
PSD9XX
Functional
Blocks
(cont.)
9.3 Microcontroller Bus Interface
The “no-glue logic” PSD9XX Microcontroller Bus Interface can be directly connected to
most popular microcontrollers and their control signals. Key 8-bit microcontrollers with their
bus types and control signals are shown in Table 17. The interface type is specified using
the PSDsoft.
Table 17. Microcontrollers and their Control Signals
**Unused CNTL2 pin can be configured as PLD input. Other unused pins (PC7, PD0, PA3-0) can be
**configured for other I/O functions.
**ALE/AS input is optional for microcontrollers with a non-multiplexed bus
9.3.1. PSD9XX Interface to a Multiplexed 8-Bit Bus
Figure 12 shows an example of a system using a microcontroller with an 8-bit multiplexed
bus and a PSD9XX. The ADIO port on the PSD9XX is connected directly to the
microcontroller address/data bus. ALE latches the address lines internally. Latched
addresses can be brought out to Port A or B. The PSD9XX drives the ADIO data bus only
when one of its internal resources is accessed and the RD input is active. Should the
system address bus exceed sixteen bits, Ports A, B, C, or D may be used as additional
address inputs.
9.3.2. PSD9XX Interface to a Non-Multiplexed 8-Bit Bus
Figure 13 shows an example of a system using a microcontroller with an 8-bit
non-multiplexed bus and a PSD9XX. The address bus is connected to the ADIO Port, and
the data bus is connected to Port A. Port A is in tri-state mode when the PSD9XX is not
accessed by the microcontroller. Should the system address bus exceed sixteen bits, Ports
B, C, or D may be used for additional address inputs.
PSD9XX Family Preliminary Information
The
PSD9XX
Functional
Blocks
(cont.)
Figure 12. An Example of a Typical 8-Bit Multiplexed Bus Interface
Figure 13. An Example of a Typical 8-Bit Non-Multiplexed Bus Interface
Preliminary Information PSD9XX Family
The
PSD9XX
Functional
Blocks
(cont.)
9.3.3 Microcontroller Interface Examples
Figures 14 through 18 show examples of the basic connections between the PSD9XX
and some popular microcontrollers. The PSD9XX Control input pins are labeled as to the
microcontroller function for which they are configured. The MCU interface is specified using
the PSDsoft.
9.3.3.1 80C31
Figure 14 shows the interface to the 80C31, which has an 8-bit multiplexed address/data
bus. The lower address byte is multiplexed with the data bus. The microcontroller control
signals PSEN, RD, and WR may be used for accessing the internal memory components
and I/O Ports. The ALE input (pin PD0) latches the address.
9.3.3.2 80C251
The Intel 80C251 microcontroller features a user-configurable bus interface with four
possible bus configurations, as shown in Table 19.
Configuration 1 is 80C31 compatible, and the bus interface to the PSD9XX is identical to
that shown in Figure 14. Configurations 2 and 3 have the same bus connection as shown
in Figure 15. There is only one read input (PSEN) connected to the Cntl1 pin on the
PSD9XX. The A16 connection to the PA0 pin allows for a larger address input to the
PSD9XX. Configuration 4 is shown in Figure 16. The RD signal is connected to Cntl1 and
the PSEN signal is connected to the CNTL2.
The 80C251 has two major operating modes: Page Mode and Non-Page Mode. In
Non-Page Mode, the data is multiplexed with the lower address byte, and ALE is active in
every bus cycle. In Page Mode, data D[7:0] is multiplexed with address A[15:8]. In a bus
cycle where there is a Page hit, the ALE signal is not active and only addresses A[7:0]
are changing. The PSD9XX supports both modes. In Page Mode, the PSD bus timing
is identical to Non-Page Mode except the address hold time and setup time with respect
to ALE is not required. The PSD access time is measured from address A[7:0] valid to
data in valid.
PSD9XX Family Preliminary Information
The
PSD9XX
Functional
Blocks
(cont.)
Table 19. 80C251 Configurations
9.3.3.3 80C51XA
The Philips 80C51XA microcontroller family supports an 8- or 16-bit multiplexed bus that
can have burst cycles. Address bits A[3:0] are not multiplexed, while A[19:4] are
multiplexed with data bits D[15:0] in 16-bit mode. In 8-bit mode, A[11:4] are multiplexed
with data bits D[7:0].
The 80C51XA can be configured to operate in eight-bit data mode. (shown in Figure 17).
The 80C51XA improves bus throughput and performance by executing Burst cycles for
code fetches. In Burst Mode, address A19-4 are latched internally by the PSD9XX, while
the 80C51XA changes the A3-0 lines to fetch up to 16 bytes of code. The PSD access
time is then measured from address A3-A0 valid to data in valid. The PSD bus timing
requirement in Burst Mode is identical to the normal bus cycle, except the address setup
and hold time with respect to ALE does not apply.
9.3.3.4 68HC11
Figure 18 shows an interface to a 68HC11 where the PSD9XX is configured in 8-bit
multiplexed mode with E and R/W settings. The DPLD can generate the READ and WR
signals for external devices.
Preliminary Information PSD9XX Family
Figure 14. Interfacing the PSD9XX with an 80C31
Figure 15. Interfacing the PSD9XX to the 80C251, with One Read Input
PSD9XX Family Preliminary Information
Figure 16. Interfacing the PSD9XX to the 80C251, with Read and PSEN Inputs
Figure 17. Interfacing the PSD9XX to the 80C51XA, 8-Bit Data Bus
Preliminary Information PSD9XX Family
Figure 18. Interfacing the PSD9XX with a 68HC11 (Muxed Address/Data Bus)
PSD9XX Family Preliminary Information
The
PSD9XX
Functional
Blocks
(cont.)
9.4 I/O Ports
There are four programmable I/O ports: Ports A, B, C, and D. Each of the ports is eight
bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus
allowing multiple functions per port. The ports are configured using PSDsoft or by the
microcontroller writing to on-chip registers in the CSIOP address space.
The topics discussed in this section are: General Port Architecture Port Operating Modes Port Configuration Registers Port Data Registers Individual Port Functionality.
9.4.1 General Port Architecture
The general architecture of the I/O Port is shown in Figure 19. Individual Port architectures
are shown in Figures 20 through 22. In general, once the purpose for a port pin has been
defined, that pin will no longer be available for other purposes. Exceptions will be noted.
As shown in Figure 19, the ports contain an output multiplexer whose selects are driven
by the configuration bits in the Control Registers (Ports A and B only) and PSDsoft. Inputs
to the multiplexer include the following: Output data from the Data Out Register Latched address outputs General Purpose PLD (GPLD) outputs (external chip selects)
The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be
read. The PDB is connected to the Internal Data Bus for feedback and can be read by the
microcontroller. The Data Out, Direction and Control Registers, and port pin input are all
connected to the PDB.
The contents of these registers can be altered by the microcontroller. The PDB feedback
path allows the microcontroller to check the contents of the registers.
Preliminary Information PSD9XX Family
Figure 19. General I/O Port ArchitectureThe
PSD9XX
Functional
Blocks
(cont.)
