PSD835G2V-12UI ,Flash PSD, 3V Supply, for 8-bit MCUs 4Mbit + 256 Kbit Dual Flash Memories and 64Kbit SRAMFEATURES SUMMARY■ FLASH IN-SYSTEM PROGRAMMABLE (ISP) Figure 1. PackagePERIPHERAL FOR 8-BIT MCUs■ DU ..
PSD853F2-90M ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5VPSD813F2, PSD833F2PSD834F2, PSD853F2, PSD854F2Flash In-System Programmable (ISP)Peripherals for 8-b ..
PSD854F2-70M ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5VFEATURES SUMMARY . . . . . 1SUMMARY DESCRIPTION . . . 6PIN DESCRIPTION 10PSD A ..
PSD854F2-90M ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5VPSD813F2, PSD833F2PSD834F2, PSD853F2, PSD854F2Flash In-System Programmable (ISP)Peripherals for 8-b ..
PSD854F2-90MI ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5VFEATURES SUMMARY■ FLASH IN-SYSTEM PROGRAMMABLE (ISP) Figure 1. PackagesPERIPHERAL FOR 8-BIT MCUS■ D ..
PSD854F2V-90M ,Parallel Port Programmer for STs Programmable System Device (PSD) ProductsFEATURES SUMMARY■ LOW COST PARALLEL PORT Figure 1. PSD ProgrammerPROGRAMMER FOR ST'S ENTIRE PSD PRO ..
QL16X24B-1PL84C , pASIC 1 Family Very-High-Speed CMOS FPGA
QL16X24B-1PL84C , pASIC 1 Family Very-High-Speed CMOS FPGA
QL2003-1PF144C , 3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility
QL2003-1PF144C , 3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility
QL2007-0PF144C , 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility
QL2007-0PF144C , 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility
PSD835G2V-12UI
Flash PSD, 3V Supply, for 8-bit MCUs 4Mbit + 256 Kbit Dual Flash Memories and 64Kbit SRAM
1/98
PRELIMINARY DATAMay 2004
PSD835G2VFlash PSD, 3V Supply, for 8-bit MCUs
4Mbit + 256 Kbit Dual Flash Memories and 64Kbit SRAM
FEATURES SUMMARY FLASH IN-SYSTEM PROGRAMMABLE (ISP)
PERIPHERAL FOR 8-BIT MCUs DUAL BANK FLASH MEMORIES 4 Mbits of Primary Flash Memory (8
uniform sectors, 64Kbyte) 256 Kbits of Secondary Flash Memory
with 4 sectors Concurrent operation: READ from one
memory while erasing and writing the
other 64 KBIT OF BATTERY-BACKED SRAM 52 RECONFIGURABLE I/O PORTS ENHANCED JTAG SERIAL PORT PLD WITH MACROCELLS Over 3000 Gates of PLD: CPLD and
DPLD CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs) DPLD - user defined internal chip select
decoding 52 INDIVIDUALLY CONFIGURABLE I/O
PORT PINS
They can be used for the following functions: MCU I/Os
–PLD I/Os Latched MCU address output Special function I/Os. I/O ports may be configured as open-drain
outputs. IN-SYSTEM PROGRAMMING (ISP) WITH
JTAG Built-in JTAG compliant serial port allows
full-chip In-System Programmability Efficient manufacturing allow easy
product testing and programming Use low cost FlashLINK cable with PC PAGE REGISTER Internal page register that can be used to
expand the microcontroller address space
by a factor of 256 PROGRAMMABLE POWER MANAGEMENT
PSD835G2V
TABLE OF CONTENTS
Features Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
In-Application Programming (IAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PSDsoft. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
In-Application re-Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
PSD Register Description and Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
REGISTER BIT DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . .22
Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Upper and Lower Block IN MAIN FLASH SECTOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Memory Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Read Primary Flash Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Read the Erase/Program Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Data Polling Flag (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Toggle Flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Error Flag (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Erase Time-out Flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3/98
PSD835G2V
PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Flash Memory Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Reset (RESET) Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
SECTOR SELECT AND SRAM SELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Memory Select Configuration for MCUs with Separate Program and Data Spaces . . . . . . . .32
Configuration Modes for MCUs with Separate Program and Data Spaces . . . . . . . . . . . . . . .33
PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MEMORY ID REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
External Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
PSD Interface to a Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
PSD Interface to a Non-Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
MCU Bus Interface Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
80C51XA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
PSD835G2V
I/O PORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
General Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Port Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Peripheral I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Drive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
OMC Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Ports A,B and C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Port D – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Port E – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Port F – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Port G – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Power-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Reset of Flash Memory Erase and Program Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
PROGRAMMING IN-CIRCUIT USING THE JTAG/ISP INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . .73
Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
JTAG Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
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AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
AC AND DC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
APPENDIX A.PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
PSD835G2V
SUMMARY DESCRIPTIONThe PSD family of memory systems for microcon-
trollers (MCUs) brings In-System-Programmability
(ISP) to Flash memory and programmable logic.
The result is a simple and flexible solution for em-
bedded designs. PSD devices combine many of
the peripheral functions found in MCU based ap-
plications.
The CPLD in the PSD devices features an opti-
mized macrocell logic architecture. The PSD mac-
rocell was created to address the unique
requirements of embedded system designs. It al-
lows direct connection between the system ad-
dress/data bus, and the internal PSD registers, to
simplify communication between the MCU and
other supporting devices.
The PSD family offers two methods to program the
PSD Flash memory while the PSD is soldered to
the circuit board: In-System Programming (ISP)
via JTAG, and In-Application Programming (IAP).
In-System Programming (ISP) via JTAGAn IEEE 1149.1 compliant JTAG In-System Pro-
gramming (ISP) interface is included on the PSD
enabling the entire device (Flash memories, PLD,
configuration) to be rapidly programmed while sol-
dered to the circuit board. This requires no MCU
participation, which means the PSD can be pro-
grammed anytime, even when completely blank.
The innovative JTAG interface to Flash memories
is an industry first, solving key problems faced by
designers and manufacturing houses, such as:
First time programming. How do I get firmware
into the Flash memory the very first time JTAG is
the answer. Program the blank PSD with no MCU
involvement.
Inventory build-up of pre-programmed devic-
es. How do I maintain an accurate count of pre-
programmed Flash memory and PLD devices
based on customer demand How many and what
version JTAG is the answer. Build your hardware
with blank PSDs soldered directly to the board and
then custom program just before they are shipped
to the customer. No more labels on chips, and no
more wasted inventory.
Expensive sockets. How do I eliminate the need
for expensive and unreliable sockets JTAG is the
answer. Solder the PSD directly to the circuit
board. Program first time and subsequent times
with JTAG. No need to handle devices and bend
the fragile leads.
In-Application Programming (IAP)Two independent Flash memory arrays are includ-
ed so that the MCU can execute code from one
while erasing and programming the other. Robust
product firmware updates in the field are possible
over any communications channel (CAN, Ether-
net, UART, J1850, etc.) using this unique architec-
ture. Designers are relieved of these problems:
Simultaneous read and write to Flash memo-
ry. How can the MCU program the same memory
from which it is executing code It cannot. The
PSD allows the MCU to operate the two Flash
memory blocks concurrently, reading code from
one while erasing and programming the other dur-
ing IAP.
Complex memory mapping. How can I map
these two memories efficiently A programmable
Decode PLD (DPLD) is embedded in the PSD.
The concurrent PSD memories can be mapped
anywhere in MCU address space, segment by
segment with extremely high address resolution.
As an option, the secondary Flash memory can be
swapped out of the system memory map when
IAP is complete. A built-in page register breaks the
MCU address limit.
Separate Program and Data space. How can I
write to Flash memory while it resides in Program
space during field firmware updates My 80C51
will not allow it. The PSD provides means to re-
classify Flash memory as Data space during IAP,
then back to Program space when complete.
PSDsoftPSDsoft, a software development tool from ST,
guides you through the design process step-by-
step making it possible to complete an embedded
MCU design capable of ISP/IAP in just hours. Se-
lect your MCU and PSDsoft takes you through the
remainder of the design with point and click entry,
covering PSD selection, pin definitions, program-
mable logic inputs and outputs, MCU memory map
definition, ANSI-C code generation for your MCU,
and merging your MCU firmware with the PSD de-
sign. When complete, two different device pro-
grammers are supported directly from PSDsoft:
FlashLINK (JTAG) and PSDpro.
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PSD835G2V
Table 1. Pin Description (for the TQFP80 package)
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PSD ARCHITECTURAL OVERVIEWPSD devices contain several major functional
blocks. Figure 3., page 12 shows the architecture
of the PSD device family. The functions of each
block are described briefly in the following sec-
tions. Many of the blocks perform multiple func-
tions and are user configurable.
MemoryEach of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discus-
sion can be found in Memory Blocks, page 21.
The 4Mbit (512K x 8) Flash memory is the primary
memory of the PSD. It is divided into 8 equally-
sized sectors that are individually selectable.
The 256Kbit (32K x8) secondary Flash memory is
divided into 4 equally-sized sectors. Each sector is
individually selectable.
The 64 Kbit SRAM is intended for use as a
scratch-pad memory or as an extension to the
MCU SRAM. If an external battery is connected to
Voltage Standby (VSTBY, PC2), data is retained
in the event of power failure.
Each sector of memory can be located in a differ-
ent address space as defined by the user. The ac-
cess times for all memory types includes the
address latching and DPLD decoding time.
Page RegisterThe 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or in-
ternal memory and I/O. The Page Register can
also be used to change the address mapping of
sectors of the Flash memories into different mem-
ory spaces for IAP.
PLDsThe device contains two PLDs, the Decode PLD
(DPLD) and the Complex PLD (CPLD), as shown
in Table 2, each optimized for a different function.
The functional partitioning of the PLDs reduces
power consumption, optimizes cost/performance,
and eases design entry.
The DPLD is used to decode addresses and to
generate Sector Select signals for the PSD inter-
nal memory and registers. The CPLD can imple-
ment user-defined logic functions. The DPLD has
combinatorial outputs. The CPLD has 16 Output
Macrocells (OMC) and 8 combinatorial outputs.
The PSD also has 24 Input Macrocells (IMC) that
can be configured as inputs to the PLDs. The
PLDs receive their inputs from the PLD Input Bus
and are differentiated by their output destinations,
number of product terms, and macrocells.
The PLDs consume minimal power by using Pow-
er-Management design techniques. The speed
and power consumption of the PLD is controlled
by the Turbo bit in PMMR0 and other bits in the
PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD propaga-
tion time when invoking the power management
features.
I/O PortsThe PSD has 52 I/O pins distributed over the sev-
en ports (Port A, B, C, D, E, F and G). Each I/O pin
can be individually configured for different func-
tions. Ports can be configured as standard MCU I/
O ports, PLD I/O, or latched address outputs for
MCUs using multiplexed address/data buses.
The JTAG pins can be enabled on Port E for In-
System Programming (ISP). Ports F and G can
also be configured as data ports for a non-multi-
plexed bus.
Ports A and B can also be configured as a data
port for a non-multiplexed bus.
MCU Bus InterfacePSD interfaces easily with most 8-bit MCUs that
have either multiplexed or non-multiplexed ad-
dress/data buses. The device is configured to re-
spond to the MCU’s control signals, which are also
used as inputs to the PLDs. For examples, please
see MCU Bus Interface Examples, page 49.
Table 2. PLD I/O
Table 3. JTAG SIgnals on Port E
PSD835G2V
JTAG PortIn-System Programming (ISP) can be performed
through the JTAG signals on Port E. This serial in-
terface allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port E. Table 3., page 13 indi-
cates the JTAG pin assignments.
In-System Programming (ISP)Using the JTAG signals on Port E, the entire PSD
device (memory, logic, configuration) can be pro-
grammed or erased without the use of the MCU.
In-Application re-Programming (IAP)The primary Flash memory can also be pro-
grammed in-system by the MCU executing the
programming algorithms out of the secondary
memory, or SRAM. Since this is a sizable separate
block, the application can also continue to operate.
The secondary memory can be programmed the
same way by executing out of the primary Flash
memory. The PLD or other PSD Configuration
blocks can be programmed through the JTAG port
or a device programmer. Table 4 indicates which
programming methods can program different func-
tional blocks of the PSD.
Power Management Unit (PMU)The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The Turbo bit in PMMR0 can be
reset to 0 and the CPLD latches its outputs and
goes to sleep until the next transition on its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. Please see POWER
MANAGEMENT, page 67 for more details.
Table 4. Methods of Programming Different Functional Blocks of the PSD
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PSD835G2V
DEVELOPMENT SYSTEMThe PSD family is supported by PSDsoft, a Win-
dows-based (95, 98, NT) software development
tool. A PSD design is quickly and easily produced
in a point-and-click environment. The designer
does not need to enter Hardware Description Lan-
guage (HDL) equations, unless desired, to define
PSD pin functions and memory map information.
The general design flow is shown in Figure 4. PS-
Dsoft is available from our web site (the address is
given on the back page of this data sheet) or other
distribution channels.
PSDsoft directly supports two low cost device pro-
grammers form ST: PSDpro and FlashLINK
(JTAG). Both of these programmers may be pur-
chased through your local distributor/representa-
tive, or directly from our web site using a credit
card. The PSD is also supported by third party de-
vice programmers. See our web site for the current
list.
PSD835G2V
PSD REGISTER DESCRIPTION AND ADDRESS OFFSETTable 5 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 Bytes of address that is
allocated by the user to the internal PSD registers.
Table 5 provides brief descriptions of the registers
in CSIOP space. The following section gives a
more detailed description.
Table 5. Register Address OffsetNote:1. Other registers that are not part of the I/O ports.
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REGISTER BIT DEFINITIONAll the registers of the PSD are included here, for reference. Detailed descriptions of these registers can
be found in the following sections.
Table 6. Data-In Registers – Ports A, B, C, D, E, F, GNote: Bit Definitions (Read-only registers):
Read Port pin status when Port is in MCU I/O input mode.
Table 7. Data-Out Registers – Ports A, B, C, D, E, F, GNote: Bit Definitions:
Latched data for output to Port pin when pin is configured in MCU I/O output mode.
Table 8. Direction Registers – Ports A, B, C, D, E, F, GNote: Bit Definitions:
Port pin 0 = Port pin is configured in Input mode (default).
Port pin 1 = Port pin is configured in Output mode.
Table 9. Control Registers – Ports E, F, GNote: Bit Definitions:
Port pin 0 = Port pin is configured in MCU I/O mode (default).
Port pin 1 = Port pin is configured in Latched Address Out mode.
Table 10. Drive Registers – Ports A, B, D, E, GNote: Bit Definitions:
Port pin 0 = Port pin is configured for CMOS Output driver (default).
Port pin 1 = Port pin is configured for Open Drain output driver.
Table 11. Drive Registers – Ports C, FNote: Bit Definitions:
Port pin 0 = Port pin is configured for CMOS Output driver (default).
Port pin
1 = Port pin is configured in Slew Rate mode.
PSD835G2V
Table 12. Enable-Out Registers – Ports A, B, C, F
Note: Bit Definitions (Read-only registers):
Port pin 0 = Port pin is in tri-state driver (default).
Port pin 1 = Port pin is enabled.
Table 13. Input Macrocells – Ports A, B, C
Note: Bit Definitions (Read-only registers):
Read Input Macrocell (IMC7-IMC0) status on Ports A, B and C.
Table 14. Output Macrocells A Register
Note: Bit Definitions:
Write Register: Load MCellA7-MCellA0 with 0 or 1.
Read Register: Read MCellA7-MCellA0 output status.
Table 15. Output Macrocells B Register
Note: Bit Definitions:
Write Register: Load MCellB7-MCellB0 with 0 or 1.
Read Register: Read MCellB7-MCellB0 output status.
Table 16. Mask Macrocells A Register
Note: Bit Definitions:
McellA_Prot 0 = Allow MCellA flip-flop to be loaded by MCU (default).
McellA_Prot 1 = Prevent MCellA flip-flop from being loaded by MCU.
Table 17. Mask Macrocells B Register
Note: Bit Definitions:
McellB_Prot 0 = Allow MCellB flip-flop to be loaded by MCU (default).
McellB_Prot 1 = Prevent MCellB flip-flop from being loaded by MCU.
Table 18. Flash Memory Protection Register
Note: Bit Definitions (Read-only register):
Sec_Prot 1 = Primary Flash memory Sector is write protected.
Sec_Prot 0 = Primary Flash memory Sector is not write protected.
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Table 19. Flash Boot Protection Register
Note: Bit Definitions:
Sec_Prot 1 = Secondary Flash memory Sector is write protected.
Sec_Prot 0 = Secondary Flash memory Sector is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
Security_Bit 1 = Security Bit in device has been set.
Table 20. JTAG Enable Register
Note: Bit Definitions:
JTAG_Enable 1 = JTAG Port is enabled.
JTAG_Enable 0 = JTAG Port is disabled.
Table 21. Page Register
Note: Bit Definitions:
Configure Page input to PLD. Default is PGR7-PGR0=00.
Table 22. PMMR0 Register
Note:1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not clear the registers. Bit Definitions:
APD Enable0 = Automatic Power-down (APD) is disabled.
1 = Automatic Power-down (APD) is enabled.
PLD Turbo0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
PLD Array CLK0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off.
1 = CLKIN to the PLD AND array is disconnected, saving power.
PLD MCells CLK0 = CLKIN to the PLD Macrocells is connected.
1 = CLKIN to the PLD Macrocells is disconnected, saving power.
Table 23. PMMR2 Register
Note: Bit Definitions:
PLD Array Addr 0 = Address A7-A0 are connected to the PLD array.
1 = Address A7-A0 are blocked from the PLD array, saving power.
(Note: in XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4)
PLD Array CNTL20 = CNTL2 input to the PLD AND array is connected.
1 = CNTL2 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL10 = CNTL1 input to the PLD AND array is connected.
1 = CNTL1 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL00 = CNTL0 input to the PLD AND array is connected.
1 = CNTL0 input to the PLD AND array is disconnected, saving power.
PLD Array ALE 0 = ALE input to the PLD AND array is connected.
1 = ALE input to the PLD AND array is disconnected, saving power.
PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected.
1 = WRH/DBE input to the PLD AND array is disconnected, saving power.
PSD835G2V
Table 24. VM Register
Note:1. On reset, Bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft. Bit0 and Bit7 are always cleared on reset.
Bit0-Bit4 are active only when the device is configured in Philips 80C51XA mode. Bit Definitions:
SR_code0 = PSEN cannot access SRAM in 80C51XA modes.
1 = PSEN can access SRAM in 80C51XA modes.
Boot_code0 = PSEN cannot access Secondary NVM in 80C51XA modes.
1 = PSEN can access Secondary NVM in 80C51XA modes.
FL_code0 = PSEN cannot access Primary Flash memory in 80C51XA modes.
1 = PSEN can access Primary Flash memory in 80C51XA modes.
Boot_data0 = RD cannot access Secondary NVM in 80C51XA modes.
1 = RD can access Secondary NVM in 80C51XA modes.
FL_data0 = RD cannot access Primary Flash memory in 80C51XA modes.
1 = RD can access Primary Flash memory in 80C51XA modes.
Peripheral mode0 = Peripheral mode of Port F is disabled.
1 = Peripheral mode of Port F is enabled.
Table 25. Memory_ID0 Register
Note: Bit Definitions:
F_size[3:0] 4h = Primary Flash memory size is 4 Mbit
5h = Primary Flash memory size is 8Mbit
S_size[3:0] 0h = There is no SRAM
1h = SRAM size is 16 Kbit
3h = SRAM size is 64 Kbit
Table 26. Memory_ID1 Register
Note: Bit Definitions:
B_size[3:0] 0h = There is no Secondary NVM
2h = Secondary NVM size is 256 Kbit
B_type[1:0] 0h = Secondary NVM is Flash memory
1h = Secondary NVM is EEPROM
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DETAILED OPERATION
As shown in Figure 3., page 12, the PSD consists
of six major types of functional blocks: Memory Blocks PLD Blocks MCU Bus Interface I/O Ports Power Management Unit (PMU) JTAG/ISP Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
Memory Blocks
The PSD has the following memory blocks: Primary Flash memory Secondary Flash memory
–SRAM
The Memory Select signals for these blocks origi-
nate from the Decode PLD (DPLD) and are user-
defined in PSDsoft.
Table 27. Memory Block Size and Organization
PSD835G2V
Primary Flash Memory and Secondary Flash
memory Description
The primary Flash memory is divided evenly into
eight equal sectors. The secondary Flash memory
is divided into four equal sectors of eight KBytes
each. Each sector of either memory block can be
separately protected from Program and Erase cy-
cles.
Flash memory may be erased on a sector-by-sec-
tor basis and programmed Word-by-Word. Flash
sector erasure may be suspended while data is
read from other sectors of the block and then re-
sumed after reading.
During a Program or Erase cycle in Flash memory,
the status can be output on Ready/Busy (PE4).
This pin is set up using PSDsoft.
Memory Block Select Signals
The DPLD generates the Select signals for all the
internal memory blocks (see PLDs, page 35).
Each of the eight sectors of the primary Flash
memory has a Select signal (FS0-FS7) which can
contain up to three product terms. Each of the four
sectors of the secondary Flash memory has a Se-
lect signal (CSBOOT0-CSBOOT3) which can con-
tain up to three product terms. Having three
product terms for each Select signal allows a given
sector to be mapped in different areas of system
memory. When using an MCU with separate Pro-
gram and Data space, these flexible Select signals
allow dynamic re-mapping of sectors from one
memory space to the other before and after IAP.
Upper and Lower Block IN MAIN FLASH
SECTOR
The PSD835G2’s main Flash memory has eight
64-KByte sectors. The 64-KByte sector size may
cause some difficulty in code mapping for an 8-bit
MCU with only 64-KByte address space. To re-
solve this mapping issue, the PSD835G2 provides
additional logic (see Figure 6., page 23) for the
user to split the 8 sectors such that each sector
has a lower and upper 32-KByte block, and the
two blocks can reside in different pages but in the
same address range.
If your design works with 64KB sectors, you don’t
need to configure this logic. If the design requires
32KB blocks in each sector, you need to define a
“FA15” PLD equation in PSDsoft as the A15 ad-
dress input to the main Flash module. FA15 con-
sists of 3 product terms and will control whether
the MCU is accessing the lower or upper 32KB in
the selected sector. Figure 4 shows an example
for Flash sector chip select FS0. A typical equation
is FA15 = pgr4 of the Page Register. When pgr4 is (page 00), the lower 32KB is selected. When
pgr4 is switched to 1 by the user, the upper 32KB
is selected. PSDsoft will automatically generate
the PLD equations shown, based on your point
and click selections.
If no FA15 equation is defined in PSDsoft, the A15
that comes from the MCU address bus will be rout-
ed as input to the primary Flash memory instead of
FA15. The FA15 equation has no impact on the
Sector Erase operation.
Note: FA15 affects all eight sectors of the primary
Flash memory simultaneously. You cannot direct
FA15 to a particular Flash sector only.
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PSD835G2V
This signal can be used to output the Ready/Busy
status of the PSD. The output on Ready/Busy
(PE4) is a 0 (Busy) when Flash memory blocks are
being written to, or when the Flash memory block
is being erased. The output is a 1 (Ready) when
no Write or Erase cycle is in progress.
Memory Operation
The primary Flash memory and secondary Flash
memory are addressed through the MCU Bus In-
terface. The MCU can access these memories in
one of two ways: The MCU can execute a typical bus Write or
Read operation just as it would if accessing a
RAM or ROM device using standard bus cy-
cles. The MCU can execute a specific instruction
that consists of several Write and Read oper-
ations. This involves writing specific data pat-
terns to special addresses within the Flash
memory to invoke an embedded algorithm.
These instructions are summarized in Table
28., page 24.
Typically, the MCU can read Flash memory using
Read operations, just as it would read a ROM de-
vice. However, Flash memory can only be altered
using specific Erase and Program instructions. For
example, the MCU cannot write a single byte di-
rectly to Flash memory as it would write a byte to
RAM. To program a byte into Flash memory, the
MCU must execute a Program instruction, then
test the status of the Program cycle. This status
test is achieved by a Read operation or polling
Ready/Busy (PE4).
Flash memory can also be read by using special
instructions to retrieve particular Flash device in-
formation (sector protect status and ID).
PSD835G2V
Table 28. Instructions
Note:1. All bus cycles are write bus cycles, except the ones with the “Read” label All values are in hexadecimal:
X = Don’t Care.
RA = Address of the memory location to be read
RD = Data read from location RA during the Read cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0).
PA is an even address for PSD in word programming mode.
PD = Data to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select pins (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector or
whole memory to be erased, or verified, must be Active (High). Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) signals are active High, and are defined in PSDsoft. Only address bits A11-A0 are used in instruction decoding. A15-A12 (or A16-A12) are don’t care. No Unlock or instruction cycles are required when the device is in the Read mode The Reset instruction is required to return to the Read mode after reading the Flash ID, or after reading the Sector Protection Status,
or if the Error Flag (DQ5/DQ13) bit goes High. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80 µs. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1,A0)=(1,0) The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass
mode.
11. The system may perform Read and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is
intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status
of the primary Flash memory.
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PSD835G2V
INSTRUCTIONS
An instruction consists of a sequence of specific
operations. Each received Byte is sequentially de-
coded by the PSD and not executed as a standard
Write operation. The instruction is executed when
the correct number of Bytes is properly received
and the time between two consecutive Bytes is
shorter than the time-out period. Some instruc-
tions are structured to include Read operations af-
ter the initial Write operations.
The instruction must be followed exactly. Any in-
valid combination of instruction Bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into Read
mode (Flash memory is read like a ROM device).
The PSD supports the instructions summarized in
Table 28., page 24:
Flash memory: Erase memory by chip or sector Suspend or resume sector erase Program a Byte Reset to Read mode Read primary Flash Identifier value Read Sector Protection Status Bypass
These instructions are detailed in Table 28. For ef-
ficient decoding of the instructions, the first two
Bytes of an instruction are the coded cycles and
are followed by an instruction Byte or a confirma-
tion Byte. The coded cycles consist in writing the
data AAh to address X555h during the first cycle
and data 55h to address XAAAh during the second
cycle unless the Bypass Instruction feature is
used). Address signals A15-A12 are Don’t Care
during the instruction Write cycles. However, the
appropriate Sector Select (FS0-FS7 or
CSBOOT0-CSBOOT3) must be selected.
The primary and secondary Flash memories have
the same instruction set (except for Read Primary
Flash Identifier). The Sector Select signals deter-
mine which Flash memory is to receive and exe-
cute the instruction. The primary Flash memory is
selected if any one of Sector Select (FS0-FS7) is
High, and the secondary Flash memory is selected
if any one of Sector Select (CSBOOT0-
CSBOOT3) is High.
Power-up Mode
The PSD internal logic is reset upon Power-up to
the Read mode. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must be held Low, and
Write Strobe (WR, CNTL0) High, during Power-up
for maximum security of the data contents and to
remove the possibility of a byte being written on
the first edge of Write Strobe (WR, CNTL0). Any
Write cycle initiation is locked when VCC is below
VLKO.
READ
Under typical conditions, the MCU may read the
primary Flash memory or the secondary Flash
memory using Read operations just as it would a
ROM or RAM device. Alternately, the MCU may
use Read operations to obtain status information
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these memory blocks. The
following sections describe these Read functions.
Read Memory Contents
Primary Flash memory and secondary Flash
memory are placed in the Read mode after Power-
up, chip reset, or a Reset Flash instruction (see
Table 28). The MCU can read the memory con-
tents of the primary Flash memory or the second-
ary Flash memory by using Read operations any
time the Read operation is not part of an instruc-
tion.
Read Primary Flash Identifier
The primary Flash memory identifier is read with
an instruction composed of 4 operations: 3 specific
Write operations and a Read operation (see Table
28). The identifier for the device is E8h.
Read Memory Sector Protection Status
The primary Flash memory Sector Protection Sta-
tus is read with an instruction composed of 4 oper-
ations: 3 specific Write operations and a Read
operation (see Table 28). The Read operation pro-
duces 01h if the Flash memory sector is protected,
or 00h if the sector is not protected.
The sector protection status for all NVM blocks
(primary Flash memory or secondary Flash mem-
ory) can also be read by the MCU accessing the
Flash Protection and Flash Boot Protection regis-
ters in PSD I/O space. See Flash Memory Sector
Protect, page 31, for register definitions.
PSD835G2V
Read the Erase/Program Status Bits
The PSD provides several status bits to be used
by the MCU to confirm the completion of an Erase
or Program cycle of Flash memory. These status
bits minimize the time that the MCU spends per-
forming these tasks and are defined in Table 29.
The status bits can be read as many times as
needed.
For Flash memory, the MCU can perform a Read
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algorithm. See PROGRAMMING
FLASH MEMORY, page 28, for details.
Table 29. Status Bit
Note:1. X = Not guaranteed value, can be read either 1 or 0. DQ7-DQ0 represent the Data Bus bits, D7-D0. FS0-FS7 and CSBOOT0-CSBOOT3 are active High.
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PSD835G2V
Data Polling Flag (DQ7)
When erasing or programming in Flash memory,
the Data Polling Flag (DQ7) bit outputs the com-
plement of the bit being entered for programming/
writing on the DQ7 bit. Once the Program instruc-
tion or the Write operation is completed, the true
logic value is read on the Data Polling Flag (DQ7)
bit (in a Read operation). Data Polling is effective after the fourth Write
pulse (for a Program instruction) or after the
sixth Write pulse (for an Erase instruction). It
must be performed at the address being pro-
grammed or at an address within the Flash
memory sector being erased. During an Erase cycle, the Data Polling Flag
(DQ7) bit outputs a 0. After completion of the
cycle, the Data Polling Flag (DQ7) bit outputs
the last bit programmed (it is a 1 after erasing). If the Byte to be programmed is in a protected
Flash memory sector, the instruction is ig-
nored. If all the Flash memory sectors to be erased
are protected, the Data Polling Flag (DQ7) bit
is reset to 0 for about 100 µs, and then returns
to the previous addressed byte. No erasure is
performed.
Toggle Flag (DQ6)
The PSD offers another way for determining when
the Flash memory Program cycle is completed.
During the internal Write operation and when ei-
ther the FS0-FS7 or CSBOOT0-CSBOOT3 is true,
the Toggle Flag (DQ6) bit toggles from 0 to 1 and
1 to 0 on subsequent attempts to read any Byte of
the memory.
When the internal cycle is complete, the toggling
stops and the data read on the Data Bus D0-D7 is
the addressed memory Byte. The device is now
accessible for a new Read or Write operation. The
cycle is finished when two successive Reads yield
the same output data. The Toggle Flag (DQ6) bit is effective after the
fourth Write pulse (for a Program instruction)
or after the sixth Write pulse (for an Erase in-
struction). If the Byte to be programmed belongs to a pro-
tected Flash memory sector, the instruction is
ignored. If all the Flash memory sectors selected for
erasure are protected, the Toggle Flag (DQ6)
bit toggles to 0 for about 100 µs and then re-
turns to the previous addressed Byte.
Error Flag (DQ5)
During a normal Program or Erase cycle, the Error
Flag (DQ5) bit is set to 0. This bit is set to 1 when
there is a failure during Flash memory Byte Pro-
gram, Sector Erase, or Bulk Erase cycle.
In the case of Flash memory programming, the Er-
ror Flag (DQ5) bit indicates the attempt to program
a Flash memory bit from the programmed state, 0,
to the erased state, 1, which is not valid. The Error
Flag (DQ5) bit may also indicate a Time-out condi-
tion while attempting to program a Byte.
In case of an error in a Flash memory Sector Erase
or Byte Program cycle, the Flash memory sector in
which the error occurred or to which the pro-
grammed Byte belongs must no longer be used.
Other Flash memory sectors may still be used.
The Error Flag (DQ5) bit is reset after a Reset
Flash instruction.
Erase Time-out Flag (DQ3)
The Erase Time-out Flag (DQ3) bit reflects the
time-out period allowed between two consecutive
Sector Erase instructions. The Erase Time-out
Flag (DQ3) bit is reset to 0 after a Sector Erase cy-
cle for a time period of 100 µs + 20% unless an ad-
ditional Sector Erase instruction is decoded. After
this time period, or when the additional Sector
Erase instruction is decoded, the Erase Time-out
Flag (DQ3) bit is set to 1.
PSD835G2V
PROGRAMMING FLASH MEMORY
Flash memory must be erased prior to being pro-
grammed. The MCU may erase Flash memory all
at once or by-sector. A Flash memory sector is
erased to all 1s (FFh), and is programmed by set-
ting selected bits to 0. Although Flash memory is
erased by-sector, it is programmed Word-by-
Word.
The primary and secondary Flash memories re-
quire the MCU to send an instruction to program a
Word or to erase sectors (see Table 28., page 24).
Once the MCU issues a Flash memory Program or
Erase instruction, it must check the status bits for
completion. The embedded algorithms that are in-
voked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or the Ready/Busy (PE4) output pin.
Data Polling
Polling on the Data Polling Flag (DQ7) bit is a
method of checking whether a Program or Erase
cycle is in progress or has completed. Figure 7
shows the Data Polling algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the Word to be
programmed in Flash memory to check status.
The Data Polling Flag (DQ7) bit of this location be-
comes the complement of b7 of the original data
byte to be programmed. The MCU continues to
poll this location, comparing the Data Polling Flag
(DQ7) bit and monitoring the Error Flag (DQ5) bit.
When the Data Polling Flag (DQ7) bit matches b7
of the original data, and the Error Flag (DQ5) bit
remains 0, the embedded algorithm is complete. If
the Error Flag (DQ5) bit is 1, the MCU should test
the Data Polling Flag (DQ7) bit again since the
Data Polling Flag (DQ7) bit may have changed si-
multaneously with the Error Flag (DQ5) bit (see
Figure 7).
The Error Flag (DQ5) bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the Byte or if the MCU at-
tempted to program a 1 to a bit that was not erased
(not erased is logic 0).
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PSD835G2V
Data Toggle
Checking the Toggle Flag (DQ6) bit is a method of
determining whether a Program or Erase cycle is
in progress or has completed. Figure 8 shows the
Data Toggle algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the byte to be pro-
grammed in Flash memory to check status. The
Toggle Flag (DQ6) bit of this location toggles each
time the MCU reads this location until the embed-
ded algorithm is complete. The MCU continues to
read this location, checking the Toggle Flag (DQ6)
bit and monitoring the Error Flag (DQ5) bit. When
the Toggle Flag (DQ6) bit stops toggling (two con-
secutive reads yield the same value), and the Er-
ror Flag (DQ5) bit remains 0, the embedded
algorithm is complete. If the Error Flag (DQ5) bit is
1, the MCU should test the Toggle Flag (DQ6) bit
again, since the Toggle Flag (DQ6) bit may have
changed simultaneously with the Error Flag (DQ5)
bit (see Figure 8).
The Error Flag (DQ5) bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte, or if the MCU at-
tempted to program a 1 to a bit that was not erased
(not erased is logic 0).
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
Byte that was written to Flash memory with the
Byte that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 8 still applies. the Toggle Flag
(DQ6) bit toggles until the Erase cycle is complete.
A 1 on the Error Flag (DQ5) bit indicates a time-out
condition on the Erase cycle; a 0 indicates no er-
ror. The MCU can read any location within the sec-
tor being erased to get the Toggle Flag (DQ6) bit
and the Error Flag (DQ5) bit.
PSDsoft generates ANSI C code functions which
implement these Data Toggling algorithms.
Unlock Bypass. The Unlock Bypass instructions
allow the system to program bytes to the Flash
memories faster than using the standard Program
instruction. The Unlock Bypass mode is entered
by first initiating two Unlock cycles. This is followed
by a third Write cycle containing the Unlock By-
pass code, 20h (as shown in Table 28., page 24).
PSD835G2V
ERASING FLASH MEMORY
Flash Bulk Erase
The Flash Bulk Erase instruction uses six Write
operations followed by a Read operation of the
status register, as described in Table
28., page 24. If any byte of the Bulk Erase instruc-
tion is wrong, the Bulk Erase instruction aborts and
the device is reset to the Read Flash memory sta-
tus.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag (DQ5) bit, the
Toggle Flag (DQ6) bit, and the Data Polling Flag
(DQ7) bit, as detailed in PROGRAMMING FLASH
MEMORY, page 28. The Error Flag (DQ5) bit re-
turns a 1 if there has been an Erase Failure (max-
imum number of Erase cycles has been
executed).
It is not necessary to program the memory with
00h because the PSD automatically does this be-
fore erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.
Flash Sector Erase
The Sector Erase instruction uses six Write oper-
ations, as described in Table 28., page 24. Addi-
tional Flash Sector Erase codes and Flash
memory sector addresses can be written subse-
quently to erase other Flash memory sectors in
parallel, without further coded cycles, if the addi-
tional bytes are transmitted in a shorter time than
the time-out period of about 100 µs. The input of a
new Sector Erase code restarts the time-out peri-
od.
The status of the internal timer can be monitored
through the level of the Erase Time-out Flag (DQ3)
bit. If the Erase Time-out Flag (DQ3) bit is 0, the
Sector Erase instruction has been received and
the time-out period is counting. If the Erase Time-
out Flag (DQ3) bit is 1, the time-out period has ex-
pired and the PSD is busy erasing the Flash mem-
ory sector(s). Before and during Erase time-out,
any instruction other than Suspend Sector Erase
and Resume Sector Erase instructions abort the
cycle that is currently in progress, and reset the
device to Read mode. It is not necessary to pro-
gram the Flash memory sector with 00h as the
PSD does this automatically before erasing
(Byte=FFh).
During a Sector Erase, the memory status may be
checked by reading the Error Flag (DQ5) bit, the
Toggle Flag (DQ6) bit, and the Data Polling Flag
(DQ7) bit, as detailed in PROGRAMMING FLASH
MEMORY, page 28.
During execution of the Erase cycle, the Flash
memory accepts only Reset and Suspend Sector
Erase instructions. Erasure of one Flash memory
sector may be suspended, in order to read data
from another Flash memory sector, and then re-
sumed.
Suspend Sector Erase
When a Sector Erase cycle is in progress, the Sus-
pend Sector Erase instruction can be used to sus-
pend the cycle by writing 0B0h to any even
address when an appropriate Sector Select (FS0-
FS7 or CSBOOT0-CSBOOT3) is High. (See Table
28., page 24). This allows reading of data from an-
other Flash memory sector after the Erase cycle
has been suspended. Suspend Sector Erase is
accepted only during an Erase cycle and defaults
to Read mode. A Suspend Sector Erase instruc-
tion executed during an Erase time-out period, in
addition to suspending the Erase cycle, terminates
the time out period.
The Toggle Flag (DQ6) bit stops toggling when the
PSD internal logic is suspended. The status of this
bit must be monitored at an address within the
Flash memory sector being erased. The Toggle
Flag (DQ6) bit stops toggling between 0.1 µs and µs after the Suspend Sector Erase instruction
has been executed. The PSD is then automatically
set to Read mode.
If an Suspend Sector Erase instruction was exe-
cuted, the following rules apply: Attempting to read from a Flash memory sec-
tor that was being erased outputs invalid data. Reading from a Flash sector that was not be-
ing erased is valid. The Flash memory cannot be programmed,
and only responds to Resume Sector Erase
and Reset Flash instructions (Read is an oper-
ation and is allowed). If a Reset Flash instruction is received, data in
the Flash memory sector that was being
erased is invalid.
Resume Sector Erase
If a Suspend Sector Erase instruction was previ-
ously executed, the erase cycle may be resumed
with this instruction. The Resume Sector Erase in-
struction consists in writing 030h to any even ad-
dress while an appropriate Sector Select (FS0-
FS7 or CSBOOT0-CSBOOT3) is High. (See Table
28., page 24.)
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PSD835G2V
SPECIFIC FEATURES
Flash Memory Sector Protect
Each primary and secondary Flash memory sector
can be separately protected against Program and
Erase cycles. Sector Protection provides addition-
al data security because it disables all Program or
Erase cycles. This mode can be activated through
the JTAG/ISP Port or a Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft program. This automatically
protects selected sectors when the device is pro-
grammed through the JTAG Port or a Device Pro-
grammer. Flash memory sectors can be
unprotected to allow updating of their contents us-
ing the JTAG Port or a Device Programmer. The
MCU can read (but cannot change) the sector pro-
tection bits.
Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a read of the protected data.
The retention of the Protection status is thus en-
sured.
The sector protection status can be read by the
MCU through the primary and secondary Flash
memory protection registers (in the CSIOP block).
See Table 18., page 18 and Table 19., page 19.
Reset Flash
The Reset Flash instruction consists of one Write
cycle (see Table 28., page 24). It can also be op-
tionally preceded by the standard two write decod-
ing cycles (writing AAh to AAAh and 55h to 554h).
It must be executed after: Reading the Flash Protection Status or Flash
ID using the Flash instruction. An Error condition has occurred (and the de-
vice has set the Error Flag (DQ5) bit to 1) dur-
ing a Flash memory Program or Erase cycle.
The Reset Flash instruction puts the Flash memo-
ry back into normal Read mode immediately. If an
Error condition has occurred (and the device has
set the Error Flag (DQ5) bit to 1) the Flash memory
is put back into normal Read mode within 25µs of
the Reset Flash instruction having been issued.
The Reset Flash instruction is ignored when it is is-
sued during a Program or Bulk Erase cycle of the
Flash memory. The Reset Flash instruction aborts
any on-going Sector Erase cycle, and returns the
Flash memory to the normal Read mode within
25µs.
Reset (RESET) Signal
A pulse on Reset (RESET) aborts any cycle that is
in progress, and resets the Flash memory to the
Read mode. When the reset occurs during a Pro-
gram or Erase cycle, the Flash memory takes up
to 25µ s to return to the Read mode. It is recom-
mended that the Reset (RESET) pulse (except for
Power-Up Reset, described in Power-Up
Reset, page 71) be at least 25µ s so that the Flash
memory is always ready for the MCU to fetch the
bootstrap instructions after the Reset cycle is com-
plete.
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to three product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to Voltage Stand-by (VSTBY, PE6). If you have an
external battery connected to the PSD, the con-
tents of the SRAM are retained in the event of a
power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at V or greater. If the supply voltage falls below the
battery voltage, an internal power switch-over to
the battery occurs.
PE7 can be configured as an output that indicates
when power is being drawn from the external bat-
tery. Battery-on Indicator (VBATON, PE7) is High
when the supply voltage falls below the battery
voltage and the battery on Voltage Stand-by (VST-
BY, PE6) is supplying power to the internal SRAM.
SRAM Select (RS0), Voltage Stand-by (VSTBY,
PC2) and Battery-on Indicator (VBATON, PC4)
are all configured using PSDsoft Express Configu-
ration.
The SRAM Select (RS0), VBATON and VSTBY
are all configured using PSDsoft.
PSD835G2V
SECTOR SELECT AND SRAM SELECT
Sector Select (FS0-FS7 for primary Flash memo-
ry, CSBOOT0-CSBOOT3 for secondary Flash
memory) and SRAM Select (RS0) are all outputs
of the DPLD. They are setup using PSDsoft. The
following rules apply to the equations for these sig-
nals: Primary Flash memory and secondary Flash
memory Sector Select signals must not be
larger than the physical sector size. Any primary Flash memory sector must not be
mapped in the same memory space as
another primary Flash memory sector. A secondary Flash memory sector must not be
mapped in the same memory space as
another secondary Flash memory sector. SRAM and I/O spaces must not overlap. A secondary Flash memory sector may
overlap a primary Flash memory sector. In
case of overlap, priority is given to the
secondary Flash memory sector. SRAM and I/O spaces may overlap any other
memory sector. Priority is given to the SRAM
and I/O.
Example
FS0 is valid when the address is in the range of
8000h to BFFFh, CSBOOT0 is valid from 8000h to
9FFFh, and RS0 is valid from 8000h to 87FFh.
Any address in the range of RS0 always accesses
the SRAM. Any address in the range of CSBOOT0
greater than 87FFh (and less than 9FFFh) auto-
matically addresses secondary Flash memory
segment 0. Any address greater than 9FFFh ac-
cesses the primary Flash memory segment 0. You
can see that half of the primary Flash memory seg-
ment 0 and one-fourth of secondary Flash memory
segment 0 cannot be accessed in this example.
Also note that an equation that defined FS1 to any-
where in the range of 8000h to BFFFh would not
be valid.
Figure 9 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
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PSD835G2V
Configuration Modes for MCUs with Separate
Program and Data Spaces
Separate Space Modes. Program space is sep-
arated from Data space. For example, Program
Select Enable (PSEN, CNTL2) is used to access
the program code from the primary Flash memory,
while Read Strobe (RD, CNTL1) is used to access
data from the secondary Flash memory, SRAM
and I/O Port blocks. This configuration requires
the VM register to be set to 0Ch (see Figure 10).
Combined Space Modes. The Program and
Data spaces are combined into one memory
space that allows the primary Flash memory, sec-
ondary Flash memory, and SRAM to be accessed
by either Program Select Enable (PSEN, CNTL2)
or Read Strobe (RD, CNTL1). For example, to
configure the primary Flash memory in Combined
space, bits b2 and b4 of the VM register are set to
1 (see Figure 11).
PSD835G2V
PAGE REGISTER
The 8-bit Page Register increases the addressing
capability of the MCU by a factor of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0-
PGR7) are inputs to the DPLD decoder and can be
included in the Sector Select (FS0-FS7,
CSBOOT0-CSBOOT3), and SRAM Select (RS0)
equations.
If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic. See Application Note AN1154.
Figure 12 shows the Page Register. The eight flip-
flops in the register are connected to the internal
data bus D0-D7. The MCU can write to or read
from the Page Register. The Page Register can be
accessed at address location CSIOP + E0h.
The 8-bit Read-Only Memory Status Registers are
included in the CSIOP space. The user can deter-
mine the memory configuration of the PSD device
by reading the Memory ID0 and ID1 Registers.
The contents of the registers are defined in Table
25 and Table 26., page 20.
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PSD835G2V
PLDS
The PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
in PSDsoft, the logic is programmed into the de-
vice and available upon Power-up.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in Decode PLD
(DPLD), page 37, and in Complex PLD
(CPLD), page 38. Figure 13., page 36 shows the
configuration of the PLDs.
The DPLD performs address decoding for Select
signals for internal components, such as memory,
registers, and I/O ports.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0-
ECS2) signals.
The AND Array is used to form product terms.
These product terms are specified using PSDsoft.
An Input Bus consisting of 82 signals is connected
to the PLDs. The signals are shown in Table 30.
The Turbo Bit in PSD
The PLDs in the PSD can minimize power con-
sumption by switching to standby when inputs re-
main unchanged for an extended time of about
70ns. Resetting the Turbo bit to 0 (Bit 3 of
PMMR0) automatically places the PLDs into
standby if no inputs are changing. Turning the Tur-
bo mode off increases propagation delays while
reducing power consumption. See POWER
MANAGEMENT, page 67, on how to set the Tur-
bo bit.
Additionally, five bits are available in PMMR2 to
block MCU control signals from entering the PLDs.
This reduces power consumption and can be used
only when these MCU control signals are not used
in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
Table 30. DPLD and CPLD Inputs
Note:1. The address inputs are A19-A4 in 80C51XA mode.
PSD835G2V
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PSD835G2V
Decode PLD (DPLD)
The DPLD, shown in Figure 14, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals: 8 Sector Select (FS0-FS7) signals for the pri-
mary Flash memory (three product terms
each) 4 Sector Select (CSBOOT0-CSBOOT3) sig-
nals for the secondary Flash memory (three
product terms each) 1 internal SRAM Select (RS0) signal (three
product terms) 1 internal CSIOP Select (PSD Configuration
Register) signal 1 JTAG Select signal (enables JTAG/ISP on
Port E) 2 internal Peripheral Select signals
(Peripheral I/O mode).
PSD835G2V
Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate three External Chip Se-
lect (ECS0-ECS2), routed to Port D.
Although External Chip Select (ECS0-ECS2) can
be produced by any Output Macrocell (OMC),
these three External Chip Select (ECS0-ECS2) on
Port D do not consume any Output Macrocells
(OMC).
As shown in Figure 13., page 36, the CPLD has
the following blocks: 24 Input Macrocells (IMC) 16 Output Macrocells (OMC) Macrocell Allocator Product Term Allocator AND Array capable of generating up to 137
product terms Four I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
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PSD835G2V
PSD835G2V
Output Macrocell (OMC)
Eight of the Output Macrocells (OMC) are con-
nected to Port A pins and are named as McellA0-
McellA7. The other eight macrocells are connect-
ed to Port B pins and are named as McellB0-
McellB7.
The Output Macrocell (OMC) architecture is
shown in Figure 16., page 42. As shown in the fig-
ure, there are native product terms available from
the AND Array, and borrowed product terms avail-
able (if unused) from other Output Macrocells
(OMC). The polarity of the product term is con-
trolled by the XOR gate. The Output Macrocell
(OMC) can implement either sequential logic, us-
ing the flip-flop element, or combinatorial logic.
The multiplexer selects between the sequential or
combinatorial logic outputs. The multiplexer output
can drive a port pin and has a feedback path to the
AND Array inputs.
The flip-flop in the Output Macrocell (OMC) block
can be configured as a D, T, JK, or SR type in the
PSDsoft program. The flip-flop’s clock, preset, and
clear inputs may be driven from a product term of
the AND Array. Alternatively, CLKIN (PD1) can be
used for the clock input to the flip-flop. The flip-flop
is clocked to the rising edge of CLKIN (PD1). The
preset and clear are active High inputs. Each clear
input can use up to two product terms.
Table 31. Output Macrocell Port and Data Bit Assignments
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Product Term Allocator
The CPLD has a Product Term Allocator. The PS-
Dsoft uses the Product Term Allocator to borrow
and place product terms from one macrocell to an-
other. The following list summarizes how product
terms are allocated: McellA0-McellA7 all have three native product
terms and may borrow up to six more McellB0-McellB3 all have four native product
terms and may borrow up to five more McellB4-McellB7 all have four native product
terms and may borrow up to six more.
Each macrocell may only borrow product terms
from certain other macrocells. Product terms al-
ready in use by one macrocell are not available for
another macrocell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required that consume other Output Macro-
cells (OMC). If external product terms are used,
extra delay is added for the equation that required
the extra product terms.
This is called product term expansion. PSDsoft
performs this expansion as needed.
Loading and Reading the Output Macrocells
(OMC). The Output Macrocells (OMC) block oc-
cupies a memory location in the MCU address
space, as defined by the CSIOP block (see I/O
PORTS, page 56). The flip-flops in each of the 16
Output Macrocells (OMC) can be loaded from the
data bus by a MCU. Loading the Output Macro-
cells (OMC) with data from the MCU takes priority
over internal functions. As such, the preset, clear,
and clock inputs to the flip-flop can be overridden
by the MCU. The ability to load the flip-flops and
read them back is useful in such applications as
loadable counters and shift registers, mailboxes,
and handshaking protocols.
Data can be loaded to the Output Macrocells
(OMC) on the trailing edge of the Write Strobe
(WR, CNTL0) signal.
The OMC Mask Register
There is one Mask Register for each of the two
groups of eight Output Macrocells (OMC). The
Mask Registers can be used to block the loading
of data to individual Output Macrocells (OMC).
The default value for the Mask Registers is 00h,
which allows loading of the Output Macrocells
(OMC). When a given bit in a Mask Register is set
to a 1, the MCU is blocked from writing to the as-
sociated Output Macrocells (OMC). For example,
suppose McellA0-McellA3 are being used for a
state machine. You would not want a MCU write to
McellA to overwrite the state machine registers.
Therefore, you would want to load the Mask Reg-
ister for McellA (Mask Macrocell AB) with the value
0Fh.
The Output Enable of the OMC
The Output Macrocells (OMC) block can be con-
nected to an I/O port pin as a PLD output. The out-
put enable of each port pin driver is controlled by
a single product term from the AND Array, OR’ed
with the Direction Register output. The pin is en-
abled upon Power-up if no output enable equation
is defined and if the pin is declared as a PLD out-
put in PSDsoft.
If the Output Macrocell (OMC) output is declared
as an internal node and not as a port pin output in
the PSDabel file, the port pin can be used for other
I/O functions. The internal node feedback can be
routed as an input to the AND Array.
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Input Macrocells (IMC)
The CPLD has 24 Input Macrocells (IMC), one for
each pin on Ports A, B, and C. The architecture of
the Input Macrocells (IMC) is shown in Figure
17., page 44. The Input Macrocells (IMC) are indi-
vidually configurable, and can be used as a latch,
register, or to pass incoming Port signals prior to
driving them onto the PLD input bus. The outputs
of the Input Macrocells (IMC) can be read by the
MCU through the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND Array or the
MCU Address Strobe (ALE/AS). Each product
term output is used to latch or clock four Input
Macrocells (IMC). Port inputs 3-0 can be con-
trolled by one product term and 7-4 by another.
Configurations for the Input Macrocells (IMC) are
specified by PSDsoft. Outputs of the Input Macro-
cells (IMC) can be read by the MCU via the IMC
buffer. See I/O PORTS, page 56.
Input Macrocells (IMC) can use Address Strobe
(ALE/AS, PD0) to latch address bits higher than
A15. Any latched addresses are routed to the
PLDs as inputs.
Input Macrocells (IMC) are particularly useful with
handshaking communication applications where
two processors pass data back and forth through
a common mailbox. Figure 18., page 45 shows a
typical configuration where the Master MCU writes
to the Port A Data Out Register. This, in turn, can
be read by the Slave MCU via the activation of the
“Slave-Read” output enable product term.
The Slave can also write to the Port A Input Mac-
rocells (IMC) and the Master can then read the In-
put Macrocells (IMC) directly.
Note that the “Slave-Read” and “Slave-Wr” signals
are product terms that are derived from the Slave
MCU inputs Read Strobe (RD, CNTL1), Write
Strobe (WR, CNTL0), and Slave_CS.
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External Chip
The CPLD also provides eight Chip Select outputs
that can be used to select external devices. The
Chip Selects can be routed to either Port C or Port
F, depending on the pin declaration in the PSD-
soft. Each Chip Select (ECS0-ECS7) consists of
one product term that can be configured active
High or Low.
The Output Enable of the pin is controlled by either
the Output Enable product term or the Direction
Register (see Figure 19).
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MCU BUS INTERFACE
The “no-glue logic” MCU Bus Interface block can
be directly connected to most popular MCUs and
their control signals. Key 8-bit MCUs, with their
bus types and control signals, are shown in Table
32. The interface type is specified using the PSD-
soft.
Table 32. MCUs and their Control Signals
Note:1. Unused CNTL2 pin can be configured as PLD input. Other unused pins (PD3-PD0, PA3-PA0) can be configured for other I/O func-
tions. ALE/AS input is optional for MCUs with a non-multiplexed bus
PSD835G2V
PSD Interface to a Multiplexed 8-Bit Bus
Figure 20 shows an example of a system using a
MCU with an 8-bit multiplexed bus and a PSD. The
ADIO port on the PSD is connected directly to the
MCU address/data bus. Address Strobe (ALE/AS,
PD0) latches the address signals internally.
Latched addresses can be brought out to Port E,
For G. The PSD drives the ADIO data bus only
when one of its internal resources is accessed and
Read Strobe (RD, CNTL1) is active. Should the
system address bus exceed sixteen bits, Ports A,
B, C, or F may be used as additional address in-
puts.
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PSD Interface to a Non-Multiplexed 8-Bit Bus
Figure 21 shows an example of a system using a
MCU with an 8-bit non-multiplexed bus and a
PSD. The address bus is connected to the ADIO
Port, and the data bus is connected to Port F. Port
F is in tri-state mode when the PSD is not access-
ed by the MCU. Should the system address bus
exceed sixteen bits, Ports A, B or C may be used
for additional address inputs.
MCU Bus Interface Examples
Figures 22 through Figure 25., page 55 show ex-
amples of the basic connections between the PSD
and some popular MCUs. The PSD Control input
pins are labeled as to the MCU function for which
they are configured. The MCU bus interface is
specified using the PSDsoft.
