PSD834F2V-15M ,FLASH PSD, 3.3V SUPPLY, FOR 8-BIT MCUS 2 MBIT + 256 KBIT DUAL FLASH MEMORIES AND 64 KBIT SRAMFeatures . . . . . . 22SRAM . . . . . . . 23Sector Select and SRAM Select . .23 ..
PSD835G2V-12UI ,Flash PSD, 3V Supply, for 8-bit MCUs 4Mbit + 256 Kbit Dual Flash Memories and 64Kbit SRAMFEATURES SUMMARY■ FLASH IN-SYSTEM PROGRAMMABLE (ISP) Figure 1. PackagePERIPHERAL FOR 8-BIT MCUs■ DU ..
PSD853F2-90M ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5VPSD813F2, PSD833F2PSD834F2, PSD853F2, PSD854F2Flash In-System Programmable (ISP)Peripherals for 8-b ..
PSD854F2-70M ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5VFEATURES SUMMARY . . . . . 1SUMMARY DESCRIPTION . . . 6PIN DESCRIPTION 10PSD A ..
PSD854F2-90M ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5VPSD813F2, PSD833F2PSD834F2, PSD853F2, PSD854F2Flash In-System Programmable (ISP)Peripherals for 8-b ..
PSD854F2-90MI ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5VFEATURES SUMMARY■ FLASH IN-SYSTEM PROGRAMMABLE (ISP) Figure 1. PackagesPERIPHERAL FOR 8-BIT MCUS■ D ..
QL16X24B-1PL84C , pASIC 1 Family Very-High-Speed CMOS FPGA
QL16X24B-1PL84C , pASIC 1 Family Very-High-Speed CMOS FPGA
QL2003-1PF144C , 3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility
QL2003-1PF144C , 3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility
QL2007-0PF144C , 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility
QL2007-0PF144C , 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility
PSD834F2V-15M
FLASH PSD, 3.3V SUPPLY, FOR 8-BIT MCUS 2 MBIT + 256 KBIT DUAL FLASH MEMORIES AND 64 KBIT SRAM
1/95
PRELIMINARY DATANovember 2003
PSD834F2VFlash PSD, 3.3V Supply, for 8-bit MCUs
2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM
FEATURES SUMMARY FLASH IN-SYSTEM PROGRAMMABLE (ISP)
PERIPHERAL FOR 8-BIT MCUs 3.3 V±10% SINGLE SUPPLY VOLTAGE 2 MBIT OF PRIMARY FLASH MEMORY (8
UNIFORM SECTORS, 32K x 8) 256 KBIT SECONDARY FLASH MEMORY (4
UNIFORM SECTORS) 64 KBIT OF BATTERY-BACKED SRAM OVER 3,000 GATES OF PLD: DPLD and CPLD 27 RECONFIGURABLE I/O PORTS ENHANCED JTAG SERIAL PORT PROGRAMMABLE POWER MANAGEMENT HIGH ENDURANCE: 100,000 Erase/WRITE Cycles of Flash
Memory 1,000 Erase/WRITE Cycles of PLD
PSD834F2V2/95
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
KEY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PSD REGISTER DESCRIPTION AND ADDRESS OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
MEMORY BLOCKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . .15
Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Power-down Instruction and Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Specific Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3/95
PSD834F2V
PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
I/O PORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
General Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Port Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Peripheral I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Ports A and B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Port D Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Port D – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Port D Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
PSD834F2V4/95
RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Reset of Flash Memory Erase and Program Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . .63
Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
JTAG Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
PQFQ52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
PLCC52 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
5/95
PSD834F2V
SUMMARY DESCRIPTIONThe PSD family of memory systems for microcon-
trollers (MCUs) brings In-System-Programmability
(ISP) to Flash memory and programmable logic.
The result is a simple and flexible solution for em-
bedded designs. PSD devices combine many of
the peripheral functions found in MCU based ap-
plications.
The CPLD in the PSD devices features an opti-
mized macrocell logic architecture. The PSD mac-
rocell was created to address the unique
requirements of embedded system designs. It al-
lows direct connection between the system ad-
dress/data bus, and the internal PSD registers, to
simplify communication between the MCU and
other supporting devices.
The PSD device includes a JTAG Serial Program-
ming interface, to allow In-System Programming
(ISP) of the entire device. This feature reduces de-
velopment time, simplifies the manufacturing flow,
and dramatically lowers the cost of field upgrades.
Using ST’s special Fast-JTAG programming, a de-
sign can be rapidly programmed into the PSD in as
little as seven seconds.
The innovative PSD family solves key problems
faced by designers when managing discrete Flash
memory devices, such as: First-time In-System Programming (ISP) Complex address decoding Simulataneous READ and WRITE to the
device.
The JTAG Serial Interface block allows In-System
Programming (ISP), and eliminates the need for
an external Boot EPROM, or an external program-
mer. To simplify Flash memory updates, program
execution is performed from a secondary Flash
memory while the primary Flash memory is being
updated. This solution avoids the complicated
hardware and software overhead necessary to im-
plement IAP.
ST makes available a software development tool,
PSDsoft Express, that generates ANSI-C compli-
ant code for use with your target MCU. This code
allows you to manipulate the non-volatile memory
(NVM) within the PSD. Code examples are also
provided for: Flash memory IAP via the UART of the host
MCU Memory paging to execute code across several
PSD memory pages Loading, reading, and manipulation of PSD
macrocells by the MCU.
PSD834F2V6/95
KEY FEATURES A simple interface to 8-bit microcontrollers that
use either multiplexed or non-multiplexed
busses. The bus interface logic uses the control
signals generated by the microcontroller
automatically when the address is decoded and
a READ or WRITE is performed. A partial list of
the MCU families supported include: Intel 8031, 80196, 80186, 80C251, and
80386EX Motorola 68HC11, 68HC16, 68HC12, and
683XX Philips 8031 and 8051XA Zilog Z80 and Z8 Internal 2 Mbit Flash memory. This is the main
Flash memory. It is divided into 8 equal-sized
blocks that can be accessed with user-specified
addresses. Internal secondary 256 Kbit Flash boot memory.
It is divided into 4 equal-sized blocks that can be
accessed with user-specified addresses. This
secondary memory brings the ability to execute
code and update the main Flash concurrently. Internal 64 Kbit SRAM. The SRAM’s contents
can be protected from a power failure by
connecting an external battery. CPLD with 16 Output macrocells (OMCs) and
24 Input macrocells (IMCs). The CPLD may be
used to efficiently implement a variety of logic
functions for internal and external control.
Examples include state machines, loadable
shift registers, and loadable counters. Decode PLD (DPLD) that decodes address for
selection of internal memory blocks. 27 individually configurable I/O port pins that
can be used for the following functions: MCU I/Os
–PLD I/Os Latched MCU address output Special function I/Os. 16 of the I/O ports may be configured as
open-drain outputs. Standby current as low as 25μA. Built-in JTAG compliant serial port allows full-
chip In-System Programmability (ISP). With it,
you can program a blank device or reprogram a
device in the factory or the field. Internal page register that can be used to
expand the microcontroller address space by a
factor of 256. Internal programmable Power Management
Unit (PMU) that supports a low power mode
called Power Down Mode. The PMU can
automatically detect a lack of microcontroller
activity and put the PSD into Power-down
mode. Erase/WRITE cycles: Flash memory – 100,000 minimum PLD – 1,000 minimum Data Retention: 15 year minimum (for Main
Flash memory, Boot, PLD and Configuration
bits)
7/95
PSD834F2V
PSD834F2V8/95
PSD ARCHITECTURAL OVERVIEWPSD devices contain several major functional
blocks. Figure 2 shows the architecture of the PSD
device family. The functions of each block are de-
scribed briefly in the following sections. Many of
the blocks perform multiple functions and are user
configurable.
MemoryEach of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discus-
sion can be found in the section entitled “MEMO-
RY BLOCKS“ on page 15.
The 2 Mbit (256K x 8) Flash memory is the primary
memory of the PSD. It is divided into 8 equally-
sized sectors that are individually selectable.
The 256 Kbit (32K x 8) secondary Flash memory
is divided into 4 equally-sized sectors. Each sector
is individually selectable.
The 64 Kbit SRAM is intended for use as a
scratch-pad memory or as an extension to the
MCU SRAM. If an external battery is connected to
Voltage Stand-by (VSTBY, PC2), data is retained
in the event of power failure.
Each sector of memory can be located in a differ-
ent address space as defined by the user. The ac-
cess times for all memory types includes the
address latching and DPLD decoding time.
Page RegisterThe 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or in-
ternal memory and I/O. The Page Register can
also be used to change the address mapping of
sectors of the Flash memories into different mem-
ory spaces for IAP.
PLDsThe device contains two PLDs, the Decode PLD
(DPLD) and the Complex PLD (CPLD), as shown
in Table 1, each optimized for a different function.
The functional partitioning of the PLDs reduces
power consumption, optimizes cost/performance,
and eases design entry.
Table 1. PLD I/OThe DPLD is used to decode addresses and to
generate Sector Select signals for the PSD inter-
nal memory and registers. The DPLD has combi-
natorial outputs. The CPLD has 16 Output
Macrocells (OMC) and 3 combinatorial outputs.
The PSD also has 24 Input Macrocells (IMC) that
can be configured as inputs to the PLDs. The
PLDs receive their inputs from the PLD Input Bus
and are differentiated by their output destinations,
number of product terms, and macrocells.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo Bit in PMMR0 and other bits in the
PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD propaga-
tion time when invoking the power management
features.
I/O PortsThe PSD has 27 individually configurable I/O pins
distributed over the four ports (Port A, B, C, and
D). Each I/O pin can be individually configured for
different functions. Ports can be configured as
standard MCU I/O ports, PLD I/O, or latched ad-
dress outputs for MCUs using multiplexed ad-
dress/data buses.
The JTAG pins can be enabled on Port C for In-
System Programming (ISP).
Ports A and B can also be configured as a data
port for a non-multiplexed bus.
MCU Bus InterfacePSD interfaces easily with most 8-bit MCUs that
have either multiplexed or non-multiplexed ad-
dress/data buses. The device is configured to re-
spond to the MCU’s control signals, which are also
used as inputs to the PLDs. For examples, please
see the section entitled “MCU Bus Interface Exam-
ples“ on page 41.
9/95
PSD834F2V
JTAG PortIn-System Programming (ISP) can be performed
through the JTAG signals on Port C. This serial in-
terface allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port C. Table 2 indicates the
JTAG pin assignments.
In-System Programming (ISP)Using the JTAG signals on Port C, the entire PSD
device can be programmed or erased without the
use of the MCU. The primary Flash memory can
also be programmed in-system by the MCU
executing the programming algorithms out of the
secondary memory, or SRAM. The secondary
memory can be programmed the same way by
executing out of the primary Flash memory. The
PLD or other PSD Configuration blocks can be
programmed through the JTAG port or a device
programmer. Table 3 indicates which
programming methods can program different
functional blocks of the PSD.
Power Management Unit (PMU)The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The Turbo Bit in PMMR0 can be
reset to '0' and the CPLD latches its outputs and
goes to sleep until the next transition on its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. Please see the sec-
tion entitled “POWER MANAGEMENT” on page
56 for more details.
Table 2. JTAG SIgnals on Port C
Table 3. Methods of Programming Different Functional Blocks of the PSD
PSD834F2V10/95
DEVELOPMENT SYSTEMThe PSD family is supported by PSDsoft Express,
a Windows-based software development tool. A
PSD design is quickly and easily produced in a
point and click environment. The designer does
not need to enter Hardware Description Language
(HDL) equations, unless desired, to define PSD
pin functions and memory map information. The
general design flow is shown in Figure 3. PSDsoft
Express is available from our web site (the ad-
dress is given on the back page of this data sheet)
or other distribution channels.
PSDsoft Express directly supports two low cost
device programmers form ST: PSDpro and
FlashLINK (JTAG). Both of these programmers
may be purchased through your local distributor/
representative, or directly from our web site using
a credit card. The PSD is also supported by third
party device programmers. See our web site for
the current list.
11/95
PSD834F2V
PIN DESCRIPTIONTable 4 describes the signal names and signal
functions of the PSD.
Table 4. Pin Description (for the PLCC52 package - Note 1)
PSD834F2V12/95
13/95
PSD834F2VNote:1. The pin numbers in this table are for the PLCC package only. See the package information, on page 90 onwards, for pin numbers
on other package types. These functions can be multiplexed with other functions.
PSD REGISTER DESCRIPTION AND ADDRESS OFFSETTable 6 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al-
located by the user to the internal PSD registers.
Table 6 provides brief descriptions of the registers
in CSIOP space. The following section gives a
more detailed description.
PSD834F2V14/95
Table 5. I/O Port Latched Address Output Assignments (Note 1)Note:1. See the section entitled “I/O PORTS”, on page 46, on how to enable the Latched Address Output function. N/A = Not Applicable
Table 6. Register Address OffsetNote:1. Other registers that are not part of the I/O ports.
15/95
PSD834F2V
DETAILED OPERATIONAs shown in Figure 2, the PSD consists of six ma-
jor types of functional blocks: Memory Blocks PLD Blocks MCU Bus Interface I/O Ports Power Management Unit (PMU) JTAG Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
MEMORY BLOCKSThe PSD has the following memory blocks: Primary Flash memory Secondary Flash memory
–SRAM
The Memory Select signals for these blocks origi-
nate from the Decode PLD (DPLD) and are user-
defined in PSDsoft Express.
Primary Flash Memory and Secondary Flash
memory DescriptionThe primary Flash memory is divided evenly into
eight equal sectors. The secondary Flash memory
is divided into four equal sectors. Each sector of
either memory block can be separately protected
from Program and Erase cycles.
Flash memory may be erased on a sector-by-sec-
tor basis. Flash sector erasure may be suspended
while data is read from other sectors of the block
and then resumed after reading.
During a Program or Erase cycle in Flash memory,
the status can be output on Ready/Busy (PC3).
This pin is set up using PSDsoft Express Configu-
ration.
Memory Block Select SignalsThe DPLD generates the Select signals for all the
internal memory blocks (see the section entitled
“PLDS”, on page 27). Each of the eight sectors of
the primary Flash memory has a Select signal
(FS0-FS7) which can contain up to three product
terms. Each of the four sectors of the secondary
Flash memory has a Select signal (CSBOOT0-
CSBOOT3) which can contain up to three product
terms. Having three product terms for each Select
signal allows a given sector to be mapped in differ-
ent areas of system memory. When using a MCU
with separate Program and Data space, these
flexible Select signals allow dynamic re-mapping
of sectors from one memory space to the other.
Ready/Busy (PC3). This signal can be used to
output the Ready/Busy status of the PSD. The out-
put on Ready/Busy (PC3) is a 0 (Busy) when Flash
memory is being written to, or when Flash memory
is being erased. The output is a 1 (Ready) when
no WRITE or Erase cycle is in progress.
Memory Operation. The primary Flash memory
and secondary Flash memory are addressed
through the MCU Bus Interface. The MCU can ac-
cess these memories in one of two ways: The MCU can execute a typical bus WRITE or
READ operation just as it would if accessing a
RAM or ROM device using standard bus cycles. The MCU can execute a specific instruction that
consists of several WRITE and READ
operations. This involves writing specific data
patterns to special addresses within the Flash
memory to invoke an embedded algorithm.
These instructions are summarized in Table 7.
Typically, the MCU can read Flash memory using
READ operations, just as it would read a ROM de-
vice. However, Flash memory can only be altered
using specific Erase and Program instructions. For
example, the MCU cannot write a single byte di-
rectly to Flash memory as it would write a byte to
RAM. To program a byte into Flash memory, the
MCU must execute a Program instruction, then
test the status of the Program cycle. This status
test is achieved by a READ operation or polling
Ready/Busy (PC3).
Flash memory can also be read by using special
instructions to retrieve particular Flash device in-
formation (sector protect status and ID).
PSD834F2V16/95
Table 7. InstructionsNote:1. All bus cycles are WRITE bus cycles, except the ones with the “Read” label All values are in hexadecimal:
X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses
RA = Address of the memory location to be read
RD = Data read from location RA during the READ cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0).
PA is an even address for PSD in word programming mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be
erased, or verified, must be Active (High). Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft Express. Only address bits A11-A0 are used in instruction decoding. No Unlock or instruction cycles are required when the device is in the READ Mode The Reset instruction is required to return to the READ Mode after reading the Flash ID, or after reading the Sector Protection Sta-
tus, or if the Error Flag (DQ5/DQ13) Bit goes High. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80μs. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1,A0)=(1,0) The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass
mode.
11. The system may perform Read and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is
intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status
of the primary Flash memory.
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PSD834F2V
INSTRUCTIONSAn instruction consists of a sequence of specific
operations. Each received byte is sequentially de-
coded by the PSD and not executed as a standard
WRITE operation. The instruction is executed
when the correct number of bytes are properly re-
ceived and the time between two consecutive
bytes is shorter than the time-out period. Some in-
structions are structured to include READ opera-
tions after the initial WRITE operations.
The instruction must be followed exactly. Any in-
valid combination of instruction bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into READ
Mode (Flash memory is read like a ROM device).
The PSD supports the instructions summarized in
Table 7:
Flash memory: Erase memory by chip or sector Suspend or resume sector erase Program a Byte Reset to READ Mode Read primary Flash Identifier value Read Sector Protection Status Bypass
These instructions are detailed in Table 7. For ef-
ficient decoding of the instructions, the first two
bytes of an instruction are the coded cycles and
are followed by an instruction byte or confirmation
byte. The coded cycles consist of writing the data
AAh to address X555h during the first cycle and
data 55h to address XAAAh during the second cy-
cle. Address signals A15-A12 are Don’t Care dur-
ing the instruction WRITE cycles. However, the
appropriate Sector Select (FS0-FS7 or
CSBOOT0-CSBOOT3) must be selected.
The primary and secondary Flash memories have
the same instruction set (except for Read Primary
Flash Identifier). The Sector Select signals deter-
mine which Flash memory is to receive and exe-
cute the instruction. The primary Flash memory is
selected if any one of Sector Select (FS0-FS7) is
High, and the secondary Flash memory is selected
if any one of Sector Select (CSBOOT0-
CSBOOT3) is High.
Power-down Instruction and Power-up Mode
Power-up Mode. The PSD internal logic is reset
upon Power-up to the READ Mode. Sector Select
(FS0-FS7 and CSBOOT0-CSBOOT3) must be
held Low, and Write Strobe (WR, CNTL0) High,
during Power-up for maximum security of the data
contents and to remove the possibility of a byte be-
ing written on the first edge of Write Strobe (WR,
CNTL0). Any WRITE cycle initiation is locked
when VCC is below VLKO.
READUnder typical conditions, the MCU may read the
primary Flash memory or the secondary Flash
memory using READ operations just as it would a
ROM or RAM device. Alternately, the MCU may
use READ operations to obtain status information
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these memory blocks. The
following sections describe these READ functions.
Read Memory Contents. Primary Flash memory
and secondary Flash memory are placed in the
READ Mode after Power-up, chip reset, or a Reset
Flash instruction (see Table 7). The MCU can read
the memory contents of the primary Flash memory
or the secondary Flash memory by using READ
operations any time the READ operation is not
part of an instruction.
Read Primary Flash Identifier. The primary
Flash memory identifier is read with an instruction
composed of 4 operations: 3 specific WRITE oper-
ations and a READ operation (see Table 7). Dur-
ing the READ operation, address Bits A6, A1, and
A0 must be '0,' '0,' and '1,' respectively, and the ap-
propriate Sector Select (FS0-FS7) must be High.
The identifier for the device is E7h.
Read Memory Sector Protection Status. The
primary Flash memory Sector Protection Status is
read with an instruction composed of 4 operations:
3 specific WRITE operations and a READ opera-
tion (see Table 7). During the READ operation, ad-
dress Bits A6, A1, and A0 must be '0,' '1,' and '0,'
respectively, while Sector Select (FS0-FS7 or
CSBOOT0-CSBOOT3) designates the Flash
memory sector whose protection has to be veri-
fied. The READ operation produces 01h if the
Flash memory sector is protected, or 00h if the
sector is not protected.
The sector protection status for all NVM blocks
(primary Flash memory or secondary Flash mem-
ory) can also be read by the MCU accessing the
Flash Protection registers in PSD I/O space. See
the section entitled “Flash Memory Sector Pro-
tect”, on page 22, for register definitions.
PSD834F2V18/95
Reading the Erase/Program Status Bits. The
PSD provides several status bits to be used by the
MCU to confirm the completion of an Erase or Pro-
gram cycle of Flash memory. These status bits
minimize the time that the MCU spends perform-
ing these tasks and are defined in Table 8. The
status bits can be read as many times as needed.
For Flash memory, the MCU can perform a READ
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algorithm. See the section entitled
“Programming Flash Memory”, on page 19, for de-
tails.
Data Polling Flag (DQ7). When erasing or pro-
gramming in Flash memory, the Data Polling Flag
(DQ7) Bit outputs the complement of the bit being
entered for programming/writing on the DQ7 Bit.
Once the Program instruction or the WRITE oper-
ation is completed, the true logic value is read on
the Data Polling Flag (DQ7) Bit (in a READ opera-
tion). Data Polling is effective after the fourth WRITE
pulse (for a Program instruction) or after the
sixth WRITE pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memory sector being erased. During an Erase cycle, the Data Polling Flag
(DQ7) Bit outputs a '0.' After completion of the
cycle, the Data Polling Flag (DQ7) Bit outputs
the last bit programmed (it is a '1' after erasing). If the byte to be programmed is in a protected
Flash memory sector, the instruction is ignored. If all the Flash memory sectors to be erased are
protected, the Data Polling Flag (DQ7) Bit is
reset to '0' for about 100μs, and then returns to
the previous addressed byte. No erasure is
performed.
Toggle Flag (DQ6). The PSD offers another way
for determining when the Flash memory Program
cycle is completed. During the internal WRITE op-
eration and when either the FS0-FS7 or
CSBOOT0-CSBOOT3 is true, the Toggle Flag
(DQ6) Bit toggles from '0' to '1' and '1' to '0' on sub-
sequent attempts to read any byte of the memory.
When the internal cycle is complete, the toggling
stops and the data READ on the Data Bus D0-D7
is the addressed memory byte. The device is now
accessible for a new READ or WRITE operation.
The cycle is finished when two successive READs
yield the same output data. The Toggle Flag (DQ6) Bit is effective after the
fourth WRITE pulse (for a Program instruction)
or after the sixth WRITE pulse (for an Erase
instruction). If the byte to be programmed belongs to a
protected Flash memory sector, the instruction
is ignored. If all the Flash memory sectors selected for
erasure are protected, the Toggle Flag (DQ6)
Bit toggles to '0' for about 100μs and then
returns to the previous addressed byte.
Error Flag (DQ5). During a normal Program or
Erase cycle, the Error Flag (DQ5) Bit is to '0.' This
bit is set to '1' when there is a failure during Flash
memory Byte Program, Sector Erase, or Bulk
Erase cycle.
In the case of Flash memory programming, the Er-
ror Flag (DQ5) Bit indicates the attempt to program
a Flash memory bit from the programmed state,
'0,' to the erased state, '1,' which is not valid. The
Error Flag (DQ5) Bit may also indicate a Time-out
condition while attempting to program a byte.
In case of an error in a Flash memory Sector Erase
or Byte Program cycle, the Flash memory sector in
which the error occurred or to which the pro-
grammed byte belongs must no longer be used.
Other Flash memory sectors may still be used.
The Error Flag (DQ5) Bit is reset after a Reset
Flash instruction.
Erase Time-out Flag (DQ3). The Erase Time-
out Flag (DQ3) Bit reflects the time-out period al-
lowed between two consecutive Sector Erase in-
structions. The Erase Time-out Flag (DQ3) Bit is
reset to '0' after a Sector Erase cycle for a time pe-
riod of 100μs + 20% unless an additional Sector
Erase instruction is decoded. After this time peri-
od, or when the additional Sector Erase instruction
is decoded, the Erase Time-out Flag (DQ3) Bit is
set to '1.'
Table 8. Status BitNote:1. X = Not guaranteed value, can be read either 1 or 0. DQ7-DQ0 represent the Data Bus Bits, D7-D0. FS0-FS7 and CSBOOT0-CSBOOT3 are active High.
19/95
PSD834F2V
Programming Flash MemoryFlash memory must be erased prior to being pro-
grammed. A byte of Flash memory is erased to all
1s (FFh), and is programmed by setting selected
bits to '0.' The MCU may erase Flash memory all
at once or by-sector, but not byte-by-byte. Howev-
er, the MCU may program Flash memory byte-by-
byte.
The primary and secondary Flash memories re-
quire the MCU to send an instruction to program a
byte or to erase sectors (see Table 7).
Once the MCU issues a Flash memory Program or
Erase instruction, it must check for the status bits
for completion. The embedded algorithms that are
invoked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or Ready/Busy (PC3).
Data Polling. Polling on the Data Polling Flag
(DQ7) Bit is a method of checking whether a Pro-
gram or Erase cycle is in progress or has complet-
ed. Figure 4 shows the Data Polling algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the byte to be pro-
grammed in Flash memory to check status. The
Data Polling Flag (DQ7) Bit of this location be-
comes the complement of b7 of the original data
byte to be programmed. The MCU continues to
poll this location, comparing the Data Polling Flag
(DQ7) Bit and monitoring the Error Flag (DQ5) Bit.
When the Data Polling Flag (DQ7) Bit matches b7
of the original data, and the Error Flag (DQ5) Bit
remains '0,' the embedded algorithm is complete.
If the Error Flag (DQ5) Bit is '1,' the MCU should
test the Data Polling Flag (DQ7) Bit again since
the Data Polling Flag (DQ7) Bit may have changed
simultaneously with the Error Flag (DQ5) Bit (see
Figure 4).
The Error Flag (DQ5) Bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte or if the MCU at-
tempted to program a '1' to a bit that was not
erased (not erased is logic 0).
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
PSD834F2V20/95
The Error Flag (DQ5) Bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte, or if the MCU at-
tempted to program a '1' to a bit that was not
erased (not erased is logic '0').
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
byte that was written to Flash memory with the
byte that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 5 still applies. the Toggle Flag
(DQ6) Bit toggles until the Erase cycle is complete.
A 1 on the Error Flag (DQ5) Bit indicates a time-out
condition on the Erase cycle; a 0 indicates no er-
ror. The MCU can read any location within the sec-
tor being erased to get the Toggle Flag (DQ6) Bit
and the Error Flag (DQ5) Bit.
PSDsoft Express generates ANSI C code func-
tions which implement these Data Toggling algo-
rithms.
Unlock Bypass. The Unlock Bypass instructions
allow the system to program bytes to the Flash
memories faster than using the standard Program
instruction. The Unlock Bypass mode is entered
by first initiating two Unlock cycles. This is followed
by a third WRITE cycle containing the Unlock By-
pass code, 20h (as shown in Table 7).
The Flash memory then enters the Unlock Bypass
mode. A two-cycle Unlock Bypass Program in-
struction is all that is required to program in this
mode. The first cycle in this instruction contains
the Unlock Bypass Program code, A0h. The sec-
ond cycle contains the program address and data.
Additional data is programmed in the same man-
ner. These instructions dispense with the initial
two Unlock cycles required in the standard Pro-
gram instruction, resulting in faster total Flash
memory programming.
During the Unlock Bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset Flash
instructions are valid.
To exit the Unlock Bypass mode, the system must
issue the two-cycle Unlock Bypass Reset Flash in-
struction. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
Don’t Care for both cycles. The Flash memory
then returns to READ Mode.
21/95
PSD834F2V
Erasing Flash Memory
Flash Bulk Erase. The Flash Bulk Erase instruc-
tion uses six WRITE operations followed by a
READ operation of the status register, as de-
scribed in Table 7. If any byte of the Bulk Erase in-
struction is wrong, the Bulk Erase instruction
aborts and the device is reset to the Read Flash
memory status.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag (DQ5) Bit, the
Toggle Flag (DQ6) Bit, and the Data Polling Flag
(DQ7) Bit, as detailed in the section entitled “Pro-
gramming Flash Memory”, on page 19. The Error
Flag (DQ5) Bit returns a '1' if there has been an
Erase Failure (maximum number of Erase cycles
have been executed).
It is not necessary to program the memory with
00h because the PSD automatically does this be-
fore erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.
Flash Sector Erase. The Sector Erase instruc-
tion uses six WRITE operations, as described in
Table 7. Additional Flash Sector Erase codes and
Flash memory sector addresses can be written
subsequently to erase other Flash memory sec-
tors in parallel, without further coded cycles, if the
additional bytes are transmitted in a shorter time
than the time-out period of about 100μs. The input
of a new Sector Erase code restarts the time-out
period.
The status of the internal timer can be monitored
through the level of the Erase Time-out Flag (DQ3)
Bit. If the Erase Time-out Flag (DQ3) Bit is '0,' the
Sector Erase instruction has been received and
the time-out period is counting. If the Erase Time-
out Flag (DQ3) Bit is '1,' the time-out period has
expired and the PSD is busy erasing the Flash
memory sector(s). Before and during Erase time-
out, any instruction other than Suspend Sector
Erase and Resume Sector Erase instructions
abort the cycle that is currently in progress, and re-
set the device to READ Mode. It is not necessary
to program the Flash memory sector with 00h as
the PSD does this automatically before erasing
(byte=FFh).
During a Sector Erase, the memory status may be
checked by reading the Error Flag (DQ5) Bit, the
Toggle Flag (DQ6) Bit, and the Data Polling Flag
(DQ7) Bit, as detailed in the section entitled “Pro-
gramming Flash Memory”, on page 19.
During execution of the Erase cycle, the Flash
memory accepts only Reset and Suspend Sector
Erase instructions. Erasure of one Flash memory
sector may be suspended, in order to read data
from another Flash memory sector, and then re-
sumed.
Suspend Sector Erase. When a Sector Erase
cycle is in progress, the Suspend Sector Erase in-
struction can be used to suspend the cycle by writ-
ing 0B0h to any address when an appropriate
Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3)
is High. (See Table 7). This allows reading of data
from another Flash memory sector after the Erase
cycle has been suspended. Suspend Sector
Erase is accepted only during an Erase cycle and
defaults to READ Mode. A Suspend Sector Erase
instruction executed during an Erase time-out pe-
riod, in addition to suspending the Erase cycle, ter-
minates the time out period.
The Toggle Flag (DQ6) Bit stops toggling when the
PSD internal logic is suspended. The status of this
bit must be monitored at an address within the
Flash memory sector being erased. The Toggle
Flag (DQ6) Bit stops toggling between 0.1μs and
15μs after the Suspend Sector Erase instruction
has been executed. The PSD is then automatically
set to READ Mode.
If an Suspend Sector Erase instruction was exe-
cuted, the following rules apply: Attempting to read from a Flash memory sector
that was being erased outputs invalid data. Reading from a Flash sector that was not being
erased is valid. The Flash memory cannot be programmed, and
only responds to Resume Sector Erase and
Reset Flash instructions (READ is an operation
and is allowed). If a Reset Flash instruction is received, data in
the Flash memory sector that was being erased
is invalid.
Resume Sector Erase. If a Suspend Sector
Erase instruction was previously executed, the
erase cycle may be resumed with this instruction.
The Resume Sector Erase instruction consists of
writing 030h to any address while an appropriate
Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3)
is High. (See Table 7.)
PSD834F2V22/95
Specific Features
Flash Memory Sector Protect. Each primary
and secondary Flash memory sector can be sepa-
rately protected against Program and Erase cy-
cles. Sector Protection provides additional data
security because it disables all Program or Erase
cycles. This mode can be activated through the
JTAG Port or a Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft Express Configuration pro-
gram. This automatically protects selected sectors
when the device is programmed through the JTAG
Port or a Device Programmer. Flash memory sec-
tors can be unprotected to allow updating of their
contents using the JTAG Port or a Device Pro-
grammer. The MCU can read (but cannot change)
the sector protection bits.
Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a READ of the protected data.
This allows a guarantee of the retention of the Pro-
tection status.
The sector protection status can be read by the
MCU through the Flash memory protection and
PSD/EE protection registers (in the CSIOP block).
See Table 9 and Table 10.
Table 9. Sector Protection/Security Bit Definition – Flash Protection RegisterNote:1. Bit Definitions:
Sec_Prot 1 = Primary Flash memory or secondary Flash memory Sector is write protected.
Sec_Prot 0 = Primary Flash memory or secondary Flash memory Sector is not write protected.
Table 10. Sector Protection/Security Bit Definition – PSD/EE Protection RegisterNote:1. Bit Definitions:
Sec_Prot 1 = Secondary Flash memory Sector is write protected.
Sec_Prot 0 = Secondary Flash memory Sector is not write protected.
Security_Bit 0 = Security Bit in device has not been set.1 = Security Bit in device has been set.
Reset Flash. The Reset Flash instruction con-
sists of one WRITE cycle (see Table 7). It can also
be optionally preceded by the standard two
WRITE decoding cycles (writing AAh to 555h and
55h to AAAh). It must be executed after: Reading the Flash Protection Status or Flash ID An Error condition has occurred (and the device
has set the Error Flag Bit (DQ5) to '1') during a
Flash memory Program or Erase cycle.
The Reset Flash instruction puts the Flash memo-
ry back into normal READ Mode. If an Error condi-
tion has occurred (and the device has set the Error
Flag Bit (DQ5) to '1') the Flash memory is put back
into normal READ Mode within 25 μs of the Reset
Flash instruction having been issued. The Reset
Flash instruction is ignored when it is issued dur-
ing a Program or Bulk Erase cycle of the Flash
memory. The Reset Flash instruction aborts any
on-going Sector Erase cycle, and returns the
Flash memory to the normal READ Mode within μs.
Reset (RESET) Signal. A pulse on Reset (RE-
SET) aborts any cycle that is in progress, and re-
sets the Flash memory to the READ Mode. When
the reset occurs during a Program or Erase cycle,
the Flash memory takes up to 25 μs to return to
the READ Mode. It is recommended that the Reset
(RESET) pulse (except for Power On Reset, as
described on page 61) be at least 25 μs so that the
Flash memory is always ready for the MCU to
fetch the bootstrap instructions after the Reset cy-
cle is complete.
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PSD834F2V
SRAMThe SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to two product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to Voltage Stand-by (VSTBY, PC2). If you have an
external battery connected to the PSD, the con-
tents of the SRAM are retained in the event of a
power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at V or greater. If the supply voltage falls below the
battery voltage, an internal power switch-over to
the battery occurs.
PC4 can be configured as an output that indicates
when power is being drawn from the external bat-
tery. Battery-on Indicator (VBATON, PC4) is High
with the supply voltage falls below the battery volt-
age and the battery on Voltage Stand-by (VSTBY,
PC2) is supplying power to the internal SRAM.
SRAM Select (RS0), Voltage Stand-by (VSTBY,
PC2) and Battery-on Indicator (VBATON, PC4)
are all configured using PSDsoft Express Configu-
ration.
Sector Select and SRAM SelectSector Select (FS0-FS7, CSBOOT0-CSBOOT3)
and SRAM Select (RS0) are all outputs of the
DPLD. They are setup by writing equations for
them in PSDabel. The following rules apply to the
equations for these signals: Primary Flash memory and secondary Flash
memory Sector Select signals must not be
larger than the physical sector size. Any primary Flash memory sector must not be
mapped in the same memory space as another
Flash memory sector. A secondary Flash memory sector must not be
mapped in the same memory space as another
secondary Flash memory sector. SRAM, I/O, and Peripheral I/O spaces must not
overlap. A secondary Flash memory sector may overlap
a primary Flash memory sector. In case of
PSD834F2V24/95
Memory Select Configuration for MCUs with
Separate Program and Data Spaces. The 8031
and compatible family of MCUs, which includes
the 80C51, 80C151, 80C251, and 80C51XA, have
separate address spaces for Program memory
(selected using Program Select Enable (PSEN,
CNTL2)) and Data memory (selected using Read
Strobe (RD, CNTL1)). Any of the memories within
the PSD can reside in either space or both spaces.
This is controlled through manipulation of the VM
register that resides in the CSIOP space.
The VM register is set using PSDsoft Express to
have an initial value. It can subsequently be
changed by the MCU so that memory mapping
can be changed on-the-fly.
For example, you may wish to have SRAM and pri-
mary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the primary and
secondary Flash memories. This is easily done
with the VM register by using PSDsoft Express
Configuration to configure it for Boot-up and hav-
ing the MCU change it when desired.
Table 11 describes the VM Register.
Table 11. VM Register
Configuration Modes for MCUs with Separate
Program and Data Spaces. Separate Space
Modes. Program space is separated from Data
space. For example, Program Select Enable
(PSEN, CNTL2) is used to access the program
code from the primary Flash memory, while Read
Strobe (RD, CNTL1) is used to access data from
the secondary Flash memory, SRAM and I/O Port
blocks. This configuration requires the VM register
to be set to 0Ch (see Figure 7).
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PSD834F2V
Combined Space Modes. The Program and
Data spaces are combined into one memory
space that allows the primary Flash memory, sec-
ondary Flash memory, and SRAM to be accessed
by either Program Select Enable (PSEN, CNTL2)
or Read Strobe (RD, CNTL1). For example, to
configure the primary Flash memory in Combined
space, Bits b2 and b4 of the VM register are set to
1 (see Figure 8).
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Page RegisterThe 8-bit Page Register increases the addressing
capability of the MCU by a factor of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0-
PGR7) are inputs to the DPLD decoder and can be
included in the Sector Select (FS0-FS7,
CSBOOT0-CSBOOT3), and SRAM Select (RS0)
equations.
If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic. See Application Note AN1154.
Figure 9 shows the Page Register. The eight flip-
flops in the register are connected to the internal
data bus D0-D7. The MCU can write to or read
from the Page Register. The Page Register can be
accessed at address location CSIOP + E0h.
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PSD834F2V
PLDSThe PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
using the PSDabel tool in PSDsoft Express, the
logic is programmed into the device and available
upon Power-up.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in the section entitled “Decode
PLD (DPLD)”, on page 29, and the section entitled
“Complex PLD (CPLD)”, also on page 30. Figure
10 shows the configuration of the PLDs.
The DPLD performs address decoding for Select
signals for internal components, such as memory,
registers, and I/O ports.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0-
ECS2) signals.
The AND Array is used to form product terms.
These product terms are specified using PSDabel.
An Input Bus consisting of 73 signals is connected
to the PLDs. The signals are shown in Table 12.
The Turbo Bit in PSDThe PLDs in the PSD can minimize power con-
sumption by switching off when inputs remain un-
changed for an extended time of about 70ns.
Resetting the Turbo Bit to '0' (Bit 3 of PMMR0) au-
tomatically places the PLDs into standby if no in-
puts are changing. Turning the Turbo mode off
increases propagation delays while reducing pow-
er consumption. See the section entitled “POWER
MANAGEMENT”, on page 56, on how to set the
Turbo Bit.
Additionally, five bits are available in PMMR2 to
block MCU control signals from entering the PLDs.
This reduces power consumption and can be used
only when these MCU control signals are not used
in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
Table 12. DPLD and CPLD InputsNote:1. The address inputs are A19-A4 in 80C51XA mode.
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PSD834F2V
Decode PLD (DPLD)The DPLD, shown in Figure 11, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals: 8 Sector Select (FS0-FS7) signals for the
primary Flash memory (three product terms
each) 4 Sector Select (CSBOOT0-CSBOOT3) signals
for the secondary Flash memory (three product
terms each) 1 internal SRAM Select (RS0) signal (two
product terms) 1 internal CSIOP Select (PSD Configuration
Register) signal 1 JTAG Select signal (enables JTAG on Port C) 2 internal Peripheral Select signals
(Peripheral I/O mode).
PSD834F2V30/95
Complex PLD (CPLD)The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate three External Chip Se-
lect (ECS0-ECS2), routed to Port D.
Although External Chip Select (ECS0-ECS2) can
be produced by any Output Macrocell (OMC),
these three External Chip Select (ECS0-ECS2) on
Port D do not consume any Output Macrocells
(OMC).
As shown in Figure 10, the CPLD has the following
blocks: 24 Input Macrocells (IMC) 16 Output Macrocells (OMC) Macrocell Allocator Product Term Allocator AND Array capable of generating up to 137
product terms Four I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
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Output Macrocell (OMC)Eight of the Output Macrocells (OMC) are con-
nected to Ports A and B pins and are named as
McellAB0-McellAB7. The other eight macrocells
are connected to Ports B and C pins and are
named as McellBC0-McellBC7. If an McellAB out-
put is not assigned to a specific pin in PSDabel,
the Macrocell Allocator block assigns it to either
Port A or B. The same is true for a McellBC output
on Port B or C. Table 13 shows the macrocells and
port assignment.
The Output Macrocell (OMC) architecture is
shown in Figure 13. As shown in the figure, there
are native product terms available from the AND
Array, and borrowed product terms available (if
unused) from other Output Macrocells (OMC). The
polarity of the product term is controlled by the
XOR gate. The Output Macrocell (OMC) can im-
plement either sequential logic, using the flip-flop
element, or combinatorial logic. The multiplexer
selects between the sequential or combinatorial
logic outputs. The multiplexer output can drive a
port pin and has a feedback path to the AND Array
inputs.
The flip-flop in the Output Macrocell (OMC) block
can be configured as a D, T, JK, or SR type in the
PSDabel program. The flip-flop’s clock, preset,
and clear inputs may be driven from a product
term of the AND Array. Alternatively, CLKIN (PD1)
can be used for the clock input to the flip-flop. The
flip-flop is clocked on the rising edge of CLKIN
(PD1). The preset and clear are active High inputs.
Each clear input can use up to two product terms.
Table 13. Output Macrocell Port and Data Bit Assignments
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PSD834F2V
Product Term AllocatorThe CPLD has a Product Term Allocator. The PS-
Dabel compiler uses the Product Term Allocator to
borrow and place product terms from one macro-
cell to another. The following list summarizes how
product terms are allocated: McellAB0-McellAB7 all have three native
product terms and may borrow up to six more McellBC0-McellBC3 all have four native product
terms and may borrow up to five more McellBC4-McellBC7 all have four native product
terms and may borrow up to six more.
Each macrocell may only borrow product terms
from certain other macrocells. Product terms al-
ready in use by one macrocell are not available for
another macrocell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required, which consume other Output Macro-
cells (OMC). If external product terms are used,
extra delay is added for the equation that required
the extra product terms.
This is called product term expansion. PSDsoft
Express performs this expansion as needed.
Loading and Reading the Output Macrocells
(OMC). The Output Macrocells (OMC) block oc-
cupies a memory location in the MCU address
space, as defined by the CSIOP block (see the
section entitled “I/O PORTS”, on page 46). The
flip-flops in each of the 16 Output Macrocells
(OMC) can be loaded from the data bus by a MCU.
Loading the Output Macrocells (OMC) with data
from the MCU takes priority over internal func-
tions. As such, the preset, clear, and clock inputs
to the flip-flop can be overridden by the MCU. The
ability to load the flip-flops and read them back is
useful in such applications as loadable counters
and shift registers, mailboxes, and handshaking
protocols.
Data can be loaded to the Output Macrocells
(OMC) on the trailing edge of Write Strobe (WR,
CNTL0) (edge loading) or during the time that
Write Strobe (WR, CNTL0) is active (level load-
ing). The method of loading is specified in PSDsoft
Express Configuration.
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PSD834F2V
The OMC Mask Register. There is one Mask
Register for each of the two groups of eight Output
Macrocells (OMC). The Mask Registers can be
used to block the loading of data to individual Out-
put Macrocells (OMC). The default value for the
Mask Registers is 00h, which allows loading of the
Output Macrocells (OMC). When a given bit in a
Mask Register is set to a 1, the MCU is blocked
from writing to the associated Output Macrocells
(OMC). For example, suppose McellAB0-
McellAB3 are being used for a state machine. You
would not want an MCU WRITE to McellAB to
overwrite the state machine registers. Therefore,
you would want to load the Mask Register for
McellAB (Mask Macrocell AB) with the value 0Fh.
The Output Enable of the OMC. The Output
Macrocells (OMC) block can be connected to an I/
O port pin as a PLD output. The output enable of
each port pin driver is controlled by a single prod-
uct term from the AND Array, OR’ed with the Di-
rection Register output. The pin is enabled upon
Power-up if no output enable equation is defined
and if the pin is declared as a PLD output in PSD-
soft Express.
If the Output Macrocell (OMC) output is declared
as an internal node and not as a port pin output in
the PSDabel file, the port pin can be used for other
I/O functions. The internal node feedback can be
routed as an input to the AND Array.
Input Macrocells (IMC)The CPLD has 24 Input Macrocells (IMC), one for
each pin on Ports A, B, and C. The architecture of
the Input Macrocells (IMC) is shown in Figure 14.
The Input Macrocells (IMC) are individually config-
urable, and can be used as a latch, register, or to
pass incoming Port signals prior to driving them
onto the PLD input bus. The outputs of the Input
Macrocells (IMC) can be read by the MCU through
the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND Array or the
MCU Address Strobe (ALE/AS). Each product
term output is used to latch or clock four Input
Macrocells (IMC). Port inputs 3-0 can be con-
trolled by one product term and 7-4 by another.
Configurations for the Input Macrocells (IMC) are
specified by equations written in PSDabel (see Ap-
plication Note AN1171). Outputs of the Input Mac-
rocells (IMC) can be read by the MCU via the IMC
buffer. See the section entitled “I/O PORTS”, on
page 46.
Input Macrocells (IMC) can use Address Strobe
(ALE/AS, PD0) to latch address bits higher than
A15. Any latched addresses are routed to the
PLDs as inputs.
Input Macrocells (IMC) are particularly useful with
handshaking communication applications where
two processors pass data back and forth through
a common mailbox. Figure 15 shows a typical con-
figuration where the Master MCU writes to the Port
A Data Out Register. This, in turn, can be read by
the Slave MCU via the activation of the “Slave-
Read” output enable product term.
The Slave can also write to the Port A Input Mac-
rocells (IMC) and the Master can then read the In-
put Macrocells (IMC) directly.
Note that the “Slave-Read” and “Slave-Wr” signals
are product terms that are derived from the Slave
MCU inputs Read Strobe (RD, CNTL1), Write
Strobe (WR, CNTL0), and Slave_CS.
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PSD834F2V
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MCU BUS INTERFACEThe “no-glue logic” MCU Bus Interface block can
be directly connected to most popular MCUs and
their control signals. Key 8-bit MCUs, with their
bus types and control signals, are shown in Table
14. The interface type is specified using the PSD-
soft Express Configuration.
PSD Interface to a Multiplexed 8-Bit Bus. Fig-
ure 16 shows an example of a system using a
MCU with an 8-bit multiplexed bus and a PSD. The
ADIO port on the PSD is connected directly to the
MCU address/data bus. Address Strobe (ALE/AS,
PD0) latches the address signals internally.
Latched addresses can be brought out to Port A or
B. The PSD drives the ADIO data bus only when
one of its internal resources is accessed and Read
Strobe (RD, CNTL1) is active. Should the system
address bus exceed sixteen bits, Ports A, B, C, or
D may be used as additional address inputs.
Table 14. MCUs and their Control SignalsNote:1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PC7, PD0, PA3-0) can be configured for other I/O func-
tions. ALE/AS input is optional for MCUs with a non-multiplexed bus
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PSD834F2V
PSD834F2V40/95
PSD Interface to a Non-Multiplexed 8-bit Bus.Figure 17 shows an example of a system using a
MCU with an 8-bit non-multiplexed bus and a
PSD. The address bus is connected to the ADIO
Port, and the data bus is connected to Port A. Port
A is in tri-state mode when the PSD is not access-
ed by the MCU. Should the system address bus
exceed sixteen bits, Ports B, C, or D may be used
for additional address inputs.
Data Byte Enable Reference. MCUs have differ-
ent data byte orientations. Table 15 shows how
the PSD interprets byte/word operations in differ-
ent bus WRITE configurations. Even-byte refers to
locations with address A0 equal to 0 and odd byte
as locations with A0 equal to 1.
Table 15. 8-bit Data Bus
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PSD834F2V
MCU Bus Interface ExamplesFigure 18 to Figure 21 show examples of the basic
connections between the PSD and some popular
MCUs. The PSD Control input pins are labeled as
to the MCU function for which they are configured.
The MCU bus interface is specified using the PS-
Dsoft Express Configuration.
80C31. Figure 18 shows the bus interface for the
80C31, which has an 8-bit multiplexed address/
data bus. The lower address byte is multiplexed
with the data bus. The MCU control signals Pro-
gram Select Enable (PSEN, CNTL2), Read Strobe
(RD, CNTL1), and Write Strobe (WR, CNTL0) may
be used for accessing the internal memory and I/
O Ports blocks. Address Strobe (ALE/AS, PD0)
latches the address.
80C251. The Intel 80C251 MCU features a user-
configurable bus interface with four possible bus
configurations, as shown in Table 16.
PSD834F2V42/95
The first configuration is 80C31 compatible, and
the bus interface to the PSD is identical to that
shown in Figure 18. The second and third configu-
rations have the same bus connection as shown in
Figure 17. There is only one Read Strobe (PSEN)
connected to CNTL1 on the PSD. The A16 con-
nection to PA0 allows for a larger address input to
the PSD. The fourth configuration is shown in Fig-
ure 19. Read Strobe (RD) is connected to CNTL1
and Program Select Enable (PSEN) is connected
to CNTL2.
The 80C251 has two major operating modes:
Page mode and Non-page mode. In Non-page
mode, the data is multiplexed with the lower ad-
dress byte, and Address Strobe (ALE/AS, PD0) is
active in every bus cycle. In Page mode, data (D7-
D0) is multiplexed with address (A15-A8). In a bus
cycle where there is a Page hit, Address Strobe
(ALE/AS, PD0) is not active and only addresses
(A7-A0) are changing. The PSD supports both
modes. In Page Mode, the PSD bus timing is iden-
tical to Non-Page Mode except the address hold
time and setup time with respect to Address
Strobe (ALE/AS, PD0) is not required. The PSD
access time is measured from address (A7-A0)
valid to data in valid.
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PSD834F2V
PSD834F2V44/95
80C51XA. The Philips 80C51XA MCU family sup-
ports an 8- or 16-bit multiplexed bus that can have
burst cycles. Address bits (A3-A0) are not multi-
plexed, while (A19-A4) are multiplexed with data
bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-
A4) are multiplexed with data bits (D7-D0).
The 80C51XA can be configured to operate in 8-
bit data mode (as shown in Figure 20).
The 80C51XA improves bus throughput and per-
formance by executing burst cycles for code fetch-
es. In Burst Mode, address A19-A4 are latched
internally by the PSD, while the 80C51XA changes
the A3-A0 signals to fetch up to 16 bytes of code.
The PSD access time is then measured from ad-
dress A3-A0 valid to data in valid. The PSD bus
timing requirement in Burst Mode is identical to the
normal bus cycle, except the address setup and
hold time with respect to Address Strobe (ALE/AS,
PD0) does not apply.
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PSD834F2V
68HC11. Figure 21 shows a bus interface to a
68HC11 where the PSD is configured in 8-bit mul-
tiplexed mode with E and R/W settings. The DPLD
can be used to generate the READ and WR sig-
nals for external devices.
PSD834F2V46/95
I/O PORTSThere are four programmable I/O ports: Ports A, B,
C, and D. Each of the ports is eight bits except Port
D, which is 3 bits. Each port pin is individually user
configurable, thus allowing multiple functions per
port. The ports are configured using PSDsoft Ex-
press Configuration or by the MCU writing to on-
chip registers in the CSIOP space.
The topics discussed in this section are: General Port architecture Port operating modes Port Configuration Registers (PCR) Port Data Registers Individual Port functionality.
General Port ArchitectureThe general architecture of the I/O Port block is
shown in Figure 22. Individual Port architectures
are shown in Figure 24 to Figure 27. In general,
once the purpose for a port pin has been defined,
that pin is no longer available for other purposes.
Exceptions are noted.
As shown in Figure 22, the ports contain an output
multiplexer whose select signals are driven by the
configuration bits in the Control Registers (Ports A
and B only) and PSDsoft Express Configuration.
Inputs to the multiplexer include the following: Output data from the Data Out register Latched address outputs CPLD macrocell output External Chip Select (ECS0-ECS2) from the
CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and macrocell outputs, Direc-
tion and Control Registers, and port pin input are
all connected to the Port Data Buffer (PDB).
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PSD834F2VThe Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is not defined as a CPLD output
in the PSDabel file, then the Direction Register has
sole control of the buffer that drives the port pin.
The contents of these registers can be altered by
the MCU. The Port Data Buffer (PDB) feedback
path allows the MCU to check the contents of the
registers.
Ports A, B, and C have embedded Input Macro-
cells (IMC). The Input Macrocells (IMC) can be
configured as latches, registers, or direct inputs to
the PLDs. The latches and registers are clocked
by Address Strobe (ALE/AS, PD0) or a product
term from the PLD AND Array. The outputs from
the Input Macrocells (IMC) drive the PLD input bus
and can be read by the MCU. See the section en-
titled “Input Macrocell”, on page 36.
Port Operating ModesThe I/O Ports have several modes of operation.
Some modes can be defined using PSDabel,
some by the MCU writing to the Control Registers
in CSIOP space, and some by both. The modes
that can only be defined using PSDsoft Express
must be programmed into the device and cannot
be changed unless the device is reprogrammed.
The modes that can be changed by the MCU can
be done so dynamically at run-time. The PLD I/O,
Data Port, Address Input, and Peripheral I/O
modes are the only modes that must be defined
before programming the device. All other modes
can be changed by the MCU at run-time. See Ap-
plication Note AN1171 for more detail.
Table 18 summarizes which modes are available
on each port. Table 21 shows how and where the
different modes are configured. Each of the port
operating modes are described in the following
sections.
MCU I/O ModeIn the MCU I/O mode, the MCU uses the I/O Ports
block to expand its own I/O ports. By setting up the
CSIOP space, the ports on the PSD are mapped
into the MCU address space. The addresses of
the ports are listed in Table 6.
A port pin can be put into MCU I/O mode by writing
a 0 to the corresponding bit in the Control Regis-
ter. The MCU I/O direction may be changed by
writing to the corresponding bit in the Direction
Register, or by the output enable product term.
See the section entitled “Peripheral I/O Mode”, on
page 49. When the pin is configured as an output,
the content of the Data Out Register drives the pin.
When configured as an input, the MCU can read
the port input through the Data In buffer. See Fig-
ure 22.
Ports C and D do not have Control Registers, and
are in MCU I/O mode by default. They can be used
for PLD I/O if equations are written for them in PS-
Dabel.
PLD I/O ModeThe PLD I/O Mode uses a port as an input to the
CPLD’s Input Macrocells (IMC), and/or as an out-
put from the CPLD’s Output Macrocells (OMC).
The output can be tri-stated with a control signal.
This output enable control signal can be defined
by a product term from the PLD, or by resetting the
corresponding bit in the Direction Register to 0.
The corresponding bit in the Direction Register
must not be set to 1 if the pin is defined for a PLD
input signal in PSDabel. The PLD I/O mode is
specified in PSDabel by declaring the port pins,
and then writing an equation assigning the PLD I/
O to a port.
Address Out ModeFor MCUs with a multiplexed address/data bus,
Address Out Mode can be used to drive latched
addresses on to the port pins. These port pins can,
in turn, drive external devices. Either the output
enable or the corresponding bits of both the Direc-
tion Register and Control Register must be set to
a 1 for pins to use Address Out Mode. This must
be done by the MCU at run-time. See Table 20 for
the address output pin assignments on Ports A
and B for various MCUs.
For non-multiplexed 8-bit bus mode, address sig-
nals (A7-A0) are available to Port B in Address Out
Mode.
Note: Do not drive address signals with AddressOut Mode to an external memory device if it is in-
tended for the MCU to Boot from the external de-
vice. The MCU must first Boot from PSD memory
so the Direction and Control register bits can be
set.
PSD834F2V48/95
Table 18. Port Operating ModesNote:1. Can be multiplexed with other I/O functions.
Table 19. Port Operating Mode SettingsNote:1. N/A = Not Applicable The direction of the Port A,B,C, and D pins are controlled by the Direction Register OR’ed with the individual output enable product
term (.oe) from the CPLD AND Array. Any of these three methods enables the JTAG pins on Port C.
