PSD813F2-A-70J-PSD813F2A-70J-PSD813F2-A-90J-PSD813F2A-90J-PSD813F2-A-90JI-PSD813F2A-90JI-PSD813F2-A-90M-PSD813F2A-90MI-PSD833F2-90M-PSD834F2-70J-PSD834F2-70M-PSD834F2-90M-PSD834F2-90MI-PSD853F2-90M-PSD854F2-70M-PSD854F2-90M-PSD854F2-90MI Fast Delivery |IC PHOENIX CO.,LIMITED

PSD813F2A-90MI ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5VFEATURES SUMMARY . . . . . 1SUMMARY DESCRIPTION . . . 6PIN DESCRIPTION 10PSD A ..
PSD813F2V-A-15J ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 3.3VPSD813F2V, PSD833F2VPSD853F2V, PSD854F2VFlash In-System Programmable (ISP)Peripherals for 8-bit MCU ..
PSD813F2VA-15J ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 3.3VFEATURES SUMMARY■ FLASH IN-SYSTEM PROGRAMMABLE (ISP) Figure 1. PackagesPERIPHERAL FOR 8-BIT MCUS■ D ..
PSD813F2V-A-15M ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 3.3VFEATURES SUMMARY . . . . . 1SUMMARY DESCRIPTION . . . 6PIN DESCRIPTION 10PSD A ..
PSD813F4-15J , Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F4A-90M , Flash In-System Programmable ISP Peripherals For 8-bit MCUs
QL16X24B-1PL84C , pASIC 1 Family Very-High-Speed CMOS FPGA
QL16X24B-1PL84C , pASIC 1 Family Very-High-Speed CMOS FPGA
QL2003-1PF144C , 3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility
QL2003-1PF144C , 3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility
QL2007-0PF144C , 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility
QL2007-0PF144C , 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility

PSD813F2-A-70J-PSD813F2A-70J-PSD813F2-A-90J-PSD813F2A-90J-PSD813F2-A-90JI-PSD813F2A-90JI-PSD813F2-A-90M-PSD813F2A-90MI-PSD833F2-90M-PSD834F2-70J-PSD834F2-70M-PSD834F2-90M-PSD834F2-90MI-PSD853F2-90M-PSD854F2-70M-PSD854F2-90M-PSD854F2-90MI
Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
1/110
PRELIMINARY DATA
June 2004
PSD813F2, PSD833F2
PSD834F2, PSD853F2, PSD854F2
Flash In-System Programmable (ISP)
Peripherals for 8-bit MCUs, 5V
FEATURES SUMMARY FLASH IN-SYSTEM PROGRAMMABLE (ISP)
PERIPHERAL FOR 8-BIT MCUS DUAL BANK FLASH MEMORIES UP TO 2 Mbit OF PRIMARY FLASH
MEMORY (8 Uniform Sectors, 32K x8) UP TO 256 Kbit SECONDARY FLASH
MEMORY (4 Uniform Sectors) Concurrent operation: READ from one
memory while erasing and writing the
other UP TO 256 Kbit BATTERY-BACKED SRAM 27 RECONFIGURABLE I/O PORTS ENHANCED JTAG SERIAL PORT PLD WITH MACROCELLS Over 3000 Gates of PLD: CPLD and
DPLD CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs) DPLD - user defined internal chip select
decoding 27 INDIVIDUALLY CONFIGURABLE I/O
PORT PINS
The can be used for the following functions: MCU I/Os
–PLD I/Os Latched MCU address output Special function I/Os. 16 of the I/O ports may be configured as
open-drain outputs. IN-SYSTEM PROGRAMMING (ISP) WITH
JTAG Built-in JTAG compliant serial port allows
full-chip In-System Programmability Efficient manufacturing allow easy
product testing and programming Use low cost FlashLINK cable with PC PAGE REGISTER Internal page register that can be used to
expand the microcontroller address space
by a factor of 256 PROGRAMMABLE POWER MANAGEMENT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PSD Register Description and Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . .20
Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Read Primary Flash Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Reading the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Data Polling Flag (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Toggle Flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Error Flag (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Erase Time-out Flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Unlock Bypass (PSD833F2x, PSD834F2x, PSD853F2x, PSD854F2x). . . . . . . . . . . . . . . . . . . .26
ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Flash Memory Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Reset (RESET) Signal (on the PSD83xF2 and PSD85xF2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
SECTOR SELECT AND SRAM SELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Memory Select Configuration for MCUs with Separate Program and Data Spaces . . . . . . . .30
Configuration Modes for MCUs with Separate Program and Data Spaces . . . . . . . . . . . . . . .30
PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Loading and Reading the Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
PSD Interface to a Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
PSD Interface to a Non-Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Data Byte Enable Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
MCU Bus Interface Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
80C51XA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
I/O PORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
General Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Port Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Peripheral I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Drive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
OMC Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Ports A and B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Port C – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Port D – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .63
For Users of the HC11 (or compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Power-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Reset of Flash Memory Erase and Program Cycles (on the PSD834Fx) . . . . . . . . . . . . . . . . .67
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . .69
Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
JTAG Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
APPENDIX A.PQFP52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
APPENDIX B.PLCC52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
APPENDIX C.TQFP64 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
SUMMARY DESCRIPTION
The PSD8XXFX family of memory systems for mi-
crocontrollers (MCUs) brings In-System-Program-
mability (ISP) to Flash memory and programmable
logic. The result is a simple and flexible solution for
embedded designs. PSD devices combine many
of the peripheral functions found in MCU based
applications.
Table 1 summarizes all the devices in the
PSD834F2, PSD853F2, PSD854F2.
The CPLD in the PSD devices features an opti-
mized macrocell logic architecture. The PSD mac-
rocell was created to address the unique
requirements of embedded system designs. It al-
lows direct connection between the system ad-
dress/data bus, and the internal PSD registers, to
simplify communication between the MCU and
other supporting devices.
The PSD device includes a JTAG Serial Program-
ming interface, to allow In-System Programming
(ISP) of the entire device. This feature reduces de-
velopment time, simplifies the manufacturing flow,
and dramatically lowers the cost of field upgrades.
Using ST’s special Fast-JTAG programming, a de-
sign can be rapidly programmed into the PSD in as
little as seven seconds.
The innovative PSD8XXFX family solves key
problems faced by designers when managing dis-
crete Flash memory devices, such as: First-time In-System Programming (ISP) Complex address decoding Simultaneous read and write to the device.
The JTAG Serial Interface block allows In-System
Programming (ISP), and eliminates the need for
an external Boot EPROM, or an external program-
mer. To simplify Flash memory updates, program
execution is performed from a secondary Flash
memory while the primary Flash memory is being
updated. This solution avoids the complicated
hardware and software overhead necessary to im-
plement IAP.
ST makes available a software development tool,
PSDsoft Express, that generates ANSI-C compli-
ant code for use with your target MCU. This code
allows you to manipulate the non-volatile memory
(NVM) within the PSD. Code examples are also
provided for: Flash memory IAP via the UART of the host
MCU Memory paging to execute code across
several PSD memory pages Loading, reading, and manipulation of PSD
macrocells by the MCU.
Table 1. Product Range
Note:1. All products support: JTAG serial ISP, MCU parallel ISP, ISP Flash memory, ISP CPLD, Security features, Power Management
Unit (PMU), Automatic Power-down (APD) SRAM may be backed up using an external battery.
7/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
9/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PIN DESCRIPTION
Table 2. Pin Description (for the PLCC52 package - Note 1)
11/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
13/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Note:1. The pin numbers in this table are for the PLCC package only. See the package information from Table 74., page 102 onwards, for
pin numbers on other package types. These functions can be multiplexed with other functions.
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
15/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PSD ARCHITECTURAL OVERVIEW
PSD devices contain several major functional
blocks. Figure 5 shows the architecture of the PSD
device family. The functions of each block are de-
scribed briefly in the following sections. Many of
the blocks perform multiple functions and are user
configurable.
Memory
Each of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discus-
sion can be found in the section entitled Memory
Blocks, page 19.
The 1 Mbit or 2 Mbit (128K x 8, or 256K x 8) Flash
memory is the primary memory of the PSD. It is di-
vided into 8 equally-sized sectors that are individ-
ually selectable.
The optional 256 Kbit (32K x 8) secondary Flash
memory is divided into 4 equally-sized sectors.
Each sector is individually selectable.
The optional SRAM is intended for use as a
scratch-pad memory or as an extension to the
MCU SRAM. If an external battery is connected to
Voltage Stand-by (VSTBY, PC2), data is retained in
the event of power failure.
Each sector of memory can be located in a differ-
ent address space as defined by the user. The ac-
cess times for all memory types includes the
address latching and DPLD decoding time.
Page Register
The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or in-
ternal memory and I/O. The Page Register can
also be used to change the address mapping of
sectors of the Flash memories into different mem-
ory spaces for IAP.
PLDs
The device contains two PLDs, the Decode PLD
(DPLD) and the Complex PLD (CPLD), as shown
in Table 3, each optimized for a different function.
The functional partitioning of the PLDs reduces
power consumption, optimizes cost/performance,
and eases design entry.
The DPLD is used to decode addresses and to
generate Sector Select signals for the PSD inter-
nal memory and registers. The DPLD has combi-
natorial outputs. The CPLD has 16 Output
Macrocells (OMC) and 3 combinatorial outputs.
The PSD also has 24 Input Macrocells (IMC) that
can be configured as inputs to the PLDs. The
PLDs receive their inputs from the PLD Input Bus
and are differentiated by their output destinations,
number of product terms, and macrocells.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo Bit in PMMR0 and other bits in the
PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD propaga-
tion time when invoking the power management
features.
I/O Ports
The PSD has 27 individually configurable I/O pins
distributed over the four ports (Port A, B, C, and
D). Each I/O pin can be individually configured for
different functions. Ports can be configured as
standard MCU I/O ports, PLD I/O, or latched ad-
dress outputs for MCUs using multiplexed ad-
dress/data buses.
The JTAG pins can be enabled on Port C for In-
System Programming (ISP).
Ports A and B can also be configured as a data
port for a non-multiplexed bus.
MCU Bus Interface
PSD interfaces easily with most 8-bit MCUs that
have either multiplexed or non-multiplexed ad-
dress/data buses. The device is configured to re-
spond to the MCU’s control signals, which are also
used as inputs to the PLDs. For examples, please
see the section entitled MCU Bus Interface
Examples, page 45.
Table 3. PLD I/O
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
JTAG Port
In-System Programming (ISP) can be performed
through the JTAG signals on Port C. This serial in-
terface allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port C. Table 4 indicates the
JTAG pin assignments.
In-System Programming (ISP)
Using the JTAG signals on Port C, the entire PSD
device can be programmed or erased without the
use of the MCU. The primary Flash memory can
also be programmed in-system by the MCU exe-
cuting the programming algorithms out of the sec-
ondary memory, or SRAM. The secondary
memory can be programmed the same way by ex-
ecuting out of the primary Flash memory. The PLD
or other PSD Configuration blocks can be pro-
grammed through the JTAG port or a device pro-
grammer. Table 5 indicates which programming
methods can program different functional blocks
of the PSD.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The Turbo Bit in PMMR0 can be
reset to '0' and the CPLD latches its outputs and
goes to sleep until the next transition on its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. Please see the sec-
tion entitled POWER MANAGEMENT, page 62 for
more details.
Table 4. JTAG SIgnals on Port C
Table 5. Methods of Programming Different Functional Blocks of the PSD
17/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
DEVELOPMENT SYSTEM
The PSD8XXFX family is supported by PSDsoft
Express, a Windows-based software development
tool. A PSD design is quickly and easily produced
in a point and click environment. The designer
does not need to enter Hardware Description Lan-
guage (HDL) equations, unless desired, to define
PSD pin functions and memory map information.
The general design flow is shown in Figure 6. PS-
Dsoft Express is available from our web site (the
address is given on the back page of this data
sheet) or other distribution channels.
PSDsoft Express directly supports two low cost
device programmers form ST: PSDpro and
FlashLINK (JTAG). Both of these programmers
may be purchased through your local distributor/
representative, or directly from our web site using
a credit card. The PSD is also supported by third
party device programmers. See our web site for
the current list.
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PSD REGISTER DESCRIPTION AND ADDRESS OFFSET
Table 6 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al-
located by the user to the internal PSD registers.
Table 7 provides brief descriptions of the registers
in CSIOP space. The following section gives a
more detailed description.
Table 6. I/O Port Latched Address Output Assignments (Note1)
Note:1. See the section entitled I/O PORTS, page 51, on how to enable the Latched Address Output function. N/A = Not Applicable
Table 7. Register Address Offset
Note:1. Other registers that are not part of the I/O ports.
19/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
DETAILED OPERATION
As shown in Figure 5., page 14, the PSD consists
of six major types of functional blocks: Memory Blocks PLD Blocks MCU Bus Interface I/O Ports Power Management Unit (PMU) JTAG Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
Memory Blocks
The PSD has the following memory blocks: Primary Flash memory Optional Secondary Flash memory Optional SRAM
The Memory Select signals for these blocks origi-
nate from the Decode PLD (DPLD) and are user-
defined in PSDsoft Express.
Table 8. Memory Block Size and Organization
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Primary Flash Memory and Secondary Flash
memory Description
The primary Flash memory is divided evenly into
eight equal sectors. The secondary Flash memory
is divided into four equal sectors. Each sector of
either memory block can be separately protected
from Program and Erase cycles.
Flash memory may be erased on a sector-by-sec-
tor basis. Flash sector erasure may be suspended
while data is read from other sectors of the block
and then resumed after reading.
During a Program or Erase cycle in Flash memory,
the status can be output on Ready/Busy (PC3).
This pin is set up using PSDsoft Express Configu-
ration.
Memory Block Select Signals
The DPLD generates the Select signals for all the
internal memory blocks (see the section entitled
PLDS, page 33). Each of the eight sectors of the
primary Flash memory has a Select signal (FS0-
FS7) which can contain up to three product terms.
Each of the four sectors of the secondary Flash
memory has a Select signal (CSBOOT0-
CSBOOT3) which can contain up to three product
terms. Having three product terms for each Select
signal allows a given sector to be mapped in differ-
ent areas of system memory. When using a MCU
with separate Program and Data space, these
flexible Select signals allow dynamic re-mapping
of sectors from one memory space to the other.
Ready/Busy (PC3). This signal can be used to
output the Ready/Busy status of the PSD. The out-
put on Ready/Busy (PC3) is a 0 (Busy) when Flash
memory is being written to, or when Flash memory
is being erased. The output is a 1 (Ready) when
no WRITE or Erase cycle is in progress.
Memory Operation. The primary Flash memory
and secondary Flash memory are addressed
through the MCU Bus Interface. The MCU can ac-
cess these memories in one of two ways: The MCU can execute a typical bus WRITE or
READ operation just as it would if accessing a
RAM or ROM device using standard bus
cycles. The MCU can execute a specific instruction
that consists of several WRITE and READ
operations. This involves writing specific data
patterns to special addresses within the Flash
memory to invoke an embedded algorithm.
These instructions are summarized in Table
9., page 21.
Typically, the MCU can read Flash memory using
READ operations, just as it would read a ROM de-
vice. However, Flash memory can only be altered
using specific Erase and Program instructions. For
example, the MCU cannot write a single byte di-
rectly to Flash memory as it would write a byte to
RAM. To program a byte into Flash memory, the
MCU must execute a Program instruction, then
test the status of the Program cycle. This status
test is achieved by a READ operation or polling
Ready/Busy (PC3).
Flash memory can also be read by using special
instructions to retrieve particular Flash device in-
formation (sector protect status and ID).
21/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Table 9. Instructions
Note:1. All bus cycles are WRITE bus cycles, except the ones with the “READ” label All values are in hexadecimal:
X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses
RA = Address of the memory location to be read
RD = Data read from location RA during the READ cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0).
PA is an even address for PSD in word programming mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be
erased, or verified, must be Active (High). Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft Express. Only address bits A11-A0 are used in instruction decoding. No Unlock or instruction cycles are required when the device is in the READ Mode The Reset instruction is required to return to the READ Mode after reading the Flash ID, or after reading the Sector Protection Sta-
tus, or if the Error Flag Bit (DQ5/DQ13) goes High. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1,A0)=(1,0) The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass
mode.
11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is
intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status
of the primary Flash memory.
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
INSTRUCTIONS
An instruction consists of a sequence of specific
operations. Each received byte is sequentially de-
coded by the PSD and not executed as a standard
WRITE operation. The instruction is executed
when the correct number of bytes are properly re-
ceived and the time between two consecutive
bytes is shorter than the time-out period. Some in-
structions are structured to include READ opera-
tions after the initial WRITE operations.
The instruction must be followed exactly. Any in-
valid combination of instruction bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into READ
Mode (Flash memory is read like a ROM device).
The PSD supports the instructions summarized in
Table 9., page 21:
Flash memory: Erase memory by chip or sector Suspend or resume sector erase Program a Byte Reset to READ Mode Read primary Flash Identifier value Read Sector Protection Status Bypass (on the PSD833F2, PSD834F2,
PSD853F2 and PSD854F2)
These instructions are detailed in Table
9., page 21. For efficient decoding of the instruc-
tions, the first two bytes of an instruction are the
coded cycles and are followed by an instruction
byte or confirmation byte. The coded cycles con-
sist of writing the data AAh to address X555h dur-
ing the first cycle and data 55h to address XAAAh
during the second cycle. Address signals A15-A12
are Don’t Care during the instruction WRITE cy-
cles. However, the appropriate Sector Select
(FS0-FS7 or CSBOOT0-CSBOOT3) must be se-
lected.
The primary and secondary Flash memories have
the same instruction set (except for Read Primary
Flash Identifier). The Sector Select signals deter-
mine which Flash memory is to receive and exe-
cute the instruction. The primary Flash memory is
selected if any one of Sector Select (FS0-FS7) is
High, and the secondary Flash memory is selected
if any one of Sector Select (CSBOOT0-
CSBOOT3) is High.
Power-up Mode
The PSD internal logic is reset upon Power-up to
the READ Mode. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must be held Low, and
Write Strobe (WR, CNTL0) High, during Power-up
for maximum security of the data contents and to
remove the possibility of a byte being written on
the first edge of Write Strobe (WR, CNTL0). Any
WRITE cycle initiation is locked when VCC is be-
low VLKO.
READ
Under typical conditions, the MCU may read the
primary Flash memory or the secondary Flash
memory using READ operations just as it would a
ROM or RAM device. Alternately, the MCU may
use READ operations to obtain status information
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these memory blocks. The
following sections describe these READ functions.
Read Memory Contents
Primary Flash memory and secondary Flash
memory are placed in the READ Mode after Pow-
er-up, chip reset, or a Reset Flash instruction (see
Table 9., page 21). The MCU can read the memo-
ry contents of the primary Flash memory or the
secondary Flash memory by using READ opera-
tions any time the READ operation is not part of an
instruction.
Read Primary Flash Identifier
The primary Flash memory identifier is read with
an instruction composed of 4 operations: 3 specific
WRITE operations and a READ operation (see Ta-
ble 9., page 21). During the READ operation, ad-
dress bits A6, A1, and A0 must be '0,0,1,'
respectively, and the appropriate Sector Select
(FS0-FS7) must be High. The identifier for the
PSD813F2/3/4/5 is E4h, and for the PSD83xF2 or
PSD85xF2 it is E7h.
Read Memory Sector Protection Status
The primary Flash memory Sector Protection Sta-
tus is read with an instruction composed of 4 oper-
ations: 3 specific WRITE operations and a READ
operation (see Table 9., page 21). During the
READ operation, address Bits A6, A1, and A0
must be '0,1,0,' respectively, while Sector Select
(FS0-FS7 or CSBOOT0-CSBOOT3) designates
the Flash memory sector whose protection has to
be verified. The READ operation produces 01h if
the Flash memory sector is protected, or 00h if the
sector is not protected.
The sector protection status for all NVM blocks
(primary Flash memory or secondary Flash mem-
ory) can also be read by the MCU accessing the
Flash Protection registers in PSD I/O space. See
the section entitled Flash Memory Sector
Protect, page 28 for register definitions.
23/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Reading the Erase/Program Status Bits
The PSD provides several status bits to be used
by the MCU to confirm the completion of an Erase
or Program cycle of Flash memory. These status
bits minimize the time that the MCU spends per-
forming these tasks and are defined in Table 10.
The status bits can be read as many times as
needed.
For Flash memory, the MCU can perform a READ
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algorithm. See the section entitled
PROGRAMMING FLASH MEMORY, page 25 for
details.
Table 10. Status Bit
Note:1. X = Not guaranteed value, can be read either '1' or ’0.’ DQ7-DQ0 represent the Data Bus bits, D7-D0. FS0-FS7 and CSBOOT0-CSBOOT3 are active High.
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Data Polling Flag (DQ7)
When erasing or programming in Flash memory,
the Data Polling Flag Bit (DQ7) outputs the com-
plement of the bit being entered for programming/
writing on the DQ7 Bit. Once the Program instruc-
tion or the WRITE operation is completed, the true
logic value is read on the Data Polling Flag Bit
(DQ7, in a READ operation). Data Polling is effective after the fourth WRITE
pulse (for a Program instruction) or after the
sixth WRITE pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memory sector being erased. During an Erase cycle, the Data Polling Flag
Bit (DQ7) outputs a ’0.’ After completion of the
cycle, the Data Polling Flag Bit (DQ7) outputs
the last bit programmed (it is a '1' after
erasing). If the byte to be programmed is in a protected
Flash memory sector, the instruction is
ignored. If all the Flash memory sectors to be erased
are protected, the Data Polling Flag Bit (DQ7)
is reset to '0' for about 100µs, and then returns
to the previous addressed byte. No erasure is
performed.
Toggle Flag (DQ6)
The PSD offers another way for determining when
the Flash memory Program cycle is completed.
During the internal WRITE operation and when ei-
ther the FS0-FS7 or CSBOOT0-CSBOOT3 is true,
the Toggle Flag Bit (DQ6) toggles from '0' to '1' and
'1' to '0' on subsequent attempts to read any byte
of the memory.
When the internal cycle is complete, the toggling
stops and the data read on the Data Bus D0-D7 is
the addressed memory byte. The device is now
accessible for a new READ or WRITE operation.
The cycle is finished when two successive READs
yield the same output data. The Toggle Flag Bit (DQ6) is effective after the
fourth WRITE pulse (for a Program instruction)
or after the sixth WRITE pulse (for an Erase
instruction). If the byte to be programmed belongs to a
protected Flash memory sector, the
instruction is ignored. If all the Flash memory sectors selected for
erasure are protected, the Toggle Flag Bit
(DQ6) toggles to '0' for about 100µs and then
returns to the previous addressed byte.
Error Flag (DQ5)
During a normal Program or Erase cycle, the Error
Flag Bit (DQ5) is to ’0.’ This bit is set to '1' when
there is a failure during Flash memory Byte Pro-
gram, Sector Erase, or Bulk Erase cycle.
In the case of Flash memory programming, the Er-
ror Flag Bit (DQ5) indicates the attempt to program
a Flash memory bit from the programmed state,
’0,’ to the erased state, '1,' which is not valid. The
Error Flag Bit (DQ5) may also indicate a Time-out
condition while attempting to program a byte.
In case of an error in a Flash memory Sector Erase
or Byte Program cycle, the Flash memory sector in
which the error occurred or to which the pro-
grammed byte belongs must no longer be used.
Other Flash memory sectors may still be used.
The Error Flag Bit (DQ5) is reset after a Reset
Flash instruction.
Erase Time-out Flag (DQ3)
The Erase Time-out Flag Bit (DQ3) reflects the
time-out period allowed between two consecutive
Sector Erase instructions. The Erase Time-out
Flag Bit (DQ3) is reset to '0' after a Sector Erase
cycle for a time period of 100µs + 20% unless an
additional Sector Erase instruction is decoded. Af-
ter this time period, or when the additional Sector
Erase instruction is decoded, the Erase Time-out
Flag Bit (DQ3) is set to '1.'
25/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PROGRAMMING FLASH MEMORY
Flash memory must be erased prior to being pro-
grammed. A byte of Flash memory is erased to all
1s (FFh), and is programmed by setting selected
bits to ’0.’ The MCU may erase Flash memory all
at once or by-sector, but not byte-by-byte. Howev-
er, the MCU may program Flash memory byte-by-
byte.
The primary and secondary Flash memories re-
quire the MCU to send an instruction to program a
byte or to erase sectors (see Table 9., page 21).
Once the MCU issues a Flash memory Program or
Erase instruction, it must check for the status bits
for completion. The embedded algorithms that are
invoked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or Ready/Busy (PC3).
Data Polling
Polling on the Data Polling Flag Bit (DQ7) is a
method of checking whether a Program or Erase
cycle is in progress or has completed. Figure 7
shows the Data Polling algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the byte to be pro-
grammed in Flash memory to check status. The
Data Polling Flag Bit (DQ7) of this location be-
comes the complement of b7 of the original data
byte to be programmed. The MCU continues to
poll this location, comparing the Data Polling Flag
Bit (DQ7) and monitoring the Error Flag Bit (DQ5).
When the Data Polling Flag Bit (DQ7) matches b7
of the original data, and the Error Flag Bit (DQ5)
remains ’0,’ the embedded algorithm is complete.
If the Error Flag Bit (DQ5) is '1,' the MCU should
test the Data Polling Flag Bit (DQ7) again since
the Data Polling Flag Bit (DQ7) may have changed
simultaneously with the Error Flag Bit (DQ5, see
Figure 7).
The Error Flag Bit (DQ5) is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte or if the MCU at-
tempted to program a '1' to a bit that was not
erased (not erased is logic '0').
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Data Toggle
Checking the Toggle Flag Bit (DQ6) is a method of
determining whether a Program or Erase cycle is
in progress or has completed. Figure 8 shows the
Data Toggle algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the byte to be pro-
grammed in Flash memory to check status. The
Toggle Flag Bit (DQ6) of this location toggles each
time the MCU reads this location until the embed-
ded algorithm is complete. The MCU continues to
read this location, checking the Toggle Flag Bit
(DQ6) and monitoring the Error Flag Bit (DQ5).
When the Toggle Flag Bit (DQ6) stops toggling
(two consecutive reads yield the same value), and
the Error Flag Bit (DQ5) remains ’0,’ the embed-
ded algorithm is complete. If the Error Flag Bit
(DQ5) is '1,' the MCU should test the Toggle Flag
Bit (DQ6) again, since the Toggle Flag Bit (DQ6)
may have changed simultaneously with the Error
Flag Bit (DQ5, see Figure 8).
The Error Flag Bit (DQ5) is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte, or if the MCU at-
tempted to program a '1' to a bit that was not
erased (not erased is logic '0').
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
byte that was written to Flash memory with the
byte that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 8 still applies. the Toggle Flag
Bit (DQ6) toggles until the Erase cycle is complete.
A '1' on the Error Flag Bit (DQ5) indicates a time-
out condition on the Erase cycle; a '0' indicates no
error. The MCU can read any location within the
sector being erased to get the Toggle Flag Bit
(DQ6) and the Error Flag Bit (DQ5).
PSDsoft Express generates ANSI C code func-
tions which implement these Data Toggling algo-
rithms.
Unlock Bypass (PSD833F2x, PSD834F2x,
PSD853F2x, PSD854F2x)
The Unlock Bypass instructions allow the system
to program bytes to the Flash memories faster
than using the standard Program instruction. The
Unlock Bypass mode is entered by first initiating
two Unlock cycles. This is followed by a third
WRITE cycle containing the Unlock Bypass code,
20h (as shown in Table 9., page 21).
27/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
ERASING FLASH MEMORY
Flash Bulk Erase
The Flash Bulk Erase instruction uses six WRITE
operations followed by a READ operation of the
status register, as described in Table 9., page 21.
If any byte of the Bulk Erase instruction is wrong,
the Bulk Erase instruction aborts and the device is
reset to the Read Flash memory status.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5), the
Toggle Flag Bit (DQ6), and the Data Polling Flag
Bit (DQ7), as detailed in the section entitled PRO-
GRAMMING FLASH MEMORY, page 25. The Er-
ror Flag Bit (DQ5) returns a '1' if there has been an
Erase Failure (maximum number of Erase cycles
have been executed).
It is not necessary to program the memory with
00h because the PSD automatically does this be-
fore erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.
Flash Sector Erase
The Sector Erase instruction uses six WRITE op-
erations, as described in Table 9., page 21. Addi-
tional Flash Sector Erase codes and Flash
memory sector addresses can be written subse-
quently to erase other Flash memory sectors in
parallel, without further coded cycles, if the addi-
tional bytes are transmitted in a shorter time than
the time-out period of about 100µs. The input of a
new Sector Erase code restarts the time-out peri-
od.
The status of the internal timer can be monitored
through the level of the Erase Time-out Flag Bit
(DQ3). If the Erase Time-out Flag Bit (DQ3) is ’0,’
the Sector Erase instruction has been received
and the time-out period is counting. If the Erase
Time-out Flag Bit (DQ3) is '1,' the time-out period
has expired and the PSD is busy erasing the Flash
memory sector(s). Before and during Erase time-
out, any instruction other than Suspend Sector
Erase and Resume Sector Erase instructions
abort the cycle that is currently in progress, and re-
set the device to READ Mode. It is not necessary
to program the Flash memory sector with 00h as
the PSD does this automatically before erasing
(byte = FFh).
During a Sector Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5), the
Toggle Flag Bit (DQ6), and the Data Polling Flag
Bit (DQ7), as detailed in the section entitled PRO-
GRAMMING FLASH MEMORY, page 25.
During execution of the Erase cycle, the Flash
memory accepts only Reset and Suspend Sector
Erase instructions. Erasure of one Flash memory
sector may be suspended, in order to read data
from another Flash memory sector, and then re-
sumed.
Suspend Sector Erase
When a Sector Erase cycle is in progress, the Sus-
pend Sector Erase instruction can be used to sus-
pend the cycle by writing 0B0h to any address
when an appropriate Sector Select (FS0-FS7 or
CSBOOT0-CSBOOT3) is High. (See Table
9., page 21). This allows reading of data from an-
other Flash memory sector after the Erase cycle
has been suspended. Suspend Sector Erase is
accepted only during an Erase cycle and defaults
to READ Mode. A Suspend Sector Erase instruc-
tion executed during an Erase time-out period, in
addition to suspending the Erase cycle, terminates
the time out period.
The Toggle Flag Bit (DQ6) stops toggling when the
PSD internal logic is suspended. The status of this
bit must be monitored at an address within the
Flash memory sector being erased. The Toggle
Flag Bit (DQ6) stops toggling between 0.1µs and
15µs after the Suspend Sector Erase instruction
has been executed. The PSD is then automatically
set to READ Mode.
If an Suspend Sector Erase instruction was exe-
cuted, the following rules apply: Attempting to read from a Flash memory
sector that was being erased outputs invalid
data. Reading from a Flash sector that was not
being erased is valid. The Flash memory cannot be programmed,
and only responds to Resume Sector Erase
and Reset Flash instructions (READ is an
operation and is allowed). If a Reset Flash instruction is received, data in
the Flash memory sector that was being
erased is invalid.
Resume Sector Erase
If a Suspend Sector Erase instruction was previ-
ously executed, the erase cycle may be resumed
with this instruction. The Resume Sector Erase in-
struction consists of writing 030h to any address
while an appropriate Sector Select (FS0-FS7 or
CSBOOT0-CSBOOT3) is High. (See Table
9., page 21.)
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
SPECIFIC FEATURES
Flash Memory Sector Protect
Each primary and secondary Flash memory sector
can be separately protected against Program and
Erase cycles. Sector Protection provides addition-
al data security because it disables all Program or
Erase cycles. This mode can be activated through
the JTAG Port or a Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft Express Configuration pro-
gram. This automatically protects selected sectors
when the device is programmed through the JTAG
Port or a Device Programmer. Flash memory sec-
tors can be unprotected to allow updating of their
contents using the JTAG Port or a Device Pro-
grammer. The MCU can read (but cannot change)
the sector protection bits.
Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a READ of the protected data.
This allows a guarantee of the retention of the Pro-
tection status.
The sector protection status can be read by the
MCU through the Flash memory protection and
PSD/EE protection registers (in the CSIOP block).
See Tables 11 and 12.
Reset Flash
The Reset Flash instruction consists of one
WRITE cycle (see Table 9., page 21). It can also
be optionally preceded by the standard two
WRITE decoding cycles (writing AAh to 555h and
55h to AAAh). It must be executed after: Reading the Flash Protection Status or Flash An Error condition has occurred (and the
device has set the Error Flag Bit (DQ5) to '1')
during a Flash memory Program or Erase
cycle.
On the PSD813F2/3/4/5, the Reset Flash instruc-
tion puts the Flash memory back into normal
READ Mode. It may take the Flash memory up to
a few milliseconds to complete the Reset cycle.
The Reset Flash instruction is ignored when it is is-
sued during a Program or Bulk Erase cycle of the
Flash memory. The Reset Flash instruction aborts
any on-going Sector Erase cycle, and returns the
Flash memory to the normal READ Mode within a
few milliseconds.
On the PSD83xF2 or PSD85xF2, the Reset Flash
instruction puts the Flash memory back into nor-
mal READ Mode. If an Error condition has oc-
curred (and the device has set the Error Flag Bit
(DQ5) to '1') the Flash memory is put back into nor-
mal READ Mode within 25µs of the Reset Flash in-
struction having been issued. The Reset Flash
instruction is ignored when it is issued during a
Program or Bulk Erase cycle of the Flash memory.
The Reset Flash instruction aborts any on-going
Sector Erase cycle, and returns the Flash memory
to the normal READ Mode within 25µs.
Reset (RESET) Signal (on the PSD83xF2 and
PSD85xF2)
A pulse on Reset (RESET) aborts any cycle that is
in progress, and resets the Flash memory to the
READ Mode. When the reset occurs during a Pro-
gram or Erase cycle, the Flash memory takes up
to 25µs to return to the READ Mode. It is recom-
mended that the Reset (RESET) pulse (except for
Power On Reset, as described on RESET TIMING
AND DEVICE STATUS AT RESET, page 67) be
at least 25µ s so that the Flash memory is always
ready for the MCU to fetch the bootstrap instruc-
tions after the Reset cycle is complete.
Table 11. Sector Protection/Security Bit Definition – Flash Protection Register
Note:1. Bit Definitions:
Sec_Prot 1 = Primary Flash memory or secondary Flash memory Sector is write protected.
Sec_Prot 0 = Primary Flash memory or secondary Flash memory Sector is not write protected.
Table 12. Sector Protection/Security Bit Definition – PSD/EE Protection Register
Note:1. Bit Definitions:
Sec_Prot 1 = Secondary Flash memory Sector is write protected.
Sec_Prot 0 = Secondary Flash memory Sector is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
29/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to two product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to Voltage Stand-by (VSTBY, PC2). If you have an
external battery connected to the PSD, the con-
tents of the SRAM are retained in the event of a
power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at V or greater. If the supply voltage falls below the
battery voltage, an internal power switch-over to
the battery occurs.
PC4 can be configured as an output that indicates
when power is being drawn from the external bat-
tery. Battery-on Indicator (VBATON, PC4) is High
with the supply voltage falls below the battery volt-
age and the battery on Voltage Stand-by (VSTBY,
PC2) is supplying power to the internal SRAM.
SRAM Select (RS0), Voltage Stand-by (VSTBY,
PC2) and Battery-on Indicator (VBATON, PC4)
are all configured using PSDsoft Express Configu-
ration.
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
SECTOR SELECT AND SRAM SELECT
Sector Select (FS0-FS7, CSBOOT0-CSBOOT3)
and SRAM Select (RS0) are all outputs of the
DPLD. They are setup by writing equations for
them in PSDabel. The following rules apply to the
equations for these signals: Primary Flash memory and secondary Flash
memory Sector Select signals must not be
larger than the physical sector size. Any primary Flash memory sector must not be
mapped in the same memory space as
another Flash memory sector. A secondary Flash memory sector must not be
mapped in the same memory space as
another secondary Flash memory sector. SRAM, I/O, and Peripheral I/O spaces must
not overlap. A secondary Flash memory sector may
overlap a primary Flash memory sector. In
case of overlap, priority is given to the
secondary Flash memory sector. SRAM, I/O, and Peripheral I/O spaces may
overlap any other memory sector. Priority is
given to the SRAM, I/O, or Peripheral I/O.
Example
FS0 is valid when the address is in the range of
8000h to BFFFh, CSBOOT0 is valid from 8000h to
9FFFh, and RS0 is valid from 8000h to 87FFh.
Any address in the range of RS0 always accesses
the SRAM. Any address in the range of CSBOOT0
greater than 87FFh (and less than 9FFFh) auto-
matically addresses secondary Flash memory
segment 0. Any address greater than 9FFFh ac-
cesses the primary Flash memory segment 0. You
can see that half of the primary Flash memory seg-
ment 0 and one-fourth of secondary Flash memory
segment 0 cannot be accessed in this example.
Also note that an equation that defined FS1 to any-
where in the range of 8000h to BFFFh would not
be valid.
Figure 9 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not overlap. Level one has the highest priority and
level 3 has the lowest.
Memory Select Configuration for MCUs with
Separate Program and Data Spaces
The 8031 and compatible family of MCUs, which
includes the 80C51, 80C151, 80C251, and
80C51XA, have separate address spaces for Pro-
gram memory (selected using Program Select En-
able (PSEN, CNTL2)) and Data memory (selected
using Read Strobe (RD, CNTL1)). Any of the
memories within the PSD can reside in either
space or both spaces.
31/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PAGE REGISTER
The 8-bit Page Register increases the addressing
capability of the MCU by a factor of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0-
PGR7) are inputs to the DPLD decoder and can be
included in the Sector Select (FS0-FS7,
CSBOOT0-CSBOOT3), and SRAM Select (RS0)
equations.
If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic. See Application Note AN1154.
Figure 12 shows the Page Register. The eight flip-
flops in the register are connected to the internal
data bus D0-D7. The MCU can write to or read
from the Page Register. The Page Register can be
accessed at address location CSIOP + E0h.
33/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PLDS
The PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
using the PSDabel tool in PSDsoft Express, the
logic is programmed into the device and available
upon Power-up.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in the section entitled Decode
PLD (DPLD), page 35 and the section entitled
Complex PLD (CPLD), page 36. Figure
13., page 34 shows the configuration of the PLDs.
The DPLD performs address decoding for Select
signals for internal components, such as memory,
registers, and I/O ports.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0-
ECS2) signals.
The AND Array is used to form product terms.
These product terms are specified using PSDabel.
An Input Bus consisting of 73 signals is connected
to the PLDs. The signals are shown in Table 14.
The Turbo Bit in PSD
The PLDs in the PSD can minimize power con-
sumption by switching off when inputs remain un-
changed for an extended time of about 70ns.
Resetting the Turbo Bit to '0' (Bit 3 of PMMR0) au-
tomatically places the PLDs into standby if no in-
puts are changing. Turning the Turbo mode off
increases propagation delays while reducing pow-
er consumption. See the section entitled POWER
MANAGEMENT, page 62 on how to set the Turbo
Bit.
Additionally, five bits are available in PMMR2 to
block MCU control signals from entering the PLDs.
This reduces power consumption and can be used
only when these MCU control signals are not used
in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
Table 14. DPLD and CPLD Inputs
Note:1. The address inputs are A19-A4 in 80C51XA mode.
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
35/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Decode PLD (DPLD)
The DPLD, shown in Figure 14, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals: 8 Sector Select (FS0-FS7) signals for the
primary Flash memory (three product terms
each) 4 Sector Select (CSBOOT0-CSBOOT3)
signals for the secondary Flash memory (three
product terms each) 1 internal SRAM Select (RS0) signal (two
product terms) 1 internal CSIOP Select (PSD Configuration
Register) signal 1 JTAG Select signal (enables JTAG on Port 2 internal Peripheral Select signals
(Peripheral I/O mode).
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate three External Chip Se-
lect (ECS0-ECS2), routed to Port D.
Although External Chip Select (ECS0-ECS2) can
be produced by any Output Macrocell (OMC),
these three External Chip Select (ECS0-ECS2) on
Port D do not consume any Output Macrocells
(OMC).
As shown in Figure 13., page 34, the CPLD has
the following blocks: 24 Input Macrocells (IMC) 16 Output Macrocells (OMC) Macrocell Allocator Product Term Allocator AND Array capable of generating up to 137
product terms Four I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
37/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Output Macrocell (OMC)
Eight of the Output Macrocells (OMC) are con-
nected to Ports A and B pins and are named as
McellAB0-McellAB7. The other eight macrocells
are connected to Ports B and C pins and are
named as McellBC0-McellBC7. If an McellAB out-
put is not assigned to a specific pin in PSDabel,
the Macrocell Allocator block assigns it to either
Port A or B. The same is true for a McellBC output
on Port B or C. Table 15 shows the macrocells and
port assignment.
The Output Macrocell (OMC) architecture is
shown in Figure 16., page 39. As shown in the fig-
ure, there are native product terms available from
the AND Array, and borrowed product terms avail-
able (if unused) from other Output Macrocells
(OMC). The polarity of the product term is con-
trolled by the XOR gate. The Output Macrocell
(OMC) can implement either sequential logic, us-
ing the flip-flop element, or combinatorial logic.
The multiplexer selects between the sequential or
combinatorial logic outputs. The multiplexer output
can drive a port pin and has a feedback path to the
AND Array inputs.
The flip-flop in the Output Macrocell (OMC) block
can be configured as a D, T, JK, or SR type in the
PSDabel program. The flip-flop’s clock, preset,
and clear inputs may be driven from a product
term of the AND Array. Alternatively, CLKIN (PD1)
can be used for the clock input to the flip-flop. The
flip-flop is clocked on the rising edge of CLKIN
(PD1). The preset and clear are active High inputs.
Each clear input can use up to two product terms.
Table 15. Output Macrocell Port and Data Bit Assignments
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Product Term Allocator
The CPLD has a Product Term Allocator. The PS-
Dabel compiler uses the Product Term Allocator to
borrow and place product terms from one macro-
cell to another. The following list summarizes how
product terms are allocated: McellAB0-McellAB7 all have three native
product terms and may borrow up to six more McellBC0-McellBC3 all have four native
product terms and may borrow up to five more McellBC4-McellBC7 all have four native
product terms and may borrow up to six more.
Each macrocell may only borrow product terms
from certain other macrocells. Product terms al-
ready in use by one macrocell are not available for
another macrocell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required, which consume other Output Macro-
cells (OMC). If external product terms are used,
extra delay is added for the equation that required
the extra product terms.
This is called product term expansion. PSDsoft
Express performs this expansion as needed.
Loading and Reading the Output Macrocells
(OMC)
The Output Macrocells (OMC) block occupies a
memory location in the MCU address space, as
defined by the CSIOP block (see the section enti-
tled I/O PORTS, page 51). The flip-flops in each of
the 16 Output Macrocells (OMC) can be loaded
from the data bus by a MCU. Loading the Output
Macrocells (OMC) with data from the MCU takes
priority over internal functions. As such, the preset,
clear, and clock inputs to the flip-flop can be over-
ridden by the MCU. The ability to load the flip-flops
and read them back is useful in such applications
as loadable counters and shift registers, mailbox-
es, and handshaking protocols.
Data can be loaded to the Output Macrocells
(OMC) on the trailing edge of Write Strobe (WR,
CNTL0) (edge loading) or during the time that
Write Strobe (WR, CNTL0) is active (level load-
ing). The method of loading is specified in PSDsoft
Express Configuration.
The OMC Mask Register
There is one Mask Register for each of the two
groups of eight Output Macrocells (OMC). The
Mask Registers can be used to block the loading
of data to individual Output Macrocells (OMC).
The default value for the Mask Registers is 00h,
which allows loading of the Output Macrocells
(OMC). When a given bit in a Mask Register is set
to a 1, the MCU is blocked from writing to the as-
sociated Output Macrocells (OMC). For example,
suppose McellAB0-McellAB3 are being used for a
state machine. You would not want a MCU write to
McellAB to overwrite the state machine registers.
Therefore, you would want to load the Mask Reg-
ister for McellAB (Mask Macrocell AB) with the val-
ue 0Fh.
The Output Enable of the OMC
The Output Macrocells (OMC) block can be con-
nected to an I/O port pin as a PLD output. The out-
put enable of each port pin driver is controlled by
a single product term from the AND Array, ORed
with the Direction Register output. The pin is en-
abled upon Power-up if no output enable equation
is defined and if the pin is declared as a PLD out-
put in PSDsoft Express.
If the Output Macrocell (OMC) output is declared
as an internal node and not as a port pin output in
the PSDabel file, the port pin can be used for other
I/O functions. The internal node feedback can be
routed as an input to the AND Array.
39/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Input Macrocells (IMC)
The CPLD has 24 Input Macrocells (IMC), one for
each pin on Ports A, B, and C. The architecture of
the Input Macrocells (IMC) is shown in Figure
17., page 41. The Input Macrocells (IMC) are indi-
vidually configurable, and can be used as a latch,
register, or to pass incoming Port signals prior to
driving them onto the PLD input bus. The outputs
of the Input Macrocells (IMC) can be read by the
MCU through the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND Array or the
MCU Address Strobe (ALE/AS). Each product
term output is used to latch or clock four Input
Macrocells (IMC). Port inputs 3-0 can be con-
trolled by one product term and 7-4 by another.
Configurations for the Input Macrocells (IMC) are
specified by equations written in PSDabel (see Ap-
plication Note AN1171). Outputs of the Input Mac-
rocells (IMC) can be read by the MCU via the IMC
buffer. See the section entitled I/O
PORTS, page 51.
Input Macrocells (IMC) can use Address Strobe
(ALE/AS, PD0) to latch address bits higher than
A15. Any latched addresses are routed to the
PLDs as inputs.
Input Macrocells (IMC) are particularly useful with
handshaking communication applications where
two processors pass data back and forth through
a common mailbox. Figure 18., page 42 shows a
typical configuration where the Master MCU writes
to the Port A Data Out Register. This, in turn, can
be read by the Slave MCU via the activation of the
“Slave-Read” output enable product term.
The Slave can also write to the Port A Input Mac-
rocells (IMC) and the Master can then read the In-
put Macrocells (IMC) directly.
Note that the “Slave-Read” and “Slave-Wr” signals
are product terms that are derived from the Slave
MCU inputs Read Strobe (RD, CNTL1), Write
Strobe (WR, CNTL0), and Slave_CS.
41/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
43/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
MCU BUS INTERFACE
The “no-glue logic” MCU Bus Interface block can
be directly connected to most popular MCUs and
their control signals. Key 8-bit MCUs, with their
bus types and control signals, are shown in Table
16. The interface type is specified using the PSD-
soft Express Configuration.
Table 16. MCUs and their Control Signals
Note:1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PC7, PD0, PA3-0) can be configured for other I/O func-
tions. ALE/AS input is optional for MCUs with a non-multiplexed bus
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PSD Interface to a Multiplexed 8-Bit Bus
Figure 19 shows an example of a system using a
MCU with an 8-bit multiplexed bus and a PSD. The
ADIO port on the PSD is connected directly to the
MCU address/data bus. Address Strobe (ALE/AS,
PD0) latches the address signals internally.
Latched addresses can be brought out to Port A or
B. The PSD drives the ADIO data bus only when
one of its internal resources is accessed and Read
Strobe (RD, CNTL1) is active. Should the system
address bus exceed sixteen bits, Ports A, B, C, or
D may be used as additional address inputs.
45/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PSD Interface to a Non-Multiplexed 8-Bit Bus
Figure 20 shows an example of a system using a
MCU with an 8-bit non-multiplexed bus and a
PSD. The address bus is connected to the ADIO
Port, and the data bus is connected to Port A. Port
A is in tri-state mode when the PSD is not access-
ed by the MCU. Should the system address bus
exceed sixteen bits, Ports B, C, or D may be used
for additional address inputs.
Data Byte Enable Reference
MCUs have different data byte orientations. Table
17 shows how the PSD interprets byte/word oper-
ations in different bus WRITE configurations.
Even-byte refers to locations with address A0
equal to '0' and odd byte as locations with A0 equal
to ’1.’
MCU Bus Interface Examples
Figure 21 through 25 show examples of the basic
connections between the PSD and some popular
MCUs. The PSD Control input pins are labeled as
to the MCU function for which they are configured.
The MCU bus interface is specified using the PS-
Dsoft Express Configuration.
Table 17. Eight-Bit Data Bus
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
80C31
Figure 21 shows the bus interface for the 80C31,
which has an 8-bit multiplexed address/data bus.
The lower address byte is multiplexed with the
data bus. The MCU control signals Program Se-
lect Enable (PSEN, CNTL2), Read Strobe (RD,
CNTL1), and Write Strobe (WR, CNTL0) may be
used for accessing the internal memory and I/O
Ports blocks. Address Strobe (ALE/AS, PD0)
latches the address.
47/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
80C251
The Intel 80C251 MCU features a user-config-
urable bus interface with four possible bus config-
urations, as shown in Table 18., page 48.
The first configuration is 80C31-compatible, and
the bus interface to the PSD is identical to that
shown in Figure 21., page 46. The second and
third configurations have the same bus connection
as shown in Figure 22. There is only one Read
Strobe (PSEN) connected to CNTL1 on the PSD.
The A16 connection to PA0 allows for a larger ad-
dress input to the PSD. The fourth configuration is
shown in Figure 23., page 48. Read Strobe (RD) is
connected to CNTL1 and Program Select Enable
(PSEN) is connected to CNTL2.
The 80C251 has two major operating modes:
Page mode and Non-page mode. In Non-page
mode, the data is multiplexed with the lower ad-
dress byte, and Address Strobe (ALE/AS, PD0) is
active in every bus cycle. In Page mode, data (D7-
D0) is multiplexed with address (A15-A8). In a bus
cycle where there is a Page hit, Address Strobe
(ALE/AS, PD0) is not active and only addresses
(A7-A0) are changing. The PSD supports both
modes. In Page Mode, the PSD bus timing is iden-
tical to Non-Page Mode except the address hold
time and setup time with respect to Address
Strobe (ALE/AS, PD0) is not required. The PSD
access time is measured from address (A7-A0)
valid to data in valid.
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
49/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
80C51XA
The Philips 80C51XA MCU family supports an 8-
or 16-bit multiplexed bus that can have burst cy-
cles. Address bits (A3-A0) are not multiplexed,
while (A19-A4) are multiplexed with data bits
(D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4)
are multiplexed with data bits (D7-D0).
The 80C51XA can be configured to operate in
eight-bit data mode (as shown in Figure 24).
The 80C51XA improves bus throughput and per-
formance by executing burst cycles for code fetch-
es. In Burst Mode, address A19-A4 are latched
internally by the PSD, while the 80C51XA changes
the A3-A0 signals to fetch up to 16 bytes of code.
The PSD access time is then measured from ad-
dress A3-A0 valid to data in valid. The PSD bus
timing requirement in Burst Mode is identical to the
normal bus cycle, except the address setup and
hold time with respect to Address Strobe (ALE/AS,
PD0) does not apply.
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
68HC11
Figure 25 shows a bus interface to a 68HC11
where the PSD is configured in 8-bit multiplexed
mode with E and R/W settings. The DPLD can be
used to generate the READ and WR signals for
external devices.
51/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
I/O PORTS
There are four programmable I/O ports: Ports A, B,
C, and D. Each of the ports is eight bits except Port
D, which is 3 bits. Each port pin is individually user
configurable, thus allowing multiple functions per
port. The ports are configured using PSDsoft Ex-
press Configuration or by the MCU writing to on-
chip registers in the CSIOP space.
The topics discussed in this section are: General Port architecture Port operating modes Port Configuration Registers (PCR) Port Data Registers Individual Port functionality.
General Port Architecture
The general architecture of the I/O Port block is
shown in Figure 26., page 52. Individual Port ar-
chitectures are shown in Figure 28., page 58 to
Figure 31., page 61. In general, once the purpose
for a port pin has been defined, that pin is no long-
er available for other purposes. Exceptions are
noted.
As shown in Figure 26., page 52, the ports contain
an output multiplexer whose select signals are
driven by the configuration bits in the Control Reg-
isters (Ports A and B only) and PSDsoft Express
Configuration. Inputs to the multiplexer include the
following: Output data from the Data Out register Latched address outputs CPLD macrocell output External Chip Select (ECS0-ECS2) from the
CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and macrocell outputs, Direc-
tion and Control Registers, and port pin input are
all connected to the Port Data Buffer (PDB).
The Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is not defined as a CPLD output
in the PSDabel file, then the Direction Register has
sole control of the buffer that drives the port pin.
The contents of these registers can be altered by
the MCU. The Port Data Buffer (PDB) feedback
path allows the MCU to check the contents of the
registers.
Ports A, B, and C have embedded Input Macro-
cells (IMC). The Input Macrocells (IMC) can be
configured as latches, registers, or direct inputs to
the PLDs. The latches and registers are clocked
by Address Strobe (ALE/AS, PD0) or a product
term from the PLD AND Array. The outputs from
the Input Macrocells (IMC) drive the PLD input bus
and can be read by the MCU. See the section en-
titled Input Macrocell, page 41.
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDabel,
some by the MCU writing to the Control Registers
in CSIOP space, and some by both. The modes
that can only be defined using PSDsoft Express
must be programmed into the device and cannot
be changed unless the device is reprogrammed.
The modes that can be changed by the MCU can
be done so dynamically at run-time. The PLD I/O,
Data Port, Address Input, and Peripheral I/O
modes are the only modes that must be defined
before programming the device. All other modes
can be changed by the MCU at run-time. See Ap-
plication Note AN1171 for more detail.
Table 19., page 53 summarizes which modes are
available on each port. Table 22., page 56 shows
how and where the different modes are config-
ured. Each of the port operating modes are de-
scribed in the following sections.
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
53/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
MCU I/O Mode
In the MCU I/O mode, the MCU uses the I/O Ports
block to expand its own I/O ports. By setting up the
CSIOP space, the ports on the PSD are mapped
into the MCU address space. The addresses of
the ports are listed in Table 7., page 18.
A port pin can be put into MCU I/O mode by writing
a 0 to the corresponding bit in the Control Regis-
ter. The MCU I/O direction may be changed by
writing to the corresponding bit in the Direction
Register, or by the output enable product term.
See the section entitled Peripheral I/O
Mode, page 55. When the pin is configured as an
output, the content of the Data Out Register drives
the pin. When configured as an input, the MCU
can read the port input through the Data In buffer.
See Figure 26., page 52.
Ports C and D do not have Control Registers, and
are in MCU I/O mode by default. They can be used
for PLD I/O if equations are written for them in PS-
Dabel.
PLD I/O Mode
The PLD I/O Mode uses a port as an input to the
CPLD’s Input Macrocells (IMC), and/or as an out-
put from the CPLD’s Output Macrocells (OMC).
The output can be tri-stated with a control signal.
This output enable control signal can be defined
by a product term from the PLD, or by resetting the
corresponding bit in the Direction Register to ’0.’
The corresponding bit in the Direction Register
must not be set to '1' if the pin is defined for a PLD
input signal in PSDabel. The PLD I/O mode is
specified in PSDabel by declaring the port pins,
and then writing an equation assigning the PLD I/
O to a port.
Address Out Mode
For MCUs with a multiplexed address/data bus,
Address Out Mode can be used to drive latched
addresses on to the port pins. These port pins can,
in turn, drive external devices. Either the output
enable or the corresponding bits of both the Direc-
tion Register and Control Register must be set to
a 1 for pins to use Address Out Mode. This must
be done by the MCU at run-time. See Table 21 for
the address output pin assignments on Ports A
and B for various MCUs.
For non-multiplexed 8-bit bus mode, address sig-
nals (A7-A0) are available to Port B in Address Out
Mode.
Note: Do not drive address signals with Address
Out Mode to an external memory device if it is in-
tended for the MCU to Boot from the external de-
vice. The MCU must first Boot from PSD memory
so the Direction and Control register bits can be
set.
Table 19. Port Operating Modes
Note:1. Can be multiplexed with other I/O functions.
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Table 20. Port Operating Mode Settings
Note:1. N/A = Not Applicable The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array. Any of these three methods enables the JTAG pins on Port C.
Table 21. I/O Port Latched Address Output Assignments
Note:1. N/A = Not Applicable.
55/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Address In Mode
For MCUs that have more than 16 address sig-
nals, the higher addresses can be connected to
Port A, B, C, and D. The address input can be
latched in the Input Macrocell (IMC) by Address
Strobe (ALE/AS, PD0). Any input that is included
in the DPLD equations for the SRAM, or primary or
secondary Flash memory is considered to be an
address input.
Data Port Mode
Port A can be used as a data bus port for a MCU
with a non-multiplexed address/data bus. The
Data Port is connected to the data bus of the MCU.
The general I/O functions are disabled in Port A if
the port is configured as a Data Port.
Peripheral I/O Mode
Peripheral I/O mode can be used to interface with
external peripherals. In this mode, all of Port A
serves as a tri-state, bi-directional data buffer for
the MCU. Peripheral I/O Mode is enabled by set-
ting Bit 7 of the VM Register to a ’1.’ Figure 27
shows how Port A acts as a bi-directional buffer for
the MCU data bus if Peripheral I/O Mode is en-
abled. An equation for PSEL0 and/or PSEL1 must
be written in PSDabel. The buffer is tri-stated
when PSEL0 or PSEL1 is not active.

Partno	Mfg	Dc	Qty	Available	Descript
PSD813F2-A-70J \|PSD813F2A70J	INTERSIL	N/a	13	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD813F2A-70J \|PSD813F2A70J	ST	N/a	22	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD813F2-A-90J \|PSD813F2A90J	ST	N/a	8	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD813F2-A-90J \|PSD813F2A90J	WSI	N/a	15	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD813F2A-90J \|PSD813F2A90J	ST	N/a	1050	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD813F2-A-90JI \|PSD813F2A90JI	WSI	N/a	104	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD813F2A-90JI \|PSD813F2A90JI	ST	N/a	543	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD813F2-A-90M \|PSD813F2A90M	WSI	N/a	3	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD813F2A-90MI \|PSD813F2A90MI	ST	N/a	4982	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD833F2-90M \|PSD833F290M	STM	N/a	368	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD834F2-70J \|PSD834F270J	WSI	N/a	21	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD834F2-70M \|PSD834F270M	ST	N/a	159	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD834F2-90M \|PSD834F290M		N/a	612	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD834F2-90MI \|PSD834F290MI	WSI	N/a	10	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD853F2-90M \|PSD853F290M	ST	N/a	96	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD854F2-70M \|PSD854F270M	WSI	N/a	31	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD854F2-90M \|PSD854F290M	WSI	N/a	234	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V
PSD854F2-90MI \|PSD854F290MI	ST	N/a	127	avai	Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5V