PSD813F1-A-90M ,Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5VFEATURES SUMMARY
PSD813F1-A-90M
Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
1/110August 2004
PSD813F1Flash In-System Programmable (ISP)
Peripherals for 8-bit MCUs, 5V
FEATURES SUMMARY DUAL BANK FLASH MEMORIES 1 Mbit of Primary Flash Memory (8
Uniform Sectors) 256 Kbit Secondary EEPROM (4 Uniform
Sectors) Concurrent operation: read from one
memory while erasing and writing the
other 16 Kbit SRAM (BATTERY-BACKED) PLD WITH MACROCELLS Over 3,000 Gates Of PLD: DPLD and
CPLD DPLD - User-defined Internal chip-select
decoding CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs) 27 RECONFIGURABLE I/Os 27 individually configurable I/O port pins
that can be used for the following
functions:
MCU I/Os;
PLD I/Os;
Latched MCU address output; and
Special function I/Os.
Note: 16 of the I/O ports may be configured as open-drain outputs. ENHANCED JTAG SERIAL PORT Built-in JTAG-compliant serial port allows
full-chip In-System Programmability (ISP) Efficient manufacturing allows for easy
product testing and programming PAGE REGISTER Internal page register that can be used to
expand the microcontroller address space
by a factor of 256. PROGRAMMABLE POWER MANAGEMENT
PSD813F12/110
TABLE OF CONTENTS
Features Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
In-Application Programming (IAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PSDsoft Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Microcontroller Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
PSD Register Description and Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
MEMORY BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Primary Flash Memory and Secondary EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . .18
Memory Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Power-down Instruction and Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Data Polling Flag (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Toggle Flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Error Flag (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Erase Time-out Flag DQ3 (Flash Memory only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Writing to the EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Writing the OTP Row. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3/110
PSD813F1
Flash Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Flash Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
FLASH AND EEPROM MEMORY SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Flash Memory and EEPROM Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
MEMORY SELECT SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Memory Select Configuration for MCUs with Separate Program and Data Spaces . . . . . . . .31
Separate Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Combined Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
PLD’S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
DECODE PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
COMPLEX PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
PSD Interface to a Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
PSD Interface to a Non-Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Data Byte Enable Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
MCU Bus Interface Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
80C51XA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
I/O PORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
General Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Port Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
PSD813F14/110
Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Peripheral I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Drive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Mask Macrocell Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Ports A and B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Port C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Port D – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Power-down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
For Users of the HC11 (or compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
SRAM Standby Mode (Battery Backup). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . .71
Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
JTAG Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Security, Flash memory and EEPROM Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
5/110
PSD813F1
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
APPENDIX A.PQFP52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
APPENDIX B.PLCC52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
APPENDIX C.TQFP64 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
PSD813F16/110
SUMMARY DESCRIPTIONThe PSD family of Programmable Microcontroller
(MCU) Peripherals brings In-System Programma-
bility (ISP) to Flash memory and programmable
logic. The result is a simple and flexible solution for
embedded designs. PSD devices combine many
of the peripheral functions found in MCU based
applications.
PSD devices integrate an optimized “microcontrol-
ler macrocell” logic architecture. The Macrocell
was created to address the unique requirements
of embedded system designs. It allows direct con-
nection between the system address/data bus and
the internal PSD registers to simplify communica-
tion between the MCU and other supporting devic-
es.
The PSD family offers two methods to program
PSD Flash memory while the PSD is soldered to a
circuit board.
In-System Programming (ISP) via JTAGAn IEEE 1149.1 compliant JTAG interface is in-
cluded on the PSD enabling the entire device
(Flash memory, EEPROM, the PLD, and all con-
figuration) to be rapidly programmed while sol-
dered to the circuit board. This requires no MCU
participation, which means the PSD can be pro-
grammed anytime, even while completely blank.
The innovative JTAG interface to Flash memories
is an industry first, solving key problems faced by
designers and manufacturing houses, such as:
First time programming. How do I get firmware
into the Flash the very first time JTAG is the an-
swer, program the PSD while blank with no MCU
involvement.
Inventory build-up of pre-programmed devic-
es. How do I maintain an accurate count of pre-
programmed Flash memory and PLD devices
based on customer demand How many and what
version JTAG is the answer, build your hardware
with blank PSDs soldered directly to the board and
then custom program just before they are shipped
to customer. No more labels on chips and no more
wasted inventory.
Expensive sockets. How do I eliminate the need
for expensive and unreliable sockets JTAG is the
answer. Solder the PSD directly to the circuit
board. Program first time and subsequent times
with JTAG. No need to handle devices and bend
the fragile leads.
In-Application Programming (IAP)Two independent memory arrays (Flash and EE-
PROM) are included so the MCU can execute
code from one memory while erasing and pro-
gramming the other. Robust product firmware up-
dates in the field are possible over any
communication channel (CAN, Ethernet, UART,
J1850, etc.) using this unique architecture. De-
signers are relieved of these problems:
Simultaneous read and write to Flash memo-
ry. How can the MCU program the same memory
from which it is executing code It cannot. The
PSD allows the MCU to operate the two memories
concurrently, reading code from one while erasing
and programming the other during IAP.
Complex memory mapping. I have only a 64K-
byte address space to start with. How can I map
these two memories efficiently A Programmable
Decode PLD is the answer. The concurrent PSD
memories can be mapped anywhere in MCU ad-
dress space, segment by segment with extremely
high address resolution. As an option, the second-
ary Flash memory can be swapped out of the sys-
tem memory map when IAP is complete. A built-in
page register breaks the 64K-byte address limit.
Separate program and data space. How can I
write to Flash or EEPROM memory while it resides
in “program” space during field firmware updates,
my MCU won’t allow it! The Flash PSD provides
means to “reclassify” Flash or EEPROM memory
as “data” space during IAP, then back to “program”
space when complete.
PSDsoft ExpressPSDsoft Express, a software development tool
from ST, guides you through the design process
step-by-step making it possible to complete an
embedded MCU design capable of ISP/IAP in just
hours. Select your MCU and PSDsoft Express
takes you through the remainder of the design with
point and click entry, covering PSD selection, pin
definitions, programmable logic inputs and out-
puts, MCU memory map definition, ANSI-C code
generation for your MCU, and merging your MCU
firmware with the PSD design. When complete,
two different device programmers are supported
directly from PSDsoft Express: FlashLINK (JTAG)
and PSDpro.
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PSD813F1
PSD813F18/110
9/110
PSD813F1
PSD813F110/110
PIN DESCRIPTION
Table 1. Pin Description (for the PLCC52 package)
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PSD813F1
PSD813F112/110
Note:1. The pin numbers in this table are for the PLCC package only. See the Figure 2., page 7, for pin numbers on other package type. These functions can be multiplexed with other functions.
13/110
PSD813F1
PSD813F114/110
PSD ARCHITECTURAL OVERVIEWPSD devices contain several major functional
blocks. Figure 5 shows the architecture of the PSD
device. The functions of each block are described
briefly in the following sections. Many of the blocks
perform multiple functions and are user config-
urable.
MemoryThe PSD contains the following memories: a 1 Mbit Flash memory a secondary 256 Kbit EEPROM memory a 16 Kbit SRAM
Each of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discus-
sion can be found in the section entitled MEMORY
BLOCKS, page 18.
The 1 Mbit Flash memory is the main memory of
the PSD. It is divided into 8 equally-sized sectors
that are individually selectable.
The 256 Kbit EEPROM or Flash memory is divided
into 4 equally-sized sectors. Each sector is individ-
ually selectable.
The 16 Kbit SRAM is intended for use as a
scratchpad memory or as an extension to the mi-
crocontroller SRAM. If an external battery is con-
nected to the PSD’s VSTBY pin, data will be
retained in the event of a power failure.
Each sector of memory can be located in a differ-
ent address space as defined by the user. The ac-
cess times for all memory types includes the
address latching and DPLD decoding time.
PLDsThe device contains two PLD blocks, each opti-
mized for a different function, as shown in Table 2.
The functional partitioning of the PLDs reduces
power consumption, optimizes cost/performance,
and eases design entry.
The Decode PLD (DPLD) is used to decode ad-
dresses and generate chip selects for the PSD in-
ternal memory and registers. The CPLD can
implement user-defined logic functions. The DPLD
has combinatorial outputs. The CPLD has 16 Out-
put macrocells and 3 combinatorial outputs. The
PSD also has 24 Input macrocells that can be con-
figured as inputs to the PLDs. The PLDs receive
their inputs from the PLD Input Bus and are differ-
entiated by their output destinations, number of
Product Terms, and macrocells.
The PLDs consume minimal power by using Zero-
Power design techniques. The speed and power
consumption of the PLD is controlled by the Turbo
Bit (ZPSD only) in the PMMR0 register and other
bits in the PMMR2 registers. These registers are
set by the microcontroller at runtime. There is a
slight penalty to PLD propagation time when in-
voking the ZPSD features.
I/O PortsThe PSD has 27 I/O pins divided among four ports
(Port A, B, C, and D). Each I/O pin can be individ-
ually configured for different functions. Ports A, B,
C and D can be configured as standard MCU I/O
ports, PLD I/O, or latched address outputs for mi-
crocontrollers using multiplexed address/data
busses.
The JTAG pins can be enabled on Port C for In-
System Programming (ISP).
Ports A and B can also be configured as a data
port for a n on-multiplexed bus or multiplexed Ad-
dress/Data buses for certain types of 16-bit micro-
controllers.
Microcontroller Bus InterfaceThe PSD easily interfaces with most 8-bit micro-
controllers that have either multiplexed or non-
multiplexed address/data busses. The device is
configured to respond to the microcontroller’s con-
trol signals, which are also used as inputs to the
PLDs. Where there is a requirement to use a 16-
bit data bus to interface to a 16-bit microcontroller,
two PSDs must be used. For examples, please
see the section entitled MCU Bus Interface
Examples, page 47.
Table 2. PLD I/O
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PSD813F1
JTAG PortIn-System Programming can be performed
through the JTAG pins on Port C. This serial inter-
face allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port C. Table 3 indicates the
JTAG signals pin assignments.
In-System Programming (ISP)Using the JTAG signals on Port C, the entire PSD
device can be programmed or erased without the
use of the microcontroller. The main Flash memo-
ry can also be programmed in-system by the mi-
crocontroller executing the programming
algorithms out of the EEPROM or SRAM. The EE-
PROM can be programmed the same way by exe-
cuting out of the main Flash memory. The PLD
logic or other PSD configuration can be pro-
grammed through the JTAG port or a device pro-
grammer. Table 4 indicates which programming
methods can program different functional blocks
of the PSD.
Page RegisterThe 8-bit Page Register expands the address
range of the microcontroller by up to 256 times.
The paged address can be used as part of the ad-
dress space to access external memory and pe-
ripherals, or internal memory and I/O. The Page
Register can also be used to change the address
mapping of blocks of Flash memory into different
memory spaces for in-circuit programming.
Power Management Unit (PMU)The Power Management Unit (PMU) in the PSD
gives the user control of the power consumption
on selected functional blocks based on system re-
quirements. The PMU includes an Automatic Pow-
er Down unit (APD) that will turn off device
functions due to microcontroller inactivity. The
APD unit has a Power Down Mode that helps re-
duce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The turbo bit in the PMMR0 reg-
ister can be turned off and the CPLD will latch its
outputs and go to sleep until the next transition on
its inputs.
Additionally, bits in the PMMR2 register can be set
by the MCU to block signals from entering the
CPLD to reduce power consumption. Please see
the section entitled POWER
MANAGEMENT, page 64 for more details.
Table 3. JTAG SIgnals on Port C
Table 4. Methods of Programming Different Functional Blocks of the PSD
PSD813F116/110
DEVELOPMENT SYSTEMThe PSD is supported by PSDsoft Express a Win-
dows-based (95, 98, NT) software development
tool. A PSD design is quickly and easily produced
in a point and click environment. The designer
does not need to enter Hardware Definition Lan-
guage (HDL) equations (unless desired) to define
PSD pin functions and memory map information.
The general design flow is shown in Figure 6 be-
low. PSDsoft Express is available from our web
site (/psm) or other distribution chan-
nels.
PSDsoft Express directly supports two low cost
device programmers from ST, PSDpro and
FlashLINK (JTAG). Both of these programmers
may be purchased through your local distributor/
representative, or directly from our web site using
a credit card. The PSD is also supported by third
party device programmers, see web site for cur-
rent list.
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PSD813F1
PSD REGISTER DESCRIPTION AND ADDRESS OFFSETTable 5 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al-
located by the user to the internal PSD registers.
Table 6 provides brief descriptions of the registers
in CSIOP space. The following section gives a
more detailed description.
Table 5. I/O Port Latched Address Output AssignmentsNote:1. See the section entitled I/O PORTS, page 52, on how to enable the Latched Address Output function. N/A = Not Applicable
Table 6. Register Address OffsetNote:1. Other registers that are not part of the I/O ports.
PSD813F118/110
DETAILED OPERATIONAs shown in Figure 5., page 13, the PSD consists
of six major types of functional blocks: Memory Blocks PLD Blocks MCU Bus Interface I/O Ports Power Management Unit (PMU) JTAG Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
MEMORY BLOCKSThe PSD has the following memory blocks (see
Table 7): The Main Flash memory Secondary EEPROM memory SRAM
The Memory Select signals for these blocks origi-
nate from the Decode PLD (DPLD) and are user-
defined in PSDsoft Express.
Primary Flash Memory and Secondary
EEPROM DescriptionThe 1Mb primary Flash memory is divided evenly
into eight 16-KByte sectors. The EEPROM memo-
ry is divided into four sectors of eight KBytes each.
Each sector of either memory can be separately
protected from Program and Erase operations.
Flash memory may be erased on a sector-by-sec-
tor basis and programmed byte-by-byte. Flash
sector erasure may be suspended while data is
read from other sectors of memory and then re-
sumed after reading.
EEPROM may be programmed byte-by-byte or
sector-by-sector, and erasing is automatic and
transparent. The integrity of the data can be se-
cured with the help of Software Data Protection
(SDP). Any write operation to the EEPROM is in-
hibited during the first five milliseconds following
power-up.
During a program or erase of Flash, or during a
write of the EEPROM, the status can be output on
the Ready/Busy (PC3) pin of Port C3. This pin is
set up using PSDsoft Express Configuration.
Memory Block Select Signals. The decode
PLD in the PSD generates the chip selects for all
the internal memory blocks (refer to the section
entitled PLD’S, page 34). Each of the eight Flash
memory sectors have a Flash Select signal (FS0-
FS7) which can contain up to three product terms.
Each of the four EEPROM memory sectors have a
Select signal (EES0-3 or CSBOOT0-3) which can
contain up to three product terms. Having three
product terms for each sector select signal allows
a given sector to be mapped in different areas of
system memory. When using a microcontroller
with separate Program and Data space, these
flexible select signals allow dynamic re-mapping of
sectors from one space to the other.
Ready/Busy Pin (PC3). Pin PC3 can be used to
output the Ready/Busy status of the PSD. The out-
put on the pin will be a ‘0’ (Busy) when Flash or
EEPROM memory blocks are being written to, or
when the Flash memory block is being erased.
The output will be a ‘1’ (Ready) when no write or
erase operation is in progress.
Table 7. Memory Blocks
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PSD813F1
Memory OperationThe main Flash and EEPROM memory are ad-
dressed through the microcontroller interface on
the PSD device. The microcontroller can access
these memories in one of two ways: The microcontroller can execute a typical bus
WRITE or READ operation just as it would if
accessing a RAM or ROM device using
standard bus cycles. The microcontroller can execute a specific
instruction that consists of several WRITE and
READ operations. This involves writing
specific data patterns to special addresses
within the Flash or EEPROM to invoke an
embedded algorithm. These instructions are
summarized in Table 8., page 20.
Typically, Flash memory can be read by the micro-
controller using READ operations, just as it would
read a ROM device. However, Flash memory can
only be erased and programmed with specific in-
structions. For example, the microcontroller can-
not write a single byte directly to Flash memory as
one would write a byte to RAM. To program a byte
into Flash memory, the microcontroller must exe-
cute a program instruction sequence, then test the
status of the programming event. This status test
is achieved by a READ operation or polling the
Ready/Busy pin (PC3).
The Flash memory can also be read by using spe-
cial instructions to retrieve particular Flash device
information (sector protect status and ID).
The EEPROM is a bit different. Data can be written
to EEPROM memory using write operations, like
writing to a RAM device, but the status of each
WRITE event must be checked by the microcon-
troller. A WRITE event can be one to 64 contigu-
ous bytes. The status test is very similar to that
used for Flash memory (READ operation or
Ready/Busy). Optionally, the EEPROM memory
may be put into a Software Data Protect (SDP)
mode where it requires instructions, rather than
operations, to alter its contents. SDP mode makes
writing to EEPROM much like writing to Flash
memory.
PSD813F120/110
Table 8. InstructionsNote:1. Additional sectors to be erased must be entered within 80 µs. A Sector Address is any address within the Sector. Flash and EEPROM Sector Selects are active high. Addresses A15-A12 are don’t cares in Instruction Bus Cycles. The Reset instruction is required to return to the normal READ mode if DQ5 goes high or after reading the Flash Identifier or Pro-
tection status. The MCU cannot invoke these instructions while executing code from EEPROM. The MCU must be operating from some other
memory when these instructions are performed. The MCU cannot invoke these instructions while executing code from the same Flash memory for which the instruction is intended.
The MCU must operate from some other memory when these instructions are executed. Writing to OTP Row is allowed only when SDP mode is disabled.
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PSD813F1
INSTRUCTIONSAn instruction is defined as a sequence of specific
operations. Each received byte is sequentially de-
coded by the PSD and not executed as a standard
write operation. The instruction is executed when
the correct number of bytes are properly received
and the time between two consecutive bytes is
shorter than the time-out value. Some instructions
are structured to include READ operations after
the initial WRITE operations.
The sequencing of any instruction must be fol-
lowed exactly. Any invalid combination of instruc-
tion bytes or time-out between two consecutive
bytes while addressing Flash memory will reset
the device logic into READ mode (Flash memory
reads like a ROM device). An invalid combination
or time-out while addressing the EEPROM block
will cause the offending byte to be interpreted as a
single operation.
The PSD supports these instructions (see Table
8., page 20):
Flash memory: Erase memory by chip or sector Suspend or resume sector erase Program a Byte Reset to READ mode Read Flash Identifier value Read Sector Protection Status
EEPROM: Write data to OTP Row Read data from OTP Row Power down memory Enable Software Data Protect (SDP) Disable SDP Return from read OTP Row read mode or
power down mode.
These instructions are detailed in Table
8., page 20. For efficient decoding of the instruc-
tions, the first two bytes of an instruction are the
coded cycles and are followed by a command byte
or confirmation byte. The coded cycles consist of
writing the data AAh to address X555h during the
first cycle and data 55h to address XAAAh during
the second cycle. Address lines A15-A12 are don’t
cares during the instruction WRITE cycles. How-
ever, the appropriate sector select signal (FSi or
EESi) must be selected.
Power-down Instruction and Power-up Mode
EEPROM Power Down Instruction. The EE-
PROM can enter power down mode with the help
of the EEPROM power down instruction (see Ta-
ble 8., page 20). Once the EEPROM power down
instruction is decoded, the EEPROM memory can-
not be accessed unless a Return instruction (also
in Table 8., page 20) is decoded. Alternately, this
power down mode will automatically occur when
the APD circuit is triggered (see section entitled
Automatic Power-down (APD) Unit and Power-
down Mode, page 65). Therefore, this instruction
is not required if the APD circuit is used.
Power-up Mode. The PSD internal logic is reset
upon power-up to the READ mode. Any write op-
eration to the EEPROM is inhibited during the first
5ms following power-up. The FSi and EESi select
signals, along with the write strobe signal, must be
in the false state during power-up for maximum se-
curity of the data contents and to remove the pos-
sibility of a byte being written on the first edge of a
write strobe signal. Any write cycle initiation is
locked when VCC is below VLKO.
PSD813F122/110
READUnder typical conditions, the microcontroller may
read the Flash or EEPROM memory using READ
operations just as it would a ROM or RAM device.
Alternately, the microcontroller may use READ op-
erations to obtain status information about a Pro-
gram or Erase operation in progress. Lastly, the
microcontroller may use instructions to read spe-
cial data from these memories. The following sec-
tions describe these READ functions.
Read Memory Contents. Main Flash is placed in
the READ mode after power-up, chip reset, or a
Reset Flash instruction (see Table 8., page 20).
The microcontroller can read the memory contents
of main Flash or EEPROM by using READ opera-
tions any time the READ operation is not part of an
instruction sequence.
Read Main Flash Memory Identifier. The main
Flash memory identifier is read with an instruction
composed of 4 operations:
3 specific write operations and a READ operation
(see Table 8). During the READ operation, ad-
dress bits A6, A1, and A0 must be 0,0,1, respec-
tively, and the appropriate sector select signal
(FSi) must be active. The Flash ID is E3h for the
PSD. The MCU can read the ID only when it is ex-
ecuting from the EEPROM.
Read Main Flash Memory Sector Protection
Status. The main Flash memory sector protection
status is read with an instruction composed of 4
operations: 3 specific WRITE operations and a
READ operation (see Table 8., page 20). During
the READ operation, address bits A6, A1, and A0
must be 0,1,0, respectively, while the chip select
FSi designates the Flash sector whose protection
has to be verified. The READ operation will pro-
duce 01h if the Flash sector is protected, or 00h if
the sector is not protected.
The sector protection status for all NVM blocks
(main Flash or EEPROM) can be read by the mi-
crocontroller accessing the Flash Protection and
PSD/EE Protection registers in PSD I/O space.
See Flash Memory and EEPROM Sector
Protect, page 30 for register definitions.
Reading the OTP Row. There are 64 bytes of
One-Time-Programmable (OTP) memory that re-
side in EEPROM. These 64 bytes are in addition
to the 32 Kbytes of EEPROM memory. A READ of
the OTP row is done with an instruction composed
of at least 4 operations: 3 specific WRITE opera-
tions and one to 64 READ operations (see Table
8., page 20). During the READ operation(s), ad-
dress bit A6 must be zero, while address bits A5-
A0 define the OTP Row byte to be read while any
EEPROM sector select signal (EESi) is active. Af-
ter reading the last byte, an EEPROM Return in-
struction must be executed (see Table
8., page 20).
Reading the Erase/Program Status Bits. The
PSD provides several status bits to be used by the
microcontroller to confirm the completion of an
erase or programming instruction of Flash memo-
ry. Bits are also available to show the status of
WRITES to EEPROM. These status bits minimize
the time that the microcontroller spends perform-
ing these tasks and are defined in Table 9. The
status bits can be read as many times as needed.
For Flash memory, the microcontroller can per-
form a READ operation to obtain these status bits
while an Erase or Program instruction is being ex-
ecuted by the embedded algorithm. See the sec-
tion entitled PROGRAMMING FLASH
MEMORY, page 27 for details.
For EEPROM not in SDP mode, the microcontrol-
ler can perform a READ operation to obtain these
status bits just after a data WRITE operation. The
microcontroller may write one to 64 bytes before
reading the status bits. See the section entitled
Writing to the EEPROM, page 24 for details.
For EEPROM in SDP mode, the microcontroller
will perform a READ operation to obtain these sta-
tus bits while an SDP write instruction is being ex-
ecuted by the embedded algorithm. See section
entitled EEPROM Software Data Protect
(SDP), page 24 for details.
Table 9. Status BitNote:1. X = not guaranteed value, can be read either 1 or 0. DQ7-DQ0 represent the Data Bus Bits, D7-D0. FSi and EESi are active High.
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PSD813F1
Data Polling Flag (DQ7)When Erasing or Programming the Flash memory
(or when Writing into the EEPROM memory), bit
DQ7 outputs the complement of the bit being en-
tered for Programming/Writing on DQ7. Once the
Program instruction or the WRITE operation is
completed, the true logic value is read on DQ7 (in
a Read operation). Flash memory specific fea-
tures: Data Polling is effective after the fourth WRITE
pulse (for programming) or after the sixth
WRITE pulse (for Erase). It must be performed
at the address being programmed or at an
address within the Flash sector being erased. During an Erase instruction, DQ7 outputs a ‘0.’
After completion of the instruction, DQ7 will
output the last bit programmed (it is a ‘1’ after
erasing). If the byte to be programmed is in a protected
Flash sector, the instruction is ignored. If all the Flash sectors to be erased are
protected, DQ7 will be set to ‘0’ for about
100µs, and then return to the previous
addressed byte. No erasure will be performed.
Toggle Flag (DQ6)The PSD offers another way for determining when
the EEPROM write or the Flash memory Program
instruction is completed. During the internal
WRITE operation and when either the FSi or EESi
is true, the DQ6 will toggle from ‘0’ to ‘1’ and ‘1’ to
‘0’ on subsequent attempts to read any byte of the
memory.
When the internal cycle is complete, the toggling
will stop and the data read on the Data Bus D0-7
is the addressed memory byte. The device is now
accessible for a new READ or WRITE operation.
The operation is finished when two successive
reads yield the same output data. Flash memory
specific features: The Toggle bit is effective after the fourth
WRITE pulse (for programming) or after the
sixth WRITE pulse (for Erase). If the byte to be programmed belongs to a
protected Flash sector, the instruction is
ignored. If all the Flash sectors selected for erasure are
protected, DQ6 will toggle to ‘0’ for about 100
µs and then return to the previous addressed
byte.
Error Flag (DQ5)During a correct Program or Erase, the Error bit
will set to ‘0.’ This bit is set to ‘1’ when there is a
failure during Flash byte programming, Sector
erase, or Bulk Erase.
In the case of Flash programming, the Error Bit in-
dicates the attempt to program a Flash bit(s) from
the programmed state ('0') to the erased state ('1'),
which is not a valid operation. The Error bit may
also indicate a timeout condition while attempting
to program a byte.
In case of an error in Flash sector erase or byte
program, the Flash sector in which the error oc-
curred or to which the programmed byte belongs
must no longer be used. Other Flash sectors may
still be used. The Error bit resets after the Reset in-
struction.
Erase Time-out Flag DQ3 (Flash Memory only)The Erase Timer bit reflects the time-out period al-
lowed between two consecutive Sector Erase in-
structions. The Erase timer bit is set to ‘0’ after a
Sector Erase instruction for a time period of 100µs
+ 20% unless an additional Sector Erase instruc-
tion is decoded. After this time period or when the
additional Sector Erase instruction is decoded,
DQ3 is set to ‘1.’
PSD813F124/110
Writing to the EEPROMData may be written a byte at a time to the EE-
PROM using simple write operations, much like
writing to an SRAM. Unlike SRAM though, the
completion of each byte write must be checked be-
fore the next byte is written. To speed up this pro-
cess, the PSD offers a Page write feature to allow
writing of several bytes before checking status.
To prevent inadvertent writes to EEPROM, the
PSD offers a Software Data Protect (SDP) mode.
Once enabled, SDP forces the MCU to “unlock”
the EEPROM before altering its contents, much
like Flash memory programming.
Writing a Byte to EEPROM. A write operation is
initiated when an EEPROM select signal (EESi) is
true and the write strobe signal (WR) into the PSD
is true. If the PSD detects no additional writes with-
in 120µsec, an internal storage operation is initiat-
ed. Internal storage to EEPROM memory
technology typically takes a few milliseconds to
complete.
The status of the write operation is obtained by the
MCU reading the Data Polling or Toggle bits (as
detailed in section entitled READ, page 22), or the
Ready/Busy output pin (section Ready/Busy Pin
(PC3), page 18).
Keep in mind that the MCU does not need to erase
a location in EEPROM before writing it. Erasure is
performed automatically as an internal process.
Writing a Page to EEPROM. Writing data to EE-
PROM using page mode is more efficient than
writing one byte at a time. The PSD EEPROM has
a 64 byte volatile buffer that the MCU may fill be-
fore an internal EEPROM storage operation is ini-
tiated. Page mode timing approaches a 64:1
advantage over the time it takes to write individual
bytes.
To invoke page mode, the MCU must write to EE-
PROM locations within a single page, with no
more than 120µs between individual byte writes. A
single page means that address lines A14 to A6
must remain constant. The MCU may write to the
64 locations on a page in any order, which is de-
termined by address lines A5 to A0. As soon as
120µs have expired after the last page write, the
internal EEPROM storage process begins and the
MCU checks programming status. Status is
checked the same way it is for byte writes, de-
scribed above.
Note: Be aware that if the upper address bits (A14to A6) change during page write operations, loss
of data may occur. Ensure that all bytes for a given
page have been successfully stored in the EE-
PROM before proceeding to the next page. Cor-
rect management of MCU interrupts during
EEPROM page write operations is essential.
EEPROM Software Data Protect (SDP). The
SDP feature is useful for protecting the contents of
EEPROM from inadvertent write cycles that may
occur during uncontrolled MCU bus conditions.
These may happen if the application software gets
lost or when VCC is not within normal operating
range.
Instructions from the MCU are used to enable and
disable SDP mode (see Table 8., page 20). Once
enabled, the MCU must write an instruction se-
quence to EEPROM before writing data (much like
writing to Flash memory). SDP mode can be used
for both byte and page writes to EEPROM. The
device will remain in SDP mode until the MCU is-
sues a valid SDP disable instruction.
PSD devices are shipped with SDP mode dis-
abled. However, within PSDsoft Express, SDP
mode may be enabled as part of programming the
device with a device programmer (PSDpro).
To enable SDP mode at run time, the MCU must
write three specific data bytes at three specific
memory locations, as shown in Figure 7., page 25.
Any further writes to EEPROM when SDP is set
will require this same sequence, followed by the
byte(s) to write. The first SDP enable sequence
can be followed directly by the byte(s) to be writ-
ten.
To disable SDP mode, the MCU must write specif-
ic bytes to six specific locations, as shown in Fig-
ure 8., page 26.
The MCU must not be executing code from EE-
PROM when these instructions are invoked. The
MCU must be operating from some other memory
when enabling or disabling SDP mode.
The state of SDP mode is not changed by power
on/off sequences (nonvolatile). When either the
SDP enable or SDP disable instructions are is-
sued from the MCU, the MCU must use the Toggle
bit (status bit DQ6) or the Ready/Busy output pin
to check programming status. The Ready/Busy
output is driven low from the first write of AAh @
555h until the completion of the internal storage
sequence. Data Polling (status bit DQ7) is not sup-
ported when issuing the SDP enable or SDP dis-
able commands.
Note: Using the SDP sequence (enabling, dis-
abling, or writing data) is initiated when specific
bytes are written to addresses on specific “pages”
of EEPROM memory, with no more than 120µs
between WRITES. The addresses 555h and
AAAh are located on different pages of EEPROM.
This is how the PSD distinguishes these instruc-
tion sequences from ordinary writes to EEPROM,
which are expected to be within a single EEPROM
page.
25/110
PSD813F1
Writing the OTP RowWriting to the OTP row (64 bytes) can only be
done once per byte, and is enabled by an instruc-
tion. This instruction is composed of three specific
WRITE operations of data bytes at three specific
memory locations followed by the data to be
stored in the OTP row (refer to Table 8., page 20).
During the WRITE operations, address bit A6 must
be zero, while address bits A5-A0 define the OTP
Row byte to be written while any EEPROM Sector
Select signal (EESi) is active. Writing the OTP
Row is allowed only when SDP mode is not en-
abled.
PSD813F126/110
27/110
PSD813F1
PROGRAMMING FLASH MEMORYFlash memory must be erased prior to being pro-
grammed. The MCU may erase Flash memory all
at once or by-sector, but not byte-by-byte. A byte
of Flash memory erases to all logic ones (FF hex),
and its bits are programmed to logic zeros. Al-
though erasing Flash memory occurs on a sector
basis, programming Flash memory occurs on a
byte basis.
The PSD main Flash and optional boot Flash re-
quire the MCU to send an instruction to program a
byte or perform an erase function (see Table
8., page 20). This differs from EEPROM, which
can be programmed with simple MCU bus write
operations (unless EEPROM SDP mode is en-
abled).
Once the MCU issues a Flash memory program or
erase instruction, it must check for the status of
completion. The embedded algorithms that are in-
voked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or the Ready/Busy output pin.
Data PollingPolling on DQ7 is a method of checking whether a
Program or Erase instruction is in progress or has
completed. Figure 9 shows the Data Polling algo-
rithm.
When the MCU issues a programming instruction,
the embedded algorithm within the PSD begins.
The MCU then reads the location of the byte to be
programmed in Flash to check status. Data bit
DQ7 of this location becomes the compliment of
data bit 7of the original data byte to be pro-
grammed. The MCU continues to poll this location,
comparing DQ7 and monitoring the Error bit on
DQ5. When the DQ7 matches data bit 7 of the
original data, and the Error bit at DQ5 remains ‘0’,
then the embedded algorithm is complete. If the
Error bit at DQ5 is ‘1’, the MCU should test DQ7
again since DQ7 may have changed simulta-
neously with DQ5 (see Figure 9).
The Error bit at DQ5 will be set if either an internal
timeout occurred while the embedded algorithm
attempted to program the byte or if the MCU at-
tempted to program a ‘1’ to a bit that was not
erased (not erased is logic ‘0’).
PSD813F128/110
Data ToggleChecking the Data Toggle bit on DQ6 is a method
of determining whether a Program or Erase in-
struction is in progress or has completed. Figure
10 shows the Data Toggle algorithm.
When the MCU issues a programming instruction,
the embedded algorithm within the PSD begins.
The MCU then reads the location of the byte to be
programmed in Flash to check status. Data bit
DQ6 of this location will toggle each time the MCU
reads this location until the embedded algorithm is
complete. The MCU continues to read this loca-
tion, checking DQ6 and monitoring the Error bit on
DQ5. When DQ6 stops toggling (two consecutive
reads yield the same value), and the Error bit on
DQ5 remains ‘0’, then the embedded algorithm is
complete. If the Error bit on DQ5 is ‘1’, the MCU
should test DQ6 again, since DQ6 may have
changed simultaneously with DQ5 (see Figure
10).
The Error bit at DQ5 will be set if either an internal
timeout occurred while the embedded algorithm
attempted to program the byte, or if the MCU at-
tempted to program a ‘1’ to a bit that was not
erased (not erased is logic ‘0’).
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed to compare the byte
that was written to Flash with the byte that was in-
tended to be written.
When using the Data Toggle method after an
erase instruction, Figure 10 still applies. DQ6 will
toggle until the erase operation is complete. A ‘1’
on DQ5 will indicate a timeout failure of the erase
operation, a ‘0’ indicates no error. The MCU can
read any location within the sector being erased to
get DQ6 and DQ5.
29/110
PSD813F1
ERASING FLASH MEMORY
Flash Bulk EraseThe Flash Bulk Erase instruction uses six write op-
erations followed by a Read operation of the status
register, as described in Table 8., page 20. If any
byte of the Bulk Erase instruction is wrong, the
Bulk Erase instruction aborts and the device is re-
set to the Read Flash memory status.
During a Bulk Erase, the memory status may be
checked by reading status bits DQ5, DQ6, and
DQ7, as detailed in section entitled PROGRAM-
MING FLASH MEMORY, page 27. The Error bit
(DQ5) returns a ‘1’ if there has been an Erase Fail-
ure (maximum number of erase cycles have been
executed).
It is not necessary to program the array with 00h
because the PSD will automatically do this before
erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory will not accept any instructions.
Flash Sector Erase. The Sector Erase instruc-
tion uses six write operations, as described in Ta-
ble 8., page 20. Additional Flash Sector Erase
confirm commands and Flash sector addresses
can be written subsequently to erase other Flash
sectors in parallel, without further coded cycles, if
the additional instruction is transmitted in a shorter
time than the timeout period of about 100 µs. The
input of a new Sector Erase instruction will restart
the time-out period.
The status of the internal timer can be monitored
through the level of DQ3 (Erase time-out bit). If
DQ3 is ‘0’, the Sector Erase instruction has been
received and the timeout is counting. If DQ3 is ‘1’,
the timeout has expired and the PSD is busy eras-
ing the Flash sector(s). Before and during Erase
timeout, any instruction other than Erase suspend
and Erase Resume will abort the instruction and
reset the device to READ mode. It is not neces-
sary to program the Flash sector with 00h as the
PSD will do this automatically before erasing
(byte=FFh).
During a Sector Erase, the memory status may be
checked by reading status bits DQ5, DQ6, and
DQ7, as detailed in section entitled PROGRAM-
MING FLASH MEMORY, page 27.
During execution of the erase instruction, the
Flash block logic accepts only Reset and Erase
Suspend instructions. Erasure of one Flash sector
may be suspended, in order to read data from an-
other Flash sector, and then resumed.
Flash Erase SuspendWhen a Flash Sector Erase operation is in
progress, the Erase Suspend instruction will sus-
pend the operation by writing 0B0h to any address
when an appropriate Chip Select (FSi) is true.
(See Table 8., page 20). This allows reading of
data from another Flash sector after the Erase op-
eration has been suspended. Erase suspend is
accepted only during the Flash Sector Erase in-
struction execution and defaults to READ mode.
An Erase Suspend instruction executed during an
Erase timeout will, in addition to suspending the
erase, terminate the time out.
The Toggle Bit DQ6 stops toggling when the PSD
internal logic is suspended. The toggle Bit status
must be monitored at an address within the Flash
sector being erased. The Toggle Bit will stop tog-
gling between 0.1 µs and 15 µs after the Erase
Suspend instruction has been executed. The PSD
will then automatically be set to Read Flash Block
Memory Array mode.
If an Erase Suspend instruction was executed, the
following rules apply: Attempting to read from a Flash sector that
was being erased will output invalid data. Reading from a Flash sector that was not
being erased is valid. The Flash memory cannot be programmed,
and will only respond to Erase Resume and
Reset instructions (READ is an operation and
is OK). If a Reset instruction is received, data in the
Flash sector that was being erased will be
invalid.
Flash Erase ResumeIf an Erase Suspend instruction was previously ex-
ecuted, the erase operation may be resumed by
this instruction. The Erase Resume instruction
consists of writing 030h to any address while an
appropriate Chip Select (FSi) is true. (See Table
8., page 20.)
PSD813F130/110
FLASH AND EEPROM MEMORY SPECIFIC FEATURES
Flash Memory and EEPROM Sector ProtectEach Flash and EEPROM sector can be separate-
ly protected against Program and Erase functions.
Sector Protection provides additional data security
because it disables all program or erase opera-
tions. This mode can be activated through the
JTAG Port or a Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft Configuration program. This will
automatically protect selected sectors when the
device is programmed through the JTAG Port or a
Device Programmer. Flash and EEPROM sectors
can be unprotected to allow updating of their con-
tents using the JTAG Port or a Device Program-
mer. The microcontroller can read (but cannot
change) the sector protection bits.
Any attempt to program or erase a protected Flash
or EEPROM sector will be ignored by the device.
The Verify operation will result in a READ of the
protected data. This allows a guarantee of the re-
tention of the Protection status.
The sector protection status can be read by the
MCU through the Flash protection and PSD/EE
protection registers (CSIOP). See Table 10.
ResetThe Reset instruction resets the internal memory
logic state machine in a few milliseconds. Reset is
an instruction of either one write operation or three
write operations (refer to Table 8., page 20).
Table 10. Sector Protection/Security Bit Definition – Flash Protection RegisterNote:1. Bit Definitions:
Sec_Prot 1 = Flash is write protected.
Sec_Prot 0 = Flash is not write protected.
Table 11. Sector Protection/Security Bit Definition – PSD/EE Protection RegisterNote:1. Bit Definitions:
Sec_Prot 1 = EEPROM Boot Sector is write protected.
Sec_Prot 0 = EEPROM Boot Sector is not write protected.
Security_Bit 0 = Security Bit in device has not been set.1 = Security Bit in device has been set.
SRAMThe SRAM is a 16 Kbit (2K x 8) memory. The
SRAM is enabled when RS0—the SRAM chip se-
lect output from the DPLD—is high. RS0 can con-
tain up to two product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to the VSTBY pin (PC2). If you have an external
battery connected to the PSD, the contents of the
SRAM will be retained in the event of a power loss.
The contents of the SRAM will be retained so long
as the battery voltage remains at 2V or greater.
If the supply voltage falls below the battery volt-
age, an internal power switchover to the battery
occurs.
Pin PC4 can be configured as an output that indi-
cates when power is being drawn from the exter-
nal battery. This VBATON signal will be high with
the supply voltage falls below the battery voltage
and the battery on PC2 is supplying power to the
internal SRAM.
The chip select signal (RS0) for the SRAM, VSTBY,
and VBATON are all configured using PSDsoft Ex-
press Configuration.
31/110
PSD813F1
MEMORY SELECT SIGNALSThe main Flash (FSi), EEPROM (EESi), and
SRAM (RS0) memory select signals are all out-
puts of the DPLD. They are setup by entering
equations for them in PSDsoft Express. The fol-
lowing rules apply to the equations for the internal
chip select signals: Flash memory and EEPROM sector select
signals must not be larger than the physical
sector size. Any main Flash memory sector must not be
mapped in the same memory space as
another Flash sector. An EEPROM sector must not be mapped in
the same memory space as another EEPROM
sector. SRAM, I/O, and Peripheral I/O spaces must
not overlap. An EEPROM sector may overlap a main Flash
memory sector. In case of overlap, priority will
be given to the EEPROM. SRAM, I/O, and Peripheral I/O spaces may
overlap any other memory sector. Priority will
be given to the SRAM, I/O, or Peripheral I/O.
ExampleFS0 is valid when the address is in the range of
8000h to BFFFh, EES0 is valid from 8000h to
9FFFh, and RS0 is valid from 8000h to 87FFh.
Any address in the range of RS0 will always ac-
cess the SRAM. Any address in the range of EES0
greater than 87FFh (and less than 9FFFh) will au-
tomatically address EEPROM segment 0. Any ad-
dress greater than 9FFFh will access the Flash
memory segment 0. You can see that half of the
Flash memory segment 0 and one-fourth of EE-
PROM segment 0 can not be accessed in this ex-
ample. Also note that an equation that defined FS1
to anywhere in the range of 8000h to BFFFh would
not be valid.
Figure 11 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level.
Table 12. VM Register
PSD813F132/110
Separate Space ModesCode memory space is separated from data mem-
ory space. For example, the PSEN signal is used
to access the program code from the Flash Mem-
ory, while the RD signal is used to access data
from the EEPROM, SRAM and I/O Ports. This
configuration requires the VM register to be set to
0Ch. See Figure 12.
Combined Space ModesThe program and data memory spaces are com-
bined into one space that allows the main Flash
Memory, EEPROM, and SRAM to be accessed by
either PSEN or RD. For example, to configure the
main Flash memory in combined space mode, bits
2 and 4 of the VM register are set to “1” (see Figure
13).
33/110
PSD813F1
PAGE REGISTERThe 8-bit Page Register increases the addressing
capability of the microcontroller by a factor of up to
256. The contents of the register can also be read
by the microcontroller. The outputs of the Page
Register (PGR0-PGR7) are inputs to the DPLD
decoder and can be included in the Flash Memory,
EEPROM, and SRAM chip select equations.
If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic.
Figure 14 shows the Page Register. The eight flip
flops in the register are connected to the internal
data bus D0-D7. The microcontroller can write to
or read from the Page Register. The Page Regis-
ter can be accessed at address location CSIOP +
E0h.
PSD813F134/110
PLD’SThe PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
using the PSDabel tool in PSDsoft Express, the
logic is programmed into the device and available
upon power-up.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in the sections entitled DE-
CODE PLD (DPLD) and COMPLEX PLD (CPLD).
Figure 15., page 35 shows the configuration of the
PLDs.
The DPLD performs address decoding for internal
and external components, such as memory, regis-
ters, and I/O port selects.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output macrocells (OMCs), 24 Input macrocells
(IMCs), and the AND array. The CPLD can also be
used to generate external chip selects.
The AND array is used to form product terms.
These product terms are specified using PSDabel.
An Input Bus consisting of 73 signals is connected
to the PLDs. The signals are shown in Table 13.
The Turbo Bit in PSDThe PLDs in the PSD can minimize power con-
sumption by switching off when inputs remain un-
changed for an extended time of about 70ns.
Setting the Turbo mode bit to off (Bit 3 of the
PMMR0 register) automatically places the PLDs
into standby if no inputs are changing. Turbo-off
mode increases propagation delays while reduc-
ing power consumption. See the section entitled
POWER MANAGEMENT, page 64, on how to set
the Turbo Bit.
Additionally, five bits are available in the PMMR2
register to block MCU control signals from entering
the PLDs. This reduces power consumption and
can be used only when these MCU control signals
are not used in PLD logic equations.
The PLDs in the PSD can minimize power con-
sumption by switching off when inputs remain un-
changed for an extended time of about 70ns. Each
of the two PLDs has unique characteristics suited
for its applications. They are described in the fol-
lowing sections.
Table 13. DPLD and CPLD InputsNote:1. The address inputs are A19-A4 in 80C51XA mode.
35/110
PSD813F1
PSD813F136/110
DECODE PLD (DPLD)The DPLD, shown in Figure 16, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals: 8 sector selects for the main Flash memory
(three product terms each) 4 sector selects for the EEPROM (three
product terms each) 1 internal SRAM select signal (two product
terms) 1 internal CSIOP (PSD configuration register)
select signal 1 JTAG select signal (enables JTAG on Port 2 internal peripheral select signals (peripheral
I/O mode).
37/110
PSD813F1
COMPLEX PLD (CPLD)The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate 3 external chip selects,
routed to Port D.
Although external chip selects can be produced by
any Output Macrocell, these three external chip
selects on Port D do not consume any Output
macrocells.
As shown in Figure 15., page 35, the CPLD has
the following blocks: 24 Input macrocells (IMCs) 16 Output macrocells (OMCs) Macrocell Allocator Product Term Allocator AND array capable of generating up to 137
product terms Four I/O ports.
Each of the blocks are described in the subsec-
tions that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the microcontrol-
ler. This enables the MCU software to load data
into the Output Macrocells (OMC) or read data
from both the Input and Output Macrocells (IMC
and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND logic array as required in
most standard PLD macrocell architectures.
PSD813F138/110
Output Macrocell (OMC)Eight of the Output Macrocells (OMC) are con-
nected to Ports A and B pins and are named as
McellAB0-McellAB7. The other eight macrocells
are connected to Ports B and C pins and are
named as McellBC0-McellBC7. If an McellAB out-
put is not assigned to a specific pin in PSDabel,
the Macrocell Allocator will assign it to either Port
A or B. The same is true for a McellBC output on
Port B or C. Table 14 shows the macrocells and
Port assignment.
The Output Macrocell (OMC) architecture is
shown in Figure 18., page 40. As shown in the fig-
ure, there are native product terms available from
the AND array, and borrowed product terms avail-
able (if unused) from other OMCs. The polarity of
the product term is controlled by the XOR gate.
The OMC can implement either sequential logic,
using the flip-flop element, or combinatorial logic.
The multiplexer selects between the sequential or
combinatorial logic outputs. The multiplexer output
can drive a Port pin and has a feedback path to the
AND array inputs.
The flip-flop in the OMC can be configured as a D,
T, JK, or SR type in the PSDabel program. The
flip-flop’s clock, preset, and clear inputs may be
driven from a product term of the AND array. Alter-
natively, the external CLKIN signal can be used for
the clock input to the flip-flop. The flip-flop is
clocked on the rising edge of the clock input. The
preset and clear are active-high inputs. Each clear
input can use up to two product terms.
Table 14. Output Macrocell Port and Data Bit Assignments
39/110
PSD813F1
Product Term AllocatorThe CPLD has a Product Term Allocator. The PS-
Dabel compiler uses the Product Term Allocator to
borrow and place product terms from one macro-
cell to another. The following list summarizes how
product terms are allocated: McellAB0-McellAB7 all have three native
product terms and may borrow up to six more McellBC0-McellBC3 all have four native
product terms and may borrow up to five more McellBC4-McellBC7 all have four native
product terms and may borrow up to six more.
Each macrocell may only borrow product terms
from certain other macrocells. Product terms al-
ready in use by one macrocell are not available for
another macrocell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required, which will consume other Output
Macrocells (OMC). If external product terms are
used, extra delay will be added for the equation
that required the extra product terms.
This is called product term expansion. PSDsoft
Express will perform this expansion as needed.
Loading and Reading the Output Macrocells
(OMC). The OMCs occupy a memory location in
the MCU address space, as defined by the CSIOP
(refer to the I/O section). The flip-flops in each of
the 16 OMCs can be loaded from the data bus by
a microcontroller. Loading the OMCs with data
from the MCU takes priority over internal func-
tions. As such, the preset, clear, and clock inputs
to the flip-flop can be overridden by the MCU. The
ability to load the flip-flops and read them back is
useful in such applications as loadable counters
and shift registers, mailboxes, and handshaking
protocols.
Data can be loaded to the OMCs on the trailing
edge of the WR signal (edge loading) or during the
time that the WR signal is active (level loading).
The method of loading is specified in PSDsoft Ex-
press Configuration.
The OMC Mask RegisterThere is one Mask Register for each of the two
groups of eight OMCs. The Mask Registers can be
used to block the loading of data to individual
OMCs. The default value for the Mask Registers is
00h, which allows loading of the OMCs. When a
given bit in a Mask Register is set to a ‘1’, the MCU
will be blocked from writing to the associated
OMC. For example, suppose McellAB0-3 are be-
ing used for a state machine. You would not want
a MCU write to McellAB to overwrite the state ma-
chine registers. Therefore, you would want to load
the Mask Register for McellAB (Mask Macrocell
AB) with the value 0Fh.
The Output Enable of the OMCThe OMC can be connected to an I/O port pin as
a PLD output. The output enable of each Port pin
driver is controlled by a single product term from
the AND array, ORed with the Direction Register
output. The pin is enabled upon power up if no out-
put enable equation is defined and if the pin is de-
clared as a PLD output in PSDsoft Express.
If the OMC output is declared as an internal node
and not as a Port pin output in the PSDabel file,
then the Port pin can be used for other I/O func-
tions. The internal node feedback can be routed as
an input to the AND array.
PSD813F140/110
41/110
PSD813F1
Input Macrocells (IMC)The CPLD has 24 IMCs, one for each pin on Ports
A, B, and C. The architecture of the IMC is shown
in Figure 19., page 42. The IMCs are individually
configurable, and can be used as a latch, register,
or to pass incoming Port signals prior to driving
them onto the PLD input bus. The outputs of the
IMCs can be read by the microcontroller through
the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND array or the
MCU address strobe (ALE/AS). Each product term
output is used to latch or clock four IMCs. Port in-
puts 3-0 can be controlled by one product term
and 7-4 by another.
Configurations for the IMCs are specified by equa-
tions written in PSDabel (see Application Note 55).
Outputs of the IMCs can be read by the MCU via
the IMC buffer. See the I/O Port section on how to
read the IMCs.
IMCs can use the address strobe to latch address
bits higher than A15. Any latched addresses are
routed to the PLDs as inputs.
IMCs are particularly useful with handshaking
communication applications where two proces-
sors pass data back and forth through a common
mailbox. Figure 20., page 43 shows a typical con-
figuration where the Master MCU writes to the Port
A Data Out Register. This, in turn, can be read by
the Slave MCU via the activation of the “Slave-
Read” output enable product term.
The Slave can also write to the Port A IMCs and
the Master can then read the IMCs directly.
Note that the “Slave-Read” and “Slave-wr” signals
are product terms that are derived from the Slave
MCU inputs RD, WR, and Slave_CS.
PSD813F142/110
43/110
PSD813F1
PSD813F144/110
MCU BUS INTERFACEThe “no-glue logic” PSD MCU Bus Interface block
can be directly connected to most popular MCUs
and their control signals.
Key 8-bit MCUs, with their bus types and control
signals, are shown in Table 15. The interface type
is specified using the PSDsoft Express Configura-
tion.
Table 15. MCUs and their Control SignalsNote:1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PC7, PD0, PA3-0) can be configured for other I/O func-
tions. ALE/AS input is optional for MCUs with a non-multiplexed bus
45/110
PSD813F1
PSD Interface to a Multiplexed 8-Bit BusFigure 21 shows an example of a system using a
MCU with an 8-bit multiplexed bus and a PSD. The
ADIO port on the PSD is connected directly to the
MCU address/data bus. Address Strobe (ALE/AS,
PD0) latches the address signals internally.
Latched addresses can be brought out to Port A or
B. The PSD drives the ADIO data bus only when
one of its internal resources is accessed and Read
Strobe (RD, CNTL1) is active. Should the system
address bus exceed sixteen bits, Ports A, B, C, or
D may be used as additional address inputs.
PSD813F146/110
PSD Interface to a Non-Multiplexed 8-Bit BusFigure 22 shows an example of a system using a
microcontroller with an 8-bit non-multiplexed bus
and a PSD. The address bus is connected to the
ADIO Port, and the data bus is connected to Port
A. Port A is in tri-state mode when the PSD is not
accessed by the microcontroller. Should the sys-
tem address bus exceed sixteen bits, Ports B, C,
or D may be used for additional address inputs.
47/110
PSD813F1
Data Byte Enable ReferenceMicrocontrollers have different data byte orienta-
tions. The following table shows how the PSD in-
terprets byte/word operations in different bus
WRITE configurations. Even-byte refers to loca-
tions with address A0 equal to zero and odd byte
as locations with A0 equal to one.
Table 16. Eight-Bit Data Bus
MCU Bus Interface ExamplesFigure 23 to 26 show examples of the basic con-
nections between the PSD and some popular
MCUs. The PSD Control input pins are labeled as
to the MCU function for which they are configured.
The MCU bus interface is specified using the PS-
Dsoft Express Configuration.
The first configuration is 80C31-compatible, and
the bus interface to the PSD is identical to that
shown in Figure 23. The second and third configu-
rations have the same bus connection as shown in
Table 17., page 48. There is only one READ input
(PSEN) connected to the CNTL1 pin on the PSD.
The A16 connection to the PA0 pin allows for a
larger address input to the PSD. Configuration 4 is
shown in Figure 24., page 49. The RD signal is
connected to Cntl1 and the PSEN signal is con-
nected to the CNTL2.
80C31Figure 23 shows the bus interface for the 80C31,
which has an 8-bit multiplexed address/data bus.
The lower address byte is multiplexed with the
data bus. The MCU control signals Program Se-
lect Enable (PSEN, CNTL2), Read Strobe (RD,
CNTL1), and Write Strobe (WR, CNTL0) may be
used for accessing the internal memory and I/O
Ports. The ALE input (pin PD0) latches the ad-
dress.
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80C251The Intel 80C251 MCU features a user-config-
urable bus interface with four possible bus config-
urations, as shown in Table 18., page 49.
The 80C251 has two major operating modes:
Page Mode and Non-Page Mode. In Non-Page
Mode, the data is multiplexed with the lower ad-
dress byte, and ALE is active in every bus cycle.
In Page Mode, data D[7:0] is multiplexed with ad-
dress A[15:8]. In a bus cycle where there is a Page
hit, the ALE signal is not active and only addresses
A[7:0] are changing. The PSD supports both
modes. In Page Mode, the PSD bus timing is iden-
tical to Non-Page Mode except the address hold
time and setup time with respect to ALE is not re-
quired. The PSD access time is measured from
address A[7:0] valid to data in valid.
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PSD813F150/110
80C51XAThe Philips 80C51XA microcontroller family sup-
ports an 8- or 16-bit multiplexed bus that can have
burst cycles. Address bits (A3-A0) are not multi-
plexed, while (A19-A4) are multiplexed with data
bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-
A4) are multiplexed with data bits (D7-D0).
The 80C51XA can be configured to operate in
eight-bit data mode. (shown in Figure 25).
The 80C51XA improves bus throughput and per-
formance by executing Burst cycles for code fetch-
es. In Burst Mode, address A19-A4 are latched
internally by the PSD, while the 80C51XA changes
the A3-A0 lines to fetch up to 16 bytes of code. The
PSD access time is then measured from address
A3-A0 valid to data in valid. The PSD bus timing
requirement in Burst Mode is identical to the nor-
mal bus cycle, except the address setup and hold
time with respect to ALE does not apply.
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68HC11Figure 26 shows an interface to a 68HC11 where
the PSD is configured in 8-bit multiplexed mode
with E and R/W settings. The DPLD can generate
the READ and WR signals for external devices.
PSD813F152/110
I/O PORTSThere are four programmable I/O ports: Ports A, B,
C, and D. Each of the ports is eight bits except Port
D, which is 3 bits. Each port pin is individually user
configurable, thus allowing multiple functions per
port. The ports are configured using PSDsoft Ex-
press Configuration or by the MCU writing to on-
chip registers in the CSIOP address space.
The topics discussed in this section are: General Port architecture Port Operating Modes Port Configuration Registers (PCR) Port Data Registers Individual Port Functionality.
General Port ArchitectureThe general architecture of the I/O Port is shown
in Figure 27., page 53. Individual Port architec-
tures are shown in Figure 29., page 60 to Figure
32., page 63. In general, once the purpose for a
port pin has been defined, that pin will no longer be
available for other purposes. Exceptions will be
noted.
As shown in Figure 27., page 53, the ports contain
an output multiplexer whose selects are driven by
the configuration bits in the Control Registers
(Ports A and B only) and PSDsoft Express Config-
uration. Inputs to the multiplexer include the fol-
lowing: Output data from the Data Out Register Latched address outputs CPLD Macrocell output External Chip Select from CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
PDB is connected to the Internal Data Bus for
feedback and can be read by the microcontroller.
The Data Out and Macrocell outputs, Direction
and Control Registers, and port pin input are all
connected to the PDB.
The Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND array enable product term
and the Direction Register. If the enable product
term of any of the array outputs are not defined
and that port pin is not defined as a CPLD output
in the PSDabel file, then the Direction Register has
sole control of the buffer that drives the port pin.
The contents of these registers can be altered by
the microcontroller. The PDB feedback path al-
lows the microcontroller to check the contents of
the registers.
Ports A, B, and C have embedded Input Macro-
cells (IMCs). The IMCs can be configured as latch-
es, registers, or direct inputs to the PLDs. The
latches and registers are clocked by the address
strobe (AS/ALE) or a product term from the PLD
AND array. The outputs from the IMCs drive the
PLD input bus and can be read by the microcon-
troller. See the section entitled Input
Macrocell, page 42.
Port Operating ModesThe I/O Ports have several modes of operation.
Some modes can be defined using PSDabel,
some by the microcontroller writing to the Control
Registers in CSIOP space, and some by both. The
modes that can only be defined using PSDsoft Ex-
press must be programmed into the device and
cannot be changed unless the device is repro-
grammed. The modes that can be changed by the
microcontroller can be done so dynamically at run-
time. The PLD I/O, Data Port, Address Input, and
Peripheral I/O modes are the only modes that
must be defined before programming the device.
All other modes can be changed by the microcon-
troller at run-time.
Table 19., page 54 summarizes which modes are
available on each port. Table 22., page 57 shows
how and where the different modes are config-
ured. Each of the port operating modes are de-
scribed in the following subsections.
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MCU I/O ModeIn the MCU I/O Mode, the microcontroller uses the
PSD ports to expand its own I/O ports. By setting
up the CSIOP space, the ports on the PSD are
mapped into the microcontroller address space.
The addresses of the ports are listed in Table
6., page 17.
A port pin can be put into MCU I/O mode by writing
a ‘0’ to the corresponding bit in the Control Regis-
ter. The MCU I/O direction may be changed by
writing to the corresponding bit in the Direction
Register, or by the output enable product term.
See the section entitled Peripheral I/O
Mode, page 56. When the pin is configured as an
output, the content of the Data Out Register drives
the pin. When configured as an input, the micro-
controller can read the port input through the Data
In buffer. See Figure 27., page 53.
Ports C and D do not have Control Registers, and
are in MCU I/O mode by default. They can be used
for PLD I/O if equation are written for them in PS-
Dabel.
PLD I/O ModeThe PLD I/O Mode uses a port as an input to the
CPLD’s Input Macrocells, and/or as an output from
the CPLD’s Output Macrocells. The output can be
tri-stated with a control signal. This output enable
control signal can be defined by a product term
from the PLD, or by setting the corresponding bit
in the Direction Register to ‘0.’ The corresponding
bit in the Direction Register must not be set to ‘1’ if
the pin is defined as a PLD input pin in PSDabel.
The PLD I/O Mode is specified in PSDabel by de-
claring the port pins, and then writing an equation
assigning the PLD I/O to a port.
Address Out ModeFor microcontrollers with a multiplexed address/
data bus, Address Out Mode can be used to drive
latched addresses onto the port pins. These port
pins can, in turn, drive external devices. Either the
output enable or the corresponding bits of both the
Direction Register and Control Register must be
set to a ‘1’ for pins to use Address Out Mode. This
must be done by the MCU at run-time. See Table
21., page 55 for the address output pin assign-
ments on Ports A and B for various MCUs.
For non-multiplexed 8-bit bus mode, address lines
A7-A0 are available to Port B in Address Out
Mode.
Note: do not drive address lines with Address OutMode to an external memory device if it is intended
for the MCU to boot from the external device. The
MCU must first boot from PSD memory so the Di-
rection and Control register bits can be set.
Table 19. Port Operating ModesNote:1. Can be multiplexed with other I/O functions.
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PSD813F1
Table 20. Port Operating Mode SettingsNote:1. N/A = Not Applicable The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array. Any of these three methods enables the JTAG pins on Port C.
Table 21. I/O Port Latched Address Output AssignmentsNote:1. N/A = Not Applicable.
