PSD501B1-C-70J ,Low Cost Field Programmable Microcontroller PeripheralsFEATURES SUMMARY
PSD501B1-C-70J-PSD511B1-C-15L-PSD511B1-C-70J-PSD512B1-C-15J-ZPSD511B1-C-15J-ZPSD512B1-C-15J-ZPSD512B1-C-90JI-ZPSD512B1-C-90UI
Low Cost Field Programmable Microcontroller Peripherals
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NOT FOR NEW DESIGNJanuary 2002
PSD5XX
ZPSD5XXLow Cost Field Programmable Microcontroller Peripherals
FEATURES SUMMARY Single Supply Voltage:5 V±10% for PSD5XX 2.7 to 5.5 V for PSD5XX-V Up to 1 Mbit of UV EPROM Up to 16 Kbit SRAM Input Latches Programmable I/O ports Page Logic Programmable Security
Figure 1. Packages
PSD5XX Family
PSD5XX/ZPSD5XX
Field-Programmable Microcontroller Peripherals
Table of Contents Introduction...........................................................................................................................................................1 Key Features ........................................................................................................................................................3 Notation ................................................................................................................................................................4 ZPSD Background ................................................................................................................................................4 Integrated Power ManagementTM Operation........................................................................................................6 Design Flow..........................................................................................................................................................7 PSD5XX Family ....................................................................................................................................................8 Table 2. PSD5XX Pin Descriptions......................................................................................................................9 The PSD5XX Architecture ..................................................................................................................................11
9.1 The ZPLD Block..........................................................................................................................................11
9.1.1 The DPLD.........................................................................................................................................14
9.1.2 The GPLD.........................................................................................................................................14
9.1.2.1 Por A Macrocell Structure ..................................................................................................16
9.1.2.2 Port B Macrocell Structure .................................................................................................20
9.1.2.3 Port E Macrocell Structure .................................................................................................23
9.1.3 The PPLD.........................................................................................................................................26
9.1.4 The ZPLD Power Management........................................................................................................26
9.2 Bus Interface...............................................................................................................................................29
9.2.1 Bus Interface Configuration..............................................................................................................29
9.2.2 PSD5XX Interface to a Multiplexed Bus ...........................................................................................29
9.2.3 PSD5XX Interface to Non-Multiplexed Bus......................................................................................30
9.2.4 Data Byte Enable..............................................................................................................................30
9.2.5 Optional Features.............................................................................................................................34
9.2.6 Bus Interface Examples....................................................................................................................34
9.3 I/O Ports......................................................................................................................................................39
9.3.1 Standard MCU I/O............................................................................................................................39
9.3.2 PLD I/O ...........................................................................................................................................39
9.3.3 Address Out......................................................................................................................................40
9.3.4 Address In ........................................................................................................................................40
9.3.5 Data Port ..........................................................................................................................................40
9.3.6 Special Function Out ........................................................................................................................40
9.3.7 Alternate Function In ........................................................................................................................41
9.3.8 Peripheral I/O ...................................................................................................................................41
9.3.9 Open Drain Outputs..........................................................................................................................41
9.3.10 Port Registers...................................................................................................................................42
9.3.11 Port A – Functionality and Structure.................................................................................................45
9.3.12 Port B – Functionality and Structure.................................................................................................45
9.3.13 Port C and Port D – Functionality and Structure ..............................................................................48
9.3.14 Port E – Functionality and Structure.................................................................................................48
9.4 Memory Block .............................................................................................................................................52
9.4.1 EPROM ............................................................................................................................................52
9.4.2 SRAM ...............................................................................................................................................52
9.4.3 Memory Select Map..........................................................................................................................52
9.4.4 Memory Select Map for 8031 Application.........................................................................................54
9.4.5 Peripheral I/O ...................................................................................................................................56
PSD5XX Family
PSD5XX/ZPSD5XX
Field-Programmable Microcontroller Peripherals
Table of Contents (cont.)9.5 Power Management Unit ............................................................................................................................58
9.5.1 Standby Mode ..................................................................................................................................58
9.5.2 Power Down .....................................................................................................................................58
9.5.3 Sleep Mode ......................................................................................................................................58
9.5.4 Other Power Saving Options ............................................................................................................61
9.6 PSD5XX Counter/Timer ..............................................................................................................................63
9.6.1 Counter/Timer Operation..................................................................................................................66
9.6.2 Counter/Timer Registers ..................................................................................................................81
9.7 Interrupt Controller ......................................................................................................................................95
9.7.1 Interrupt Operation ...........................................................................................................................95
9.7.2 Input/Output....................................................................................................................................100
9.7.3 PPLD Macrocell..............................................................................................................................100
9.7.4 Interrupt Flowchart..........................................................................................................................100
10.0 Page Register ...................................................................................................................................................103
11.0 Security Protection............................................................................................................................................103
12.0 System Configuration .......................................................................................................................................104
12.1 Reset Input ............................................................................................................................................108
12.2 ZPLD and Memory During Reset...........................................................................................................108
12.3 Register Values During and After Reset................................................................................................108
12.4 ZPLD Macrocell Initialization .................................................................................................................108
13.0 Specifications....................................................................................................................................................109
13.1 Absolute Maximum Ratings ...................................................................................................................109
13.2 Operating Range ...................................................................................................................................109
13.3 Recommended Operating Conditions....................................................................................................109
13.4 AC/DC Parameters................................................................................................................................110
13.5 Example of PSD5XX Typical Power Calculation at VCC = 5.0 V...........................................................111
13.6 DC Characteristics (5 V ± 10% versions) ..............................................................................................112
13.7 AC/DC Parameters – ZPLD Timing Parameters ...................................................................................113
13.8 Microcontroller Interface – AC/DC Parameters .....................................................................................115
13.9 DC Characteristics (ZPSD5XXV Versions) (3.0 V ± 10% versions)......................................................120
13.10 AC/DC Parameters – ZPLD Timing Parameters (3.0 V ± 10% versions)..............................................121
13.11 Microcontroller Interface – AC/DC Parameters (3.0 V± 10% versions).................................................121
14.0 Timing Diagrams...............................................................................................................................................128
15.0 Pin Capacitance................................................................................................................................................134
16.0 AC Testing ........................................................................................................................................................134
17.0 Erasure and Programming................................................................................................................................134
18.0 PSD5XX Pin Assignments................................................................................................................................135
19.0 Package Information.........................................................................................................................................137
20.0 PSD5XX Product Ordering Information ............................................................................................................142
20.1 PSD5XX Family – Selector Guide.........................................................................................................142
20.2 Part Number Construction .....................................................................................................................143
20.3 Ordering Information..............................................................................................................................143
21.0 Process Change Notice, October 1, 1998 ........................................................................................................148
Introduction
Programmable Peripheral
PSD5XX Family
Field-Programmable Microcontroller Peripherals The PSD5XX family is a microcontroller peripheral that integrates high-performance and
user-configurable blocks of EPROM, programmable logic, and SRAM into one part. The
PSD5XX is also loaded with a variety of features, such as Counter/Timers, Interrupt
controller, power management, and page logic. The PSD5XX products also provide a
powerful microcontroller interface that eliminates the need for external “glue logic”. The no
“glue logic” concept provides a user-programmable interface to a variety of 8- and 16-bit
(multiplexed or non-multiplexed) microcontrollers that is easy to use. The part’s integration,
small form factor, low power consumption, and ease of use make it the ideal part for
interfacing to virtually any microcontroller.
The PSD5XX provides three Zero-power PLDs (ZPLDs): a Decode PLD (DPLD), a
General-purpose PLD (PLD), and a Peripheral PLD (PPLD). The ZPLDs have a total of 61
inputs, 140 product terms, 30 macrocells, and 24 I/O connections. A configuration bit
(Turbo) can be set by the MCU, and will automatically place the ZPLDs into standby if
no inputs are changing. The ZPLDs are designed to consume minimum power using Zero
Power CMOS technology that uses low standby current. Unused product terms are
automatically disabled, also reducing power, regardless of the Turbo bit setting.
The main function of the DPLD is to perform address decoding for the internal I/O ports,
EPROM, and SRAM. The address decoding can be based on up to 24 bits of address
inputs, control signals (RD, WR, PSEN, etc.), and internal page logic. The DPLD supports
separate program and data spaces (for 8031 compatible MCUs).
The General-purpose PLD (GPLD) can be used to implement various logic defined by the
user, such as: State machines Loadable counters and shift registers Inter-processor mailbox External control logic (chip selects, output enables, etc.).
The GPLD has access to up to 61 inputs, 118 product terms, 24 macrocells, and 24 I/O
PSD5XX FamilyThe Peripheral PLD (PPLD) generates outputs to the Counter/Timer unit and the Interrupt
Controller. The PPLD outputs to the Counter/Timer enable, disable, or trigger counting or
time capture. The PPLD outputs to the Interrupt Controller enables the user to define
conditions for interrupt generation.
The Counter/Timer unit provides four 16-bit highly flexible Counter/Timers. Each has five
modes of operation: pulse, waveform, event counting, time capture, and watchdog
(real-time clock). Each Counter/Timer can be programmed to count up or down. The inputs
to the Counter/Timer, which enable/disable counting or trigger an operation, can originate
from the PPLD directly or directly from the pins. The maximum operating frequency of each
counter is 7.5 MHz. The input clock can be divided (by up to 280) before driving the
Counter/Timer unit using the 4 to 280 prescaler.
The Interrupt Controller has eight levels of priority encoding. It accepts four user-defined
interrupts and four terminal counts from the Counter/Timer. Each interrupt can be
individually masked and configured to be level or edge sensitive. A 3-bit interrupt vector is
generated that can be read by the microcontroller. The serviced interrupt will be cleared
automatically after the microcontroller has read the interrupt vector.
The PSD5XX has 40 I/O pins that are divided among 5 ports. Each I/O pin can be
individually configured to provide many functions, including the following: MCU I/O ZPLD I/O Latched address output (for MCUs with multiplexed data bus) Special function I/O (Counter/Timer and Interrupts) Data bus (for MCUs with non-multiplexed data bus).
The PSD5XX can easily interface with virtually any 8- or 16-bit microcontroller with a
multiplexed or non-multiplexed bus. All of the MCU control signals are connected to the
ZPLDs, enabling the user to generate signals for external devices. The PSD5XX can
generate a reset output based on the RESET input (includes hysteresis).
The PSD5XX provides between 256 Kbits and 1 Mbit of EPROM that is divided in to four
equal-sized blocks. Each block can occupy a different address location, allowing for
versatile address mapping. The access time of the EPROM includes the address latching
and DPLD decoding.
The PSD5XX has an optional 16 Kbit SRAM that can be battery-backed by connecting a
battery to the Vstby pin. The battery will protect the contents of the SRAM in the event of a
power failure. Therefore, you can place data in the optional SRAM that you want to keep
after the power is switched off. Power switch-over to the battery automatically occurs when
Vcc drops below Vstby.
A four-bit Page Register enables easy access to the I/O section, EPROM, and SRAM for
microcontrollers with limited address space. The Page Register outputs are connected to
the ZPLDs and thus can also be used for external paging schemes.
Introduction
(cont.)
