PSD4256G6V ,FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUSBlock Diagram (Figure 4.) . . . . 15PSD ARCHITECTURAL OVERVIEW . . 16Memory . . ..
PSD501B1-C-70J ,Low Cost Field Programmable Microcontroller PeripheralsFEATURES SUMMARY
PSD4256G6V
FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS
1/100
PRELIMINARY DATADecember 2002
PSD4256G6VFlash In-System Programmable (ISP)
Peripherals for 16-bit MCUs
FEATURES SUMMARYPSD provides an integrated solution to 16-bit
MCU-based applications that includes config-
urable memories, PLD logic, and I/O: Dual bank Flash memories 8Mbits of Primary Flash Memory (16 uniform
sectors, 64Kbyte) 512Kbits of Secondary Flash Memory with 4
sectors Concurrent operation: READ from one mem-
ory while erasing and writing the other 256Kbits of SRAM (battery-backed) PLD with Macrocells Over 3000 Gates of PLD: CPLD and DPLD CPLD with 16 Output Macrocells (OMCs) and
24 Input Macrocells (IMCs) DPLD - user defined internal chip select de-
coding Seven l/O Ports with 52 I/O pins:
52 individually configurable I/O port pins that
can be used for the following functions: MCU I/Os
–PLD I/Os Latched MCU address output Special function I/Os l/O ports may be configured as open-drain
outputs In-System Programming (ISP) with JTAG Built-in JTAG compliant serial port allows full-
chip In-System Programmability Efficient manufacturing allow easy product
testing and programming Use low cost FlashLINK cable with PC Page Register Internal page register that can be used to ex-
pand the microcontroller address space by a
factor of 256 Programmable power management High Endurance: 100,000 Erase/WRITE Cycles of Flash Mem-
ory 1,000 Erase/WRITE Cycles of PLD 15 Year Data Retention Single Supply Voltage 3V (+20%/–10%) Memory Speed 100ns Flash memory and SRAM access time
for VCC = 3V (+20%/–10%) 90ns Flash memory and SRAM access time
for VCC = 3.3V (+/–10%)
Figure 1. 80-lead, Thin, Quad, Flat Package
PSD4256G6V
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9In-System Programming (ISP) via JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
PSDsoft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Logic Diagram (Figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Pin Names (Table 1.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
TQFP80 Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
TQFP80 Pin Description (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
PSD Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
MCU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
ISP via JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
PLD I/O (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
JTAG Signals on Port E (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
In-System Programming (ISP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
In-Application Programming (IAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Methods of Programming Different Functional Blocks of the PSD (Table 5.) . . . . . . . . . . . . . . . . .17
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18PSDsoft Development Tool (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PSD REGISTER DESCRIPTION AND ADDRESS OFFSETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Register Address Offset (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
REGISTER BIT DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Data-In Registers - Ports A, B, C, D, E, F, and G (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Data-Out Registers - Ports A, B, C, D, E, F, and G (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Direction Registers - Ports A, B, C, D, E, F, and G (Table 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Control Registers - Ports E, F, and G (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Drive Registers - Ports A, B, D, E, and G (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Enable-Out Registers - Ports A, B, C, and F (Table 12.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Input Macrocells - Ports A, B, and C (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Output Macrocells A Register (Table 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Out Macrocells B Register (Table 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Mask Macrocells A Register (Table 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Mask Macrocells B Register (Table 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3/100
PSD4256G6VFlash Memory Protection Register 1 (Table 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Flash Memory Protections Register 2 (Table 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Flash Boot Protection Register (Table 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
JTAG Enable Register (Table 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Page Register (Table 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
PMMR0 Register (Table 23.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PMMR2 Register (Table 24.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
VM Register (Table 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Memory_ID0 Register (Table 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Memory_ID1 Register (Table 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Memory Block Size and Organization (Table 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Primary Flash Memory and Secondary Flash memory Description. . . . . . . . . . . . . . . . . . . . . . . . .26
Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Memory Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
16-bit Instructions (Table 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Power-up Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
READ Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
READ Primary Flash Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
READ Memory Sector Protection Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Reading the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Status Bits (Table 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Status Bits for Motorola 16-bit MCU (Table 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Data Polling (DQ7) - DQ15 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Toggle Flag (DQ6) – DQ14 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Error Flag (DQ5) – DQ13 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Erase Time-out Flag (DQ3) – DQ11 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Data Polling Flowchart (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Data Toggle Flowchart (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
PSD4256G6V
ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Suspend Sector Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Reset (RESET) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MEMORY SELECT SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Priority Level of Memory and I/O Components (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Configuration Modes for MCUs with Separate Program and Data Spaces. . . . . . . . . . . . . . . . . . .36
Combined Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
80C31 Memory Map Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
8031 Memory Modules – Separate Space (Figure 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
8031 Memory Modules – Combined Space (Figure 10.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37Page Register (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
MEMORY ID REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
DPLD and CPLD Inputs (Table 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
PLD Diagram (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
DECODE PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40DPLD Logic Array (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
COMPLEX PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Macrocell and I/O Port (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Output Macrocell Port and Data Bit Assignments (Table 33.). . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5/100
PSD4256G6VLoading and Reading the Output Macrocells (OMC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
The Output Enable of the OMC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
CPLD Output Macrocell (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Input Macrocell (Figure 16.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
External Chip Select Signal (Figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Handshaking Communication Using Input Macrocells (Figure 18.). . . . . . . . . . . . . . . . . . . . . . . . .46
MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4716-bit MCUs and Their Control Signals (Table 34.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
PSD Interface to a Multiplexed Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
An Example of a Typical Multiplexed Bus Interface (Figure 19.). . . . . . . . . . . . . . . . . . . . . . . . . . .48
PSD Interface to a Non-Multiplexed, 16-bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
An Example of a Typical Non-Multiplexed Bus Interface (Figure 20.) . . . . . . . . . . . . . . . . . . . . . . .49
Data Byte Enable Reference for a 16-bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
16-Bit Data Bus with BHE (Table 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
16-bit MCU Bus Interface Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
16-Bit Data Bus with WRH and WRL (Table 36.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
16-Bit Data Bus with SIZ0, A0 (Motorola MCU) (Table 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
16-Bit Data Bus with LDS, UDS (Motorola MCU) (Table 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
80C196 and 80C186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Interfacing the PSD with an 80C196 (Figure 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
MC683xx and MC68HC16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Interfacing the PSD with an MC68331 (Figure 22.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Interfacing the PSD with an 80C51XA-G3 (Figure 23.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
H8/300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Interfacing the PSD with an H83/2350 (Figure 24.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
MMC2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
C16x Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Interfacing the PSD with an MMC2001 (Figure 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Interfacing the PSD with a C167CR (Figure 26.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
I/O PORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
General I/O Port Architecture (Figure 27.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
MCU I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Port Operating Modes (Table 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Port Operating Mode Settings (Table 40.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
I/O Port Latched Address Output Assignments (Table 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
PSD4256G6VData Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Peripheral I/O Mode (Figure 28.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
MCU RESET Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Port Configuration Registers (PCR) (Table 42.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Drive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Port Pin Direction Control, Output Enable P.T. Not Defined (Table 43.) . . . . . . . . . . . . . . . . . . . . .64
Port Pin Direction Control, Output Enable P.T. Defined (Table 44.) . . . . . . . . . . . . . . . . . . . . . . . .64
Port Direction Assignment Example (Table 45.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Drive Register Pin Assignment (Table 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Mask Macrocell Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Port Data Registers (Table 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Enable Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Ports A, B and C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Port A, B, and C Structure (Figure 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Port D – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Port D Structure (Figure 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Port E – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Port F – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Port G – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Port E, F, and G Structure (Figure 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
7/100
PSD4256G6V
POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Power-down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Effect of Power-down Mode on Ports (Table 48.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
APD Unit (Figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
PSD Timing and Standby Current During Power-down Mode (Table 49.) . . . . . . . . . . . . . . . . . . .71
Other Power Saving Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
PLD Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SRAM Standby Mode (Battery Backup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Enable Power-down Flow Chart (Figure 33.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
ADP Counter Operation (Table 50.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74Power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
I/O Pin, Register and PLD Status at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
RESET of Flash Memory Erase and Program Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Status During Power-on RESET, Warm RESET, and Power-down Mode (Table 51.) . . . . . . . . . .74
Reset (RESET) Timing (Figure 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . .75Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
JTAG Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Security and Flash memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
JTAG Port Signals (Table 52.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77PLD ICC / Frequency Consumption (Figure 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Example of PSD Typical Power Calculation at VCC = 3.0V (with Turbo Mode On) (Table 53.) . . .78
Example of PSD Typical Power Calculation at VCC = 3.0V (with Turbo Mode Off) (Table 54.) . . .79
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80Absolute Maximum Ratings (Table 55.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
PSD4256G6V
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81Operating Conditions (Table 56.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
AC Symbols for PLD Timing (Table 57.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
AC Measurement Conditions (Table 58.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Capacitance (Table 59.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
AC Measurement I/O Waveform (Figure 36.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
AC Measurement Load Circuit (Figure 37.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Switching Waveforms - Key (Figure 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
DC Characteristics (Table 60.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Input to Output Disable / Enable (Figure 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
CPLD Combinatorial Timing (Table 61.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
CPLD Macrocell Synchronous Clock Mode Timing (Table 62.) . . . . . . . . . . . . . . . . . . . . . . . . . . .84
CPLD Macrocell Asynchronous Clock Mode Timing (Table 63.). . . . . . . . . . . . . . . . . . . . . . . . . . .85
Synchronous Clock Mode Timing – PLD (Figure 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Asynchronous RESET / Preset (Figure 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Asynchronous Clock Mode Timing (product term clock) (Figure 42.) . . . . . . . . . . . . . . . . . . . . . . .86
Input Macrocell Timing (Product Term Clock) (Figure 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Input Macrocell Timing (Table 64.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Program, WRITE and Erase Times (Table 65.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Peripheral I/O WRITE Timing Diagram (Figure 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
READ Timing Diagram (Figure 45.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
READ Timing (Table 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
WRITE Timing Diagram (Figure 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
WRITE Timing (Table 67.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Peripheral I/O READ Timing Diagram (Figure 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Port F Peripheral Data Mode READ Timing (Table 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Port F Peripheral Data Mode WRITE Timing (Table 69.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Power-down Timing (Table 70.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Reset (RESET) Timing (Table 71.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Reset (RESET) Timing Diagram (Figure 48.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
VSTBYON Timing (Table 72.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
ISC Timing Diagram (Figure 49.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
ISC Timing (Table 73.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96Pin Assignments - PSD4256G6V TQFP80 (Table 76.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
9/100
PSD4256G6V
SUMMARY DESCRIPTIONThe PSD family of memory systems for microcon-
trollers (MCUs) brings In-System-Programmability
(ISP) to Flash memory and programmable logic.
The result is a simple and flexible solution for em-
bedded designs. PSD devices combine many of
the peripheral functions found in MCU based ap-
plications.
PSD devices integrate an optimized Macrocell log-
ic architecture. The Macrocell was created to ad-
dress the unique requirements of embedded
system designs. It allows direct connection be-
tween the system address/data bus, and the inter-
nal PSD registers, to simplify communication
between the MCU and other supporting devices.
The PSD family offers two methods to program the
PSD Flash memory while the PSD is soldered to
the circuit board: In-System Programming (ISP)
via JTAG, and In-Application Programming (IAP).
In-System Programming (ISP) via JTAGAn IEEE 1149.1 compliant JTAG In-System Pro-
gramming (ISP) interface is included on the PSD
enabling the entire device (Flash memories, PLD,
configuration) to be rapidly programmed while sol-
dered to the circuit board. This requires no MCU
participation, which means the PSD can be pro-
grammed anytime, even when completely blank.
The innovative JTAG interface to Flash memories
is an industry first, solving key problems faced by
designers and manufacturing houses, such as:
First time programming. How do I get firmware
into the Flash memory the very first time JTAG is
the answer. Program the blank PSD with no MCU
involvement.
Inventory build-up of pre-programmed devic-
es. How do I maintain an accurate count of pre-
programmed Flash memory and PLD devices
based on customer demand How many and what
version JTAG is the answer. Build your hardware
with blank PSDs soldered directly to the board and
then custom program just before they are shipped
to the customer. No more labels on chips, and no
more wasted inventory.
Expensive sockets. How do I eliminate the need
for expensive and unreliable sockets JTAG is the
answer. Solder the PSD directly to the circuit
board. Program first time and subsequent times
with JTAG. No need to handle devices and bend
the fragile leads.
In-Application Programming (IAP)Two independent Flash memory arrays are includ-
ed so that the MCU can execute code from one
while erasing and programming the other. Robust
product firmware updates in the filed are possible
over any communication channel (e.g., CAN,
Ethernet, UART, J1850) using this unique archi-
tecture. Designers are relieved of these problems:
Simultaneous READ and WRITE to Flash mem-
ory. How can the MCU program the same memo-
ry from which it executing code It cannot. The
PSD allows the MCU to operate the two Flash
memory blocks concurrently, reading code from
one while erasing and programming the other dur-
ing IAP.
Complex memory mapping. How can I map
these two memories efficiently A programmable
Decode PLD (DPLD) is embedded in the PSD
MODULE. The concurrent PSD memories can be
mapped anywhere in MCU address space, seg-
ment by segment with extremely high address res-
olution. As an option, the secondary Flash
memory can be swapped out of the system mem-
ory map when IAP is complete. A built-in page reg-
ister breaks the MCU address limit.
Separate Program and Data space. How can I
write to Flash memory while it resides in Program
space during field firmware updates My
80C51XA will not allow it. The PSD provides
means to reclassify Flash memory as Data space
during IAP, then back to Program space when
complete.
PSDsoftPSDsoft, a software development tool from ST,
guides you through the design process step-by-
step making it possible to complete an embedded
MCU design capable of ISP/IAP in just hours. Se-
lect your MCU and PSDsoft takes you through the
remainder of the design with point and click entry,
covering PSD selection, pin definitions, program-
mable logic inputs and outputs, MCU memory map
definition, ANSI-C code generation for your MCU,
and merging your MCU firmware with the PSD de-
sign. When complete, two different device pro-
grammers are supported directly from PSDsoft:
FlashLINK (JTAG) and PSDpro.
PSD4256G6V
Figure 2. Logic Diagram Table 1. Pin Names
11/100
PSD4256G6V
Figure 3. TQFP80 Connections
PSD4256G6V
Table 2. TQFP80 Pin Description
13/100
PSD4256G6V
PSD4256G6VNote: Signal names that have multiple names or functions are defined using PSDsoft.
15/100
PSD4256G6V
Figure 4. PSD Block DiagramNote: Additional address lines can be brought in to the device via Port A, B, C, D, or F.
PSD4256G6V
PSD ARCHITECTURAL OVERVIEWPSD devices contain several major functional
blocks. Figure 4, page 15 shows the architecture
of the PSD device family. The functions of each
block are described briefly in the following sec-
tions. Many of the blocks perform multiple func-
tions and are user configurable.
MemoryEach of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discus-
sion can be found in the section entitled “Memory
Blocks“ on page 25.
The 8Mbit primary Flash memory is the main
memory of the PSD. It is divided into 16 equally-
sized sectors that are individually selectable.
The 512Kbit secondary Flash memory is divided
into 4 sectors. Each sector is individually select-
able.
The 256Kbit SRAM is intended for use as a
scratch-pad memory or as an extension to the
MCU SRAM. If an external battery is connected to
the PSD’s Voltage Standby (VSTBY, PE6) signal,
data is retained in the event of power failure.
Each memory block can be located in a different
address space as defined by the user. The access
times for all memory types includes the address
latching and DPLD decoding time.
PLDsThe device contains two PLD blocks, the Decode
PLD (DPLD) and the Complex PLD (CPLD), as
shown in Table 2, page 12, each optimized for a
different function. The functional partitioning of the
PLDs reduces power consumption, optimizes
cost/performance, and eases design entry.
The DPLD is used to decode addresses and to
generate Sector Select signals for the PSD inter-
nal memory and registers. The DPLD has combi-
natorial outputs, while the CPLD can implement
more general user-defined logic functions. The
CPLD has 16 Output Macrocells (OMC) and 8
combinatorial outputs. The PSD also has 24 Input
Macrocells (IMC) that can be configured as inputs
to the PLDs. The PLDs receive their inputs from
the PLD Input Bus and are differentiated by their
output destinations, number of product terms, and
Macrocells.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo Bit in PMMR0 and other bits in
PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD propaga-
tion time when not in the Turbo mode.
I/O PortsThe PSD has 52 I/O pins divided among seven
ports (Port A, B, C, D, E, F, and G). Each I/O pin
can be individually configured for different func-
tions. Ports can be configured as standard MCU I/
O ports, PLD I/O, or latched address outputs for
MCUs using multiplexed address/data buses.
The JTAG pins can be enabled on Port E for In-
System Programming (ISP).
MCU Bus InterfaceThe PSD easily interfaces with most 8-bit or 16-bit
MCUs, either with multiplexed or non-multiplexed
address/data buses. The device is configured to
respond to the MCU’s control pins, which are also
used as inputs to the PLDs.
ISP via JTAG PortIn-System Programming (ISP) can be performed
through the JTAG signals on Port E. This serial in-
terface allows complete programming of the entire
PSD MODULE device. A blank device can be
completely programmed. The JTAG signals (TMS,
TCK, TSTAT, TERR, TDI, TDO) can be multi-
plexed with other functions on Port E. Table 3 indi-
cates the JTAG pin assignments.
Table 3. PLD I/O
Table 4. JTAG Signals on Port E
17/100
PSD4256G6V
In-System Programming (ISP)Using the JTAG signals on Port E, the entire PSD
device (memory, logic, configuration) can be pro-
grammed or erased without the use of the MCU.
In-Application Programming (IAP)The primary Flash memory can also be pro-
grammed, or re-programmed, in-system by the
MCU executing the programming algorithms out of
the secondary Flash memory, or SRAM. The sec-
ondary Flash memory can be programmed the
same way by executing out of the primary Flash
memory. Table 5, page 17 indicates which pro-
gramming methods can program different func-
tional blocks of the PSD.
Page RegisterThe 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or in-
ternal memory and I/O. The Page Register can
also be used to change the address mapping of
the Flash memory blocks into different memory
spaces for IAP.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The PSDalso has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The Turbo Bit in PMMR0 can be
reset to ’0’ and the CPLD latches its outputs and
goes to Standby Mode until the next transition on
its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. See the section enti-
tled “POWER MANAGEMENT” on page 70 for
more details.
Table 5. Methods of Programming Different Functional Blocks of the PSD
PSD4256G6V
DEVELOPMENT SYSTEMThe PSD family is supported by PSDsoft, a Win-
dows-based software development tool (Win-
dows-95, Windows-98, Windows-NT). A PSD
design is quickly and easily produced in a point
and click environment. The designer does not
need to enter Hardware Description Language
(HDL) equations, unless desired, to define PSD
pin functions and memory map information. The
general design flow is shown in Figure 5. PSDsoft
is available from our web site (the address is given
on the back page of this data sheet) or other distri-
bution channels.
PSDsoft directly supports two low cost device pro-
grammers form ST: PSDpro and FlashLINK
(JTAG). Both of these programmers may be pur-
chased through your local distributor/representa-
tive, or directly from our web site using a credit
card. The PSD is also supported by third party de-
vice programmers. See our web site for the current
list.
Figure 5. PSDsoft Development Tool
19/100
PSD4256G6V
PSD REGISTER DESCRIPTION AND ADDRESS OFFSETSTable 6 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al-
located by the user to the internal PSD registers.
Table 6 provides brief descriptions of the registers
in CSIOP space. The following sections give a
more detailed description.
Table 6. Register Address OffsetNote:1. Other registers that are not part of the I/O ports.
PSD4256G6V
REGISTER BIT DEFINITIONAll the registers of the PSD are included here, for
reference. Detailed descriptions of these registers
can be found in the following sections.
Table 7. Data-In Registers - Ports A, B, C, D, E, F, and GNote: Bit Definitions (Read only registers):
READ Port pin status when Port is in MCU I/O input mode.
Table 8. Data-Out Registers - Ports A, B, C, D, E, F, and GNote: Bit Definitions:
Latched data for output to Port pin when pin is configured in MCU I/O output mode.
Table 9. Direction Registers - Ports A, B, C, D, E, F, and GNote: Bit Definitions:
Portpin 0 = Port pin is configured in Input mode (default).
Portpin 1 = Port pin is configured in Output mode.
Table 10. Control Registers - Ports E, F, and GNote: Bit Definitions:
Portpin 0 = Port pin is configured in MCU I/O mode (default).
Portpin 1 = Port pin is configured in Latched Address Out mode.
Table 11. Drive Registers - Ports A, B, D, E, and GNote: Bit Definitions:
Portpin 0 = Port pin is configured for CMOS Output driver (default).
Portpin 1 = Port pin is configured for Open Drain output driver.
Table 12. Enable-Out Registers - Ports A, B, C, and FNote: Bit Definitions (Read only registers):
Portpin 0 = Port pin is in tri-state driver (default).
Portpin
1 = Port pin is enabled.
21/100
PSD4256G6V
Table 13. Input Macrocells - Ports A, B, and C
Note: Bit Definitions (Read only registers):
READ Input Macrocell (IMC7-IMC0) status on Ports A, B, and C.
Table 14. Output Macrocells A Register
Note: Bit Definitions:
WRITE Register: Load MCellA7-MCellA0 with ’0’ or ’1.’
READ Register: Read MCellA7-MCellA0 output status.
Table 15. Out Macrocells B Register
Note: Bit Definitions:
WRITE Register: Load MCellB7-MCellB0 with ’0’ or ’1.’
READ Register: Read MCellB7-MCellB0 output status.
Table 16. Mask Macrocells A Register
Note: Bit Definitions:
McellA_Prot 0 = Allow MCellA flip-flop to be loaded by MCU (default).
McellA_Prot 1 = Prevent MCellA flip-flop from being loaded by MCU.
Table 17. Mask Macrocells B Register
Note: Bit Definitions:
McellB_Prot 0 = Allow MCellB flip-flop to be loaded by MCU (default).
McellB_Prot 1 = Prevent MCellB flip-flop from being loaded by MCU.
Table 18. Flash Memory Protection Register 1
Note: Bit Definitions (Read only register):
Sec_Prot 1 = Primary Flash memory Sector is write protected.
Sec_Prot 0 = Primary Flash memory Sector is not write protected.
Table 19. Flash Memory Protections Register 2
Note: Bit Definitions (Read only register):
Sec_Prot 1 = Primary Flash memory Sector is write protected.
Sec_Prot 0 = Primary Flash memory Sector is not write protected.
PSD4256G6V
Table 20. Flash Boot Protection Register
Note: Bit Definitions:
Sec_Prot 1 = Secondary Flash memory Sector is write protected.
Sec_Prot 0 = Secondary Flash memory Sector is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
Security_Bit 1 = Security Bit in device has been set.
Table 21. JTAG Enable Register
Note: Bit Definitions:
JTAGEnable 1 = JTAG Port is enabled.
JTAGEnable 0 = JTAG Port is disabled.
Table 22. Page Register
Note: Bit Definitions:
Configure Page input to PLD. Default is PGR7-PGR0 = ’0.’
23/100
PSD4256G6V
Table 23. PMMR0 Register
Note: The bits of this register are cleared to zero following power-up. Subsequent Reset (RESET) pulses do not clear the registers.
Bit Definitions:
APD Enable 0 = Automatic Power-down (APD) is disabled.
1 = Automatic Power-down (APD) is enabled.
PLD Turbo 0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
PLD Array CLK 0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo Bit is off.
1 = CLKIN to the PLD AND array is disconnected, saving power.
PLD MCells CLK 0 = CLKIN to the PLD Macrocells is connected.
1 = CLKIN to the PLD Macrocells is disconnected, saving power.
Table 24. PMMR2 Register
Note: For Bit 4, Bit 3, Bit 2: See Table 34, page 47 for the signals that are blocked on pins CNTL0-CNTL2.
Bit Definitions:
PLD Array Addr 0 = Address A7-A0 are connected to the PLD array.
1 = Address A7-A0 are blocked from the PLD array, saving power.
Note: In X A Mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4.
PLD Array CNTL2 0 = CNTL2 input to the PLD AND array is connected.
1 = CNTL2 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL1 0 = CNTL1 input to the PLD AND array is connected.
1 = CNTL1 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL0 0 = CNTL0 input to the PLD AND array is connected.
1 = CNTL0 input to the PLD AND array is disconnected, saving power.
PLD Array ALE 0 = ALE input to the PLD AND array is connected.
1 = ALE input to the PLD AND array is disconnected, saving power.
PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected.
1 = WRH/DBE input to the PLD AND array is disconnected, saving power.
Table 25. VM Register
Note: On RESET, Bits 1-4 are loaded to configurations that are selected by the user in PSDsoft. Bit 0 and Bit 7 are always cleared on RESET.
Bit 0-4 are active only when the device is configured in 8051 Mode.
Bit Definitions:
SR_code 0 = PSEN cannot access SRAM in 80C51XA modes.
1 = PSEN can access SRAM in 80C51XA modes.
Boot_Code 0 = PSEN cannot access Secondary NVM in 80C51XA modes.
1 = PSEN can access Secondary NVM in 80C51XA modes.
FL_Code 0 = PSEN cannot access Primary Flash memory in 80C51XA modes.
1 = PSEN can access Primary Flash memory in 80C51XA modes.
Boot_data 0 = RD cannot access Secondary NVM in 80C51XA modes.
1 = RD can access Secondary NVM in 80C51XA modes.
FL_data 0 = RD cannot access Primary Flash memory in 80C51XA modes.
1 = RD can access Primary Flash memory in 80C51XA modes.
Peripheral mode 0 = Peripheral mode of Port F is disabled.
1 = Peripheral mode of Port F is enabled.
PSD4256G6V
Table 26. Memory_ID0 Register
Note: Bit Definitions:
F_size[3:0] 0h = There is no Primary Flash memory
1h = Primary Flash memory size is 256Kbit
2h = Primary Flash memory size is 512Kbit
3h = Primary Flash memory size is 1Mbit
4h = Primary Flash memory size is 2Mbit
5h = Primary Flash memory size is 4Mbit
6h = Primary Flash memory size is 8Mbit
S_size[3:0] 0h = There is no SRAM
1h = SRAM size is 16Kbit
2h = SRAM size is 32Kbit
3h = SRAM size is 64Kbit
4h = SRAM size is 128Kbit
5h = SRAM size is 256Kbit
Table 27. Memory_ID1 Register
Note: Bit Definitions:
F_size[3:0] 0h = There is no Secondary NVM
1h = Secondary NVM size is 128Kbit
2h = Secondary NVM size is 256Kbit
3h = Secondary NVM size is 512Kbit
S_size[3:0] 0h = Secondary NVM is Flash memory
1h = Secondary NVM is EEPROM
25/100
PSD4256G6V
DETAILED OPERATION
As shown in Figure 4, page 15, the PSD consists
of six major types of functional blocks: Memory Blocks MCU Bus Interface I/O Ports Power Management Unit (PMU) JTAG-ISP Interface The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
Memory Blocks
The PSD has the following memory blocks: Primary Flash memory Secondary Flash memory
–SRAM
The Memory Select signals for these blocks origi-
nate from the Decode PLD (DPLD) and are user-
defined in PSDsoft.
Table 28 summarizes the sizes and organizations
of the memory blocks.
Table 28. Memory Block Size and Organization
PSD4256G6V
Primary Flash Memory and Secondary Flash memory Description
The primary Flash memory is divided evenly into 8
sectors. The secondary Flash memory is divided
into 4 sectors of different size. Each sector of ei-
ther memory block can be separately protected
from Program and Erase cycles.
Flash memory may be erased on a sector-by-sec-
tor basis, and programmed word-by-word. Flash
sector erasure may be suspended while data is
read from other sectors of the block and then re-
sumed after reading.
During a Program or Erase cycle in Flash memory,
the status can be output on the Ready/Busy pin
(PE4). This pin is set up using PSDsoft.
Memory Block Select Signals
The DPLD generates the Select signals for all the
internal memory blocks (see the section entitled
“PLDs”, on page 38). Each of the sectors of the pri-
mary Flash memory has a Select signal (FS0-
FS15) which can contain up to three product
terms. Each of the sectors of the secondary Flash
memory has a Select signal (CSBOOT0-
CSBOOT3) which can contain up to three product
terms. Having three product terms for each Select
signal allows a given sector to be mapped in differ-
ent areas of system memory. When using a MCU
with separate Program and Data space
(80C51XA), these flexible Select signals allow dy-
namic re-mapping of sectors from one memory
space to the other before and after IAP. The
SRAM block has a single Select signal (RS0).
Ready/Busy (PE4)
This signal can be used to output the Ready/Busy
status of the PSD. The output is a '0' (Busy) when
a Flash memory block is being written to, or when
a Flash memory block is being erased. The output
is a '1' (Ready) when no WRITE or Erase cycle is
in progress.
Memory Operation
The primary Flash memory and secondary Flash
memory are addressed through the MCU Bus In-
terface. The MCU can access these memories in
one of two ways: The MCU can execute a typical bus WRITE or
READ operation just as it would if accessing a
RAM or ROM device using standard bus cycles. The MCU can execute a specific instruction that
consists of several WRITE and READ
operations. This involves writing specific data
patterns to special addresses within the Flash
memory to invoke an embedded algorithm.
These instructions are summarized in Table 29,
page 27.
Typically, the MCU can read Flash memory using
READ operations, just as it would read a ROM de-
vice. However, Flash memory can only be erased
and programmed using specific instructions. For
example, the MCU cannot write a single byte di-
rectly to Flash memory as one would write a byte
to RAM. To program a word into Flash memory,
the MCU must execute a Program instruction, then
test the status of the Programming event. This sta-
tus test is achieved by a READ operation or polling
Ready/Busy (PE4).
Flash memory can also be read by using special
instructions to retrieve particular Flash device in-
formation (sector protect status and ID).
27/100
PSD4256G6V
Table 29. 16-bit Instructions
Note:1. All bus cycles are WRITE bus cycles, except the ones with the “Read” label All values are in hexadecimal:
X = “Don’t care.” Addresses of the form XXXXh, in this table, must be even addresses
RA = Address of the memory location to be read
RD = Data read from location RA during the READ cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of WRITE Strobe (WR, CNTL0).
PA is an even address for PSD in word programming mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of WRITE Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS15 or CSBOOT0-CSBOOT3) of the sector to be
erased, or verified, must be Active (High). Sector Select (FS0 to FS15 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft. Only address bits A11-A0 are used in instruction decoding. No Unlock or instruction cycles are required when the device is in the READ Mode The RESET instruction is required to return to the READ Mode after reading the Flash ID, or after reading the Sector Protection
Status, or if the Error Flag Bit (DQ5/DQ13) goes High. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80μs. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1,A0) = (1,0). The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass
mode.
11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is
intended. The MCU must retrieve, for example, the code from the secondary Flash memory when reading the Sector Protection
Status of the primary Flash memory.
14. All WRITE bus cycles in an instruction are byte-WRITE to an even address (XA4Ah or X554h). A Flash memory Program bus cycle
writes a word to an even address.
PSD4256G6V
INSTRUCTIONS
An instruction consists of a sequence of specific
operations. Each received byte is sequentially de-
coded by the PSD and not executed as a standard
WRITE operation. The instruction is executed
when the correct number of bytes are properly re-
ceived and the time between two consecutive
bytes is shorter than the time-out period. Some in-
structions are structured to include READ opera-
tions after the initial WRITE operations.
The instruction must be followed exactly. Any in-
valid combination of instruction bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into READ
Mode (Flash memory is read like a ROM device).
The PSD supports the instructions summarized in
Table 29, page 27: Erase memory by chip or sector Suspend or resume sector erase Program a Word RESET to READ Mode READ Primary Flash Identifier value READ Sector Protection Status Bypass
These instructions are detailed in Table 29, page
27. For efficient decoding of the instructions, the
first two bytes of an instruction are the coded cy-
cles and are followed by an instruction byte or con-
firmation byte. The coded cycles consist of writing
the data AAh to address XAAAh during the first cy-
cle and data 55h to address X554h during the sec-
ond cycle (unless the Bypass instruction feature is
used, as described later). Address signals A15-
A12 are “Don’t care” during the instruction WRITE
cycles. However, the appropriate Sector Select
signal (FS0-FS15, or CSBOOT0-CSBOOT3) must
be selected.
The primary and secondary Flash memories have
the same instruction set (except for READ Primary
Flash Identifier). The Sector Select signals deter-
mine which Flash memory is to receive and exe-
cute the instruction. The primary Flash memory is
selected if any one of its Sector Select signals
(FS0-FS15) is High, and the secondary Flash
memory is selected if any one of its Sector Select
signals (CSBOOT0-CSBOOT3) is High.
Power-up Condition
The PSD internal logic is reset upon Power-up to
the READ Mode. Sector Select (FS0-FS15 and
CSBOOT0-CSBOOT3) must be held Low, and
WRITE Strobe (WR/WRL, CNTL0) High, during
Power-up for maximum security of the data con-
tents and to remove the possibility of data being
written on the first edge of WRITE Strobe (WR/
WRL, CNTL0). Any WRITE cycle initiation is
locked when VCC is below VLKO.
READ
Under typical conditions, the MCU may read the
primary Flash memory, or secondary Flash mem-
ory, using READ operations just as it would a
ROM or RAM device. Alternately, the MCU may
use READ operations to obtain status information
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these memory blocks. The
following sections describe these READ functions.
READ Memory Contents
Primary Flash memory and secondary Flash
memory are placed in the READ Mode after Pow-
er-up, chip reset, or a Reset Flash instruction (see
Table 29, page 27). The MCU can read the mem-
ory contents of the primary Flash memory, or the
secondary Flash memory by using READ opera-
tions any time the READ operation is not part of an
instruction.
READ Primary Flash Identifier
The primary Flash memory identifier is read with
an instruction composed of 4 operations: 3 specific
WRITE operations and a READ operation (see Ta-
ble 29, page 27). The identifier for the primary
Flash memory is E7h. The secondary Flash mem-
ory does not support this instruction.
READ Memory Sector Protection Status
The Flash memory Sector Protection Status is
read with an instruction composed of four opera-
tions: three specific WRITE operations and a
READ operation (see Table 29, page 27). The
READ operation produces 01h if the Flash memo-
ry sector is protected, or 00h if the sector is not
protected.
The sector protection status for all NVM blocks
(primary Flash memory, or secondary Flash mem-
ory) can be read by the MCU accessing the Flash
Protection and Flash Boot Protection registers in
PSD I/O space. See the section entitled “Flash
Memory Sector Protect”, on page 34, for register
definitions.
29/100
PSD4256G6V
Reading the Erase/Program Status Bits
The PSD provides several status bits to be used
by the MCU to confirm the completion of an Erase
or Program cycle of Flash memory. These status
bits minimize the time that the MCU spends per-
forming these tasks and are defined in Table 30.
The status byte resides in an even location, and
can be read as many times as needed. Also note
that DQ15-DQ8 is an even byte for Motorola
MCUs with a 16-bit data bus.
For Flash memory, the MCU can perform a READ
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algorithm. See the section entitled
“PROGRAMMING FLASH MEMORY”, on page
31, for details.
Table 30. Status Bits
Table 31. Status Bits for Motorola 16-bit MCU
Notes:X = Not guaranteed value, can be read either ’1’ or ’0.’
DQ15-DQ0 represent the Data Bus bits, D15-D0.
FS0-FS15/CSBOOT0-CSBOOT3 are active High.
PSD4256G6V
Data Polling (DQ7) - DQ15 for Motorola
When erasing or programming in Flash memory,
the Data Polling Bit (DQ7/DQ15) outputs the com-
plement of the bit being entered for programming/
writing on the DQ7/DQ15 Bit. Once the Program
instruction or the WRITE operation is completed,
the true logic value is read on the Data Polling Bit
(DQ7/DQ15) (in a READ operation). Data Polling is effective after the fourth WRITE
pulse (for a Program instruction) or after the
sixth WRITE pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memory sector being erased. During an Erase cycle, the Data Polling Bit
(DQ7/DQ15) outputs a ’0.’ After completion of
the cycle, the Data Polling Bit (DQ7/DQ15)
outputs the last bit programmed (it is a ’1’ after
erasing). If the location to be programmed is in a
protected Flash memory sector, the instruction
is ignored. If all the Flash memory sectors to be erased are
protected, the Data Polling Bit (DQ7/DQ15) is
reset to '0' for about 100μs, and then returns to
the value from the previously addressed
location. No erasure is performed.
Toggle Flag (DQ6) – DQ14 for Motorola
The PSD offers another way for determining when
the Flash memory Program cycle is completed.
During the internal WRITE operation and when ei-
ther FS0-FS15 or CSBOOT0-CSBOOT3 is true,
the Toggle Flag Bit (DQ6/DQ14) toggles from 0 to
’1’ and ’1’ to ’0’ on subsequent attempts to read any
word of the memory.
When the internal cycle is complete, the toggling
stops and the data read on the Data Bus D0-D7 is
the value from the addressed memory location.
The device is now accessible for a new READ or
WRITE operation. The cycle is finished when two
successive READs yield the same output data. The Toggle Flag Bit (DQ6/DQ14) is effective
after the fourth WRITE pulse (for a Program
instruction) or after the sixth WRITE pulse (for
an Erase instruction). If the location to be programmed belongs to a
protected Flash memory sector, the instruction
is ignored. If all the Flash memory sectors selected for
erasure are protected, the Toggle Flag Bit
(DQ6/DQ14) toggles to '0' for about 100μs and
then returns to the value from the previously
addressed location.
Error Flag (DQ5) – DQ13 for Motorola
During a normal Program or Erase cycle, the Error
Flag Bit (DQ5/DQ13) is reset to ’0.’ This bit is set
to ’1’ when there is a failure during a Flash memory
Program, Sector Erase, or Bulk Erase cycle.
In the case of Flash memory programming, the Er-
ror Flag Bit (DQ5/DQ13) indicates the attempt to
program a Flash memory bit, or bits, from the pro-
grammed state, 0, to the erased state, ’1,’ which is
not a valid operation. The Error Flag Bit (DQ5/
DQ13) may also indicate a Time-out condition
while attempting to program a word.
In case of an error in a Flash memory Sector Erase
or Word Program cycle, the Flash memory sector
in which the error occurred or to which the pro-
grammed location belongs must no longer be
used. Other Flash memory sectors may still be
used. The Error Flag Bit (DQ5/DQ13) is reset after
a RESET instruction. A RESET instruction is re-
quired after detecting an error on the Error Flag Bit
(DQ5/DQ13).
Erase Time-out Flag (DQ3) – DQ11 for Motorola
The Erase Time-out Flag Bit (DQ3/DQ11) reflects
the time-out period allowed between two consecu-
tive Sector Erase instructions. The Erase Time-out
Flag Bit (DQ3/DQ11) is reset to ’0’ after a Sector
Erase cycle for a period of 100μs + 20% unless an
additional Sector Erase instruction is decoded. Af-
ter this period, or when the additional Sector Erase
instruction is decoded, the Erase Time-out Flag Bit
(DQ3/DQ11) is set to '1.'
31/100
PSD4256G6V
PROGRAMMING FLASH MEMORY
Flash memory must be erased prior to being pro-
grammed. The MCU may erase Flash memory all
at once or by-sector. Although erasing Flash mem-
ory occurs on a sector or device basis, program-
ming Flash memory occurs on a word basis.
The primary and secondary Flash memories re-
quire the MCU to send an instruction to program a
word or to erase sectors (see Table 29, page 27).
Once the MCU issues a Flash memory Program or
Erase instruction, it must check the status bits for
completion. The embedded algorithms that are in-
voked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or Ready/Busy (PE4) signal.
Data Polling
Polling on the Data Polling Bit (DQ7/DQ15) is a
method of checking whether a Program or Erase
cycle is in progress or has completed. Figure 6
shows the Data Polling algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the word to be pro-
grammed in Flash memory to check the status.
The Data Polling Bit (DQ7/DQ15) becomes the
complement of the corresponding bit of the original
data word to be programmed. The MCU continues
to poll this location, comparing data and monitor-
ing the Error Flag Bit (DQ5/DQ13). When the Data
Polling Bit (DQ7/DQ15) matches the correspond-
ing bit of the original data, and the Error Flag Bit
(DQ5/DQ13) remains ’0,’ the embedded algorithm
is complete. If the Error Flag Bit (DQ5/DQ13) is ’1,’
the MCU should test the Data Polling Bit (DQ7/
DQ15) again since the Data Polling Bit (DQ7/
DQ15) may have changed simultaneously with the
Error Flag Bit (DQ5/DQ13) (see Figure 6).
The Error Flag Bit (DQ5/DQ13) is set if either an
internal time-out occurred while the embedded al-
gorithm attempted to program the location or if the
MCU attempted to program a ’1’ to a bit that was
not erased (not erased is logic ’0’).
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
word that was written to the Flash memory with the
word that was intended to be written.
When using the Data Polling method during an
Erase cycle, Figure 6 still applies. However, the
Data Polling Bit (DQ7/DQ15) is ’0’ until the Erase
cycle is complete. A ’1’ on the Error Flag Bit (DQ5/
DQ13) indicates a time-out condition on the Erase
cycle, a 0 indicates no error. The MCU can read
any even location within the sector being erased to
get the Data Polling Bit (DQ7/DQ15) and the Error
Flag Bit (DQ5/DQ13).
PSDsoft generates ANSI C code functions that im-
plement these Data Polling algorithms.
Figure 6. Data Polling Flowchart
PSD4256G6V
Data Toggle
Checking the Toggle Flag Bit (DQ6/DQ14) is an-
other method of determining whether a Program or
Erase cycle is in progress or has completed. Fig-
ure 7 shows the Data Toggle algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location to be programmed in
Flash memory to check the status. The Toggle
Flag Bit (DQ6/DQ14) toggles each time the MCU
reads this location until the embedded algorithm is
complete. The MCU continues to read this loca-
tion, checking the Toggle Flag Bit (DQ6/DQ14)
and monitoring the Error Flag Bit (DQ5/DQ13).
When the Toggle Flag Bit (DQ6/DQ14) stops tog-
gling (two consecutive READs yield the same val-
ue), and the Error Flag Bit (DQ5/DQ13) remains
’0,’ the embedded algorithm is complete. If the Er-
ror Flag Bit (DQ5/DQ13) is ’1,’ the MCU should
test the Toggle Flag Bit (DQ6/DQ14) again, since
the Toggle Flag Bit (DQ6/DQ14) may have
changed simultaneously with the Error Flag Bit
(DQ5/DQ13) (see Figure 7).
The Error Flag Bit (DQ5/DQ13) is set if either an
internal time-out occurred while the embedded al-
gorithm attempted to program, or if the MCU at-
tempted to program a ’1’ to a bit that was not
erased (not erased is logic ’0’).
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
word that was written to Flash memory with the
word that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 7 still applies. the Toggle Flag
Bit (DQ6/DQ14) toggles until the Erase cycle is
complete. A ’1’ on the Error Flag Bit (DQ5/DQ13)
indicates a time-out condition on the Erase cycle,
a ’0’ indicates no error. The MCU can read any
even location within the sector being erased to get
the Toggle Flag Bit (DQ6/DQ14) and the Error
Flag Bit (DQ5/DQ13).
PSDsoft generates ANSI C code functions which
implement these Data Toggling algorithms.
Unlock Bypass
The Unlock Bypass instruction allows the system
to program words to the Flash memories faster
than using the standard Program instruction. The
Unlock Bypass mode is entered by first initiating
two Unlock cycles. This is followed by a third
WRITE cycle containing the Unlock Bypass com-
mand, 20h (as shown in Table 29, page 27). The
Flash memory then enters the Unlock Bypass
mode.
A two-cycle Unlock Bypass Program instruction is
all that is required to program in this mode. The
first cycle in this instruction contains the Unlock
Bypass Program command, A0h. The second cy-
cle contains the program address and data. Addi-
tional data is programmed in the same manner.
This mode dispense with the initial two Unlock cy-
cles required in the standard Program instruction,
resulting in faster total programming time.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset in-
structions are valid.
To exit the Unlock Bypass mode, the system must
issue the two-cycle Unlock Bypass Reset instruc-
tion. The first cycle must contain the data 90h; the
second cycle the data 00h. Addresses are “Don’t
care” for both cycles. The Flash memory then re-
turns to READ Mode.
Figure 7. Data Toggle Flowchart
33/100
PSD4256G6V
ERASING FLASH MEMORY
Flash Bulk Erase
The Flash Bulk Erase instruction uses six WRITE
operations followed by a READ operation of the
status register, as described in Table 29, page 27.
If any byte of the Bulk Erase instruction is wrong,
the Bulk Erase instruction aborts and the device is
reset to the READ Memory mode.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5/
DQ13), the Toggle Flag Bit (DQ6/DQ14), and the
Data Polling Bit (DQ7/DQ15), as detailed in the
section entitled “PROGRAMMING FLASH MEM-
ORY”, on page 31. The Error Flag Bit (DQ5/DQ13)
returns a '1' if there has been an Erase Failure
(maximum number of Erase cycles have been ex-
ecuted).
It is not necessary to program the memory with
00h because the PSD automatically does this be-
fore erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.
Flash Sector Erase
The Sector Erase instruction uses six WRITE op-
erations, as described in Table 29, page 27. Addi-
tional Flash Sector Erase confirm commands and
Flash memory sector addresses can be written
subsequently to erase other Flash memory sec-
tors in parallel, without further coded cycles, if the
additional commands are transmitted in a shorter
time than the time-out period of about 100μs. The
input of a new Sector Erase command restarts the
time-out period.
The status of the internal timer can be monitored
through the level of the Erase Time-out Flag Bit
(DQ3/DQ11). If the Erase Time-out Flag Bit (DQ3/
DQ11) is '0,' the Sector Erase instruction has been
received and the time-out period is counting. If the
Erase Time-out Flag Bit (DQ3/DQ11) is '1,' the
time-out period has expired and the PSD is busy
erasing the Flash memory sector(s). Before and
during Erase time-out, any instruction other than
Suspend Sector Erase and Resume Sector Erase,
abort the cycle that is currently in progress, and re-
set the device to READ Mode. It is not necessary
to program the Flash memory sector with 00h as
the PSD does this automatically before erasing.
During a Sector Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5/
DQ13), the Toggle Flag Bit (DQ6/DQ14), and the
Data Polling Bit (DQ7/DQ15), as detailed in the
section entitled “PROGRAMMING FLASH MEM-
ORY”, on page 31.
During execution of the Erase cycle, the Flash
memory accepts only RESET and Suspend Sec-
tor Erase instructions. Erasure of one Flash mem-
ory sector may be suspended, in order to read
data from another Flash memory sector, and then
resumed.
Suspend Sector Erase
When a Sector Erase cycle is in progress, the Sus-
pend Sector Erase instruction can be used to sus-
pend the cycle by writing 0B0h to any even
address when an appropriate Sector Select (FS0-
FS15 or CSBOOT0-CSBOOT3) is High. (See Ta-
ble 29, page 27). This allows reading of data from
another Flash memory sector after the Erase cycle
has been suspended. Suspend Sector Erase is
accepted only during the Flash Sector Erase in-
struction execution and defaults to READ Mode. A
Suspend Sector Erase instruction executed during
an Erase time-out period, in addition to suspend-
ing the Erase cycle, terminates the time out period.
The Toggle Flag Bit (DQ6/DQ14) stops toggling
when the PSD internal logic is suspended. The
status of this bit must be monitored at an address
within the Flash memory sector being erased. The
Toggle Flag Bit (DQ6/DQ14) stops toggling be-
tween 0.1μs and 15μs after the Suspend Sector
Erase instruction has been executed. The PSD is
then automatically set to READ Mode.
If an Suspend Sector Erase instruction was exe-
cuted, the following rules apply: Attempting to read from a Flash memory sector
that was being erased outputs invalid data. Reading from a Flash memory sector that was
not being erased is valid. The Flash memory cannot be programmed, and
only responds to Resume Sector Erase and RE-
SET instructions (READ is an operation and is
allowed).
–If a RESET instruction is received, data in the
Flash memory sector that was being erased is
invalid.
Resume Sector Erase
If a Suspend Sector Erase instruction was previ-
ously executed, the Erase cycle may be resumed
with this instruction. The Resume Sector Erase in-
struction consists of writing 030h to any even ad-
dress while an appropriate Sector Select (FS0-
FS15 or CSBOOT0-CSBOOT3) is High. (See Ta-
ble 29, page 27.)
PSD4256G6V
SPECIFIC FEATURES
Flash Memory Sector Protect
Each sector of Primary or Secondary Flash mem-
ory can be separately protected against Program
and Erase cycles. Sector Protection provides ad-
ditional data security because it disables all Pro-
gram or Erase cycles. This mode can be activated
(or deactivated) through the JTAG-ISP Port or a
Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft program. This automatically
protects selected sectors when the device is pro-
grammed through the JTAG Port or a Device Pro-
grammer. Flash memory sectors can be
unprotected to allow updating of their contents us-
ing the JTAG Port or a Device Programmer. The
MCU can read (but cannot change) the sector pro-
tection bits.
Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a READ of the protected data.
This allows a guarantee of the retention of the Pro-
tection status.
The sector protection status can be read by the
MCU through the Flash memory protection and
Secondary Flash memory protection registers (in
the CSIOP block) or use the READ Sector Protec-
tion instruction. See Table 18, page 21 to Table
20, page 22.
RESET
The RESET instruction consists of one WRITE cy-
cle (see Table 29, page 27). It can also be option-
ally preceded by the standard two WRITE
decoding cycles (writing AAh to AAAh, and 55h to
554h).
The RESET instruction must be executed after: Reading the Flash Protection Status or Flash ID An Error condition has occurred (and the device
has set the Error Flag Bit (DQ5/DQ13) to '1')
during a Flash memory Program or Erase cycle.
The RESET instruction immediately puts the Flash
memory back into normal READ Mode. However,
if there is an error condition (with the Error Flag Bit
(DQ5/DQ13) set to '1') the Flash memory will re-
turn to the READ Mode in 25μs after the RESET
instruction is issued.
The RESET instruction is ignored when it is issued
during a Program or Bulk Erase cycle of the Flash
memory. The RESET instruction aborts any on-
going Sector Erase cycle, and returns the Flash
memory to the normal READ Mode in 25μs.
Reset (RESET) Pin
A pulse on the Reset (RESET) pin aborts any cy-
cle that is in progress, and resets the Flash mem-
ory to the READ Mode. When the reset occurs
during a Program or Erase cycle, the Flash mem-
ory takes up to 25 μs to return to the READ Mode.
It is recommended that the Reset (RESET) pulse
(except for Power On Reset, as described on page
74) be at least 25μs so that the Flash memory is
always ready for the MCU to retrieve the bootstrap
instructions after the RESET cycle is complete.
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to three product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to the Voltage Standby (VSTBY, PE6) line. If you
have an external battery connected to the PSD,
the contents of the SRAM are retained in the event
of a power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at 2V
or greater. If the supply voltage falls below the bat-
tery voltage, an internal power switch-over to the
battery occurs.
PE7 can be configured as an output that indicates
when power is being drawn from the external bat-
tery. This Battery-on Indicator (VBATON, PE7) sig-
nal is High when the supply voltage falls below the
battery voltage and the battery on Voltage Stand-
by (VSTBY, PE6) is supplying power to the internal
SRAM.
SRAM Select (RS0), Voltage Standby (VSTBY,
PE6) and Battery-on Indicator (VBATON, PE7) are
all configured using PSDsoft.
35/100
PSD4256G6V
MEMORY SELECT SIGNALS
The Primary Flash Memory Sector Select (FS0-
FS15), Secondary Flash Memory Sector Select
(CSBOOT0-CSBOOT3) and SRAM Select (RS0)
signals are all outputs of the DPLD. They are de-
fined using PSDsoft. The following rules apply to
the equations for these signals: Primary Flash memory and secondary Flash
memory Sector Select signals must not be larg-
er than the physical sector size. Any primary Flash memory sector must notbe
mapped in the same memory space as another
Flash memory sector. A secondary Flash memory sector must notbe
mapped in the same memory space as another
secondary Flash memory sector. SRAM, I/O, and Peripheral I/O spaces must not
overlap. A secondary Flash memory sector may overlap
a primary Flash memory sector. In case of over-
lap, priority is given to the secondary Flash
memory sector. SRAM, I/O, and Peripheral I/O spaces may
overlap any other memory sector. Priority is giv-
en to the SRAM, I/O, or Peripheral I/O.
Example
FS0 is valid when the address is in the range of
8000h to BFFFh, CSBOOT0 is valid from 8000h to
9FFFh, and RS0 is valid from 8000h to 87FFh.
Any address in the range of RS0 always accesses
the SRAM. Any address in the range of CSBOOT0
greater than 87FFh (and less than 9FFFh) auto-
matically addresses secondary Flash memory
segment 0. Any address greater than 9FFFh ac-
cesses the primary Flash memory segment 0. You
can see that half of the primary Flash memory seg-
ment 0 and one-fourth of secondary Flash memory
segment 0 cannot be accessed in this example.
Also note that an equation that defined FS1 to any-
where in the range of 8000h to BFFFh would not
be valid.
Figure 8 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not overlap. Level 1 has the highest priority and
level 3 has the lowest.
Memory Select Configuration for MCUs with
Separate Program and Data Spaces
The 80C31 and compatible family of MCUs can be
configured to have separate address spaces for
Program memory (selected using Program Select
Enable (PSEN, CNTL2)) and Data memory (se-
lected using READ Strobe (RD, CNTL1)). Any of
the memories within the PSD can reside in either
space or both spaces. This is controlled through
manipulation of the VM register that resides in the
CSIOP space.
The VM register is set using PSDsoft to have an
initial value. It can subsequently be changed by
the MCU so that memory mapping can be
changed on-the-fly.
For example, you may wish to have SRAM and pri-
mary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the secondary
Flash memory and primary Flash memory. This is
easily done with the VM register by using PSDsoft
to configure it for Boot-up and having the MCU
change it when desired.
Table 25, page 23 describes the VM Register.
Figure 8. Priority Level of Memory and I/O
Components
PSD4256G6V
Configuration Modes for MCUs with Separate Program and Data Spaces
Separate Space Modes. Program space is sep-
arated from Data space. For example, Program
Select Enable (PSEN, CNTL2) is used to access
the program code from the primary Flash memory,
while READ Strobe (RD, CNTL1) is used to ac-
cess data from the secondary Flash memory,
SRAM and I/O Port blocks. This configuration re-
quires the VM register to be set to 0Ch (see Figure
9).
Combined Space Modes
The Program and Data spaces are combined into
one memory space that allows the primary Flash
memory, secondary Flash memory, and SRAM to
be accessed by either Program Select Enable
(PSEN, CNTL2) or READ Strobe (RD, CNTL1).
For example, to configure the primary Flash mem-
ory in Combined space, Bits 2 and 4 of the VM reg-
ister are set to 1 (see Figure 10).
80C31 Memory Map Example
See the Application Notes for examples.
Figure 9. 8031 Memory Modules – Separate Space
Figure 10. 8031 Memory Modules – Combined Space
37/100
PSD4256G6V
PAGE REGISTER
The 8-bit Page Register increases the addressing
capability of the MCU by a factor of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0-
PGR7) are inputs to the DPLD decoder and can be
included in the Sector Select (FS0-FS15,
CSBOOT0-CSBOOT3), and SRAM Select (RS0)
equations.
If memory paging is not needed, or if not all eight
page register bits are needed for memory paging,
these bits may be used in the CPLD for general
logic. See Application Note AN1154.
Table 22, page 22 and Figure 11 show the Page
Register. The eight flip-flops in the register are
connected to the internal data bus (D0-D7). The
MCU can write to or read from the Page Register.
The Page Register can be accessed at address lo-
cation CSIOP + E0h.
Figure 11. Page Register
MEMORY ID REGISTERS
The 8-bit “Read only” Memory Status Registers
are included in the CSIOP space. The user can
determine the memory configuration of the PSD
device by reading the Memory ID0 and Memory
ID1 registers. The content of the registers is de-
fined as shown in Table 26, page 24 and Table 27,
page 24.
PSD4256G6V
PLDS
The PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
using PSDsoft, the logic is programmed into the
device and available upon Power-up.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in the following sections. Figure
12, page 39 shows the configuration of the PLDs.
The DPLD performs address decoding for internal
components, such as memory, registers, and I/O
ports Select signals.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0-
ECS2) signals.
The AND Array is used to form product terms.
These product terms are specified using PSDsoft.
An Input Bus consisting of 82 signals is connected
to the PLDs. The signals are shown in Table 32.
The Turbo Bit in PSD
The PLDs in the PSD4256G6V can minimize pow-
er consumption by switching to standby when in-
puts remain unchanged for an extended time of
about 70ns. Resetting the Turbo Bit to ’0’ (Bit 3 of
the PMMR0 register) automatically places the
PLDs into standby if no inputs are changing. Turn-
ing the Turbo mode off increases propagation de-
lays while reducing power consumption. See the
section entitled “POWER MANAGEMENT”, on
page 70, on how to set the Turbo Bit.
Additionally, five bits are available in the PMMR2
register to block MCU control signals from entering
the PLDs. This reduces power consumption and
can be used only when these MCU control signals
are not used in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
Table 32. DPLD and CPLD Inputs
Note:1. The address inputs are A19-A4 in 80C51XA mode.
39/100
PSD4256G6V
Figure 12. PLD Diagram
PSD4256G6V
DECODE PLD (DPLD)
The DPLD, shown in Figure 13, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals: 8 Sector Select (FS0-FS15) signals for the
primary Flash memory (three product terms
each) 4 Sector Select (CSBOOT0-CSBOOT3) signals
for the secondary Flash memory (three product
terms each) 1 internal SRAM Select (RS0) signal (three
product terms) 1 internal CSIOP Select (PSD Configuration
Register) signal 1 JTAG Select signal (enables JTAG-ISP on
Port E) 2 internal Peripheral Select signals (Peripheral
I/O mode).
Figure 13. DPLD Logic Array
Note:1. The address inputs are A19-A4 when in 80C51XA mode Additional address lines can be brought in the PSD via Port A, B, C, D, or F.
41/100
PSD4256G6V
COMPLEX PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate eight External Chip Se-
lect (ECS0-ECS7), routed to Port C or Port F.
Although External Chip Select (ECS0-ECS7) can
be produced by any Output Macrocell (OMC),
these eight External Chip Select (ECS0-ECS7) on
Port C or Port F do not consume any Output Mac-
rocells (OMC).
As shown in Figure 14, the CPLD has the following
blocks: 24 Input Macrocells (IMC) 16 Output Macrocells (OMC) Product Term Allocator AND Array capable of generating up to 196
product terms Four I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
Figure 14. Macrocell and I/O Port
PSD4256G6V
Output Macrocell (OMC)
Eight of the Output Macrocells (OMC) are con-
nected to Ports A pins and are named as McellA0-
McellA7. The other eight Macrocells are connect-
ed to Ports B pins and are named as McellB0-
McellB7.
The Output Macrocell (OMC) architecture is
shown in Figure 15, page 44. As shown in the fig-
ure, there are native product terms available from
the AND Array, and borrowed product terms avail-
able (if unused) from other Output Macrocells
(OMC). The polarity of the product term is con-
trolled by the XOR gate. The Output Macrocell
(OMC) can implement either sequential logic, us-
ing the flip-flop element, or combinatorial logic.
The multiplexer selects between the sequential or
combinatorial logic outputs. The multiplexer output
can drive a port pin and has a feedback path to the
AND Array inputs.
The flip-flop in the Output Macrocell (OMC) block
can be configured as a D, T, JK, or SR type in the
PSDsoft program. The flip-flop’s clock, preset, and
clear inputs may be driven from a product term of
the AND Array. Alternatively, the external CLKIN
(PD1) signal can be used for the clock input to the
flip-flop. The flip-flop is clocked on the rising edge
of CLKIN (PD1). The preset and clear are active
High inputs. Each clear input can use up to two
product terms.
Table 33. Output Macrocell Port and Data Bit Assignments
Note:1. D7-D0 are used for loading or reading in 8-bit mode.
43/100
PSD4256G6V
Product Term Allocator
The CPLD has a Product Term Allocator. PSDsoft,
uses the Product Term Allocator to borrow and
place product terms from one Macrocell to anoth-
er. The following list summarizes how product
terms are allocated: McellA0-McellA7 all have three native product
terms and may borrow up to six more McellB0-McellB3 all have four native product
terms and may borrow up to five more McellB4-McellB7 all have four native product
terms and may borrow up to six more.
Each Macrocell may only borrow product terms
from certain other Macrocells. Product terms al-
ready in use by one Macrocell are not available for
another Macrocell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required, which consume other Output Macro-
cells (OMC). If external product terms are used,
extra delay is added for the equation that required
the extra product terms. This is called product term
expansion. PSDsoft performs this expansion as
needed.
Loading and Reading the Output Macrocells
(OMC)
The Output Macrocells (OMC) block occupies a
memory location in the MCU address space, as
defined by the CSIOP (see Figure 21 to Figure 30
for examples of the basic connections between the
PSD and some popular MCUs). The PSD Control
input pins are labeled as to the MCU function for
which they are configured. The MCU bus interface
is specified using the PSDsoft Express Configura-
tion. The flip-flops in each of the 16 Output Macro-
cells (OMC) can be loaded from the data bus by a
MCU. Loading the Output Macrocells (OMC) with
data from the MCU takes priority over internal
functions. As such, the preset, clear, and clock in-
puts to the flip-flop can be overridden by the MCU.
The ability to load the flip-flops and read them
back is useful in such applications as loadable
counters and shift registers, mailboxes, and hand-
shaking protocols.
Data is loaded to the Output Macrocells (OMC) on
the trailing edge of WRITE Strobe (WR/WRL,
CNTL0).
The OMC Mask Register
There is one Mask Register for each of the two
groups of eight Output Macrocells (OMC). The
Mask Registers can be used to block the loading
of data to individual Output Macrocells (OMC).
The default value for the Mask Registers is 00h,
which allows loading of the Output Macrocells
(OMC). When a given bit in a Mask Register is set
to a 1, the MCU is blocked from writing to the as-
sociated Output Macrocells (OMC). For example,
suppose McellA0-McellA3 are being used for a
state machine. You would not want a MCU WRITE
to McellA to overwrite the state machine registers.
Therefore, you would want to load the Mask Reg-
ister for McellA (Mask Macrocell A) with the value
0Fh.
The Output Enable of the OMC
The Output Macrocells (OMC) can be connected
to an I/O port pin as a PLD output. The output en-
able of each port pin driver is controlled by a single
product term from the AND Array, ORed with the
Direction Register output. The pin is enabled upon
Power-up if no output enable equation is defined
and if the pin is declared as a PLD output in PSD-
soft.
If the Output Macrocell (OMC) output is declared
as an internal node and not as a port pin output in
the PSDabel file, then the port pin can be used for
other I/O functions. The internal node feedback
can be routed as an input to the AND Array.
PSD4256G6V
Figure 15. CPLD Output Macrocell
45/100
PSD4256G6V
Input Macrocells (IMC)
The CPLD has 24 Input Macrocells (IMC), one for
each pin on Ports A, B, and C. The architecture of
the Input Macrocells (IMC) is shown in Figure 16.
The Input Macrocells (IMC) are individually config-
urable, and can be used as a latch, register, or to
pass incoming Port signals prior to driving them
onto the PLD input bus. The outputs of the Input
Macrocells (IMC) can be read by the MCU through
the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND Array or the
MCU Address Strobe (ALE/AS). Each product
term output is used to latch or clock four Input
Macrocells (IMC). Port inputs 3-0 can be con-
trolled by one product term and 7-4 by another.
Configurations for the Input Macrocells (IMC) are
specified by PSDsoft (see Application Note
AN1171). Outputs of the Input Macrocells (IMC)
can be read by the MCU via the IMC buffer. See
Figure 21, page 51 to Figure 26, page 57 for ex-
amples of the basic connections between the PSD
and some popular MCUs. The PSD Control input
pins are labeled as to the MCU function for which
they are configured. The MCU bus interface is
specified using the “I/O Ports”, on page 16.
Input Macrocells (IMC) can use Address Strobe
(ALE/AS, PD0) to latch address bits higher than
A15. Any latched addresses are routed to the
PLDs as inputs.
Input Macrocells (IMC) are particularly useful with
handshaking communication applications where
two processors pass data back and forth through
a common mailbox. Figure 18, page 46 shows a
typical configuration where the Master MCU writes
to the Port A Data Out Register. This, in turn, can
be read by the Slave MCU via the activation of the
“Slave-READ” output enable product term.
The Slave can also write to the Port A Input Mac-
rocells (IMC) and the Master can then read the In-
put Macrocells (IMC) directly.
Note that the “Slave-READ” and “Slave-Wr” sig-
nals are product terms that are derived from the
Slave MCU inputs READ Strobe (RD, CNTL1),
WRITE Strobe (WR/WRL, CNTL0), and
Slave_CS.
Figure 16. Input Macrocell
PSD4256G6V
External Chip Select
The CPLD also provides eight External Chip Se-
lect (ECS0-ECS7) outputs that can be used to se-
lect external devices. Each External Chip Select
(ECS0-ECS7) consists of one product term that
can be configured active High or Low.
The output enable of the pin is controlled by either
the output enable product term or the Direction
Register. (See Figure 17.)
Figure 17. External Chip Select Signal
Figure 18. Handshaking Communication Using Input Macrocells
47/100
PSD4256G6V
MCU BUS INTERFACE
The “no-glue logic” MCU Bus Interface block can
be directly connected to most popular 8-bit and 16-
bit MCUs and their control signals. Key MCUs,
with their bus types and control signals, are shown
in Table 34. The MCU interface type is specified
using the PSDsoft.
Table 34. 16-bit MCUs and Their Control Signals
Note:1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PD3-PD0, PF3-PF0) can be configured for other I/O func-
tions. ALE/AS input is optional for MCUs with a non-multiplexed bus. This configuration is for MC68HC812A4_EC at 5MHz, 3V only.
PSD4256G6V
PSD Interface to a Multiplexed Bus
Figure 19 shows an example of a system using an
MCU with a multiplexed bus and a PSD4256G6V.
The ADIO port on the PSD is connected directly to
the MCU address/data bus. Address Strobe (ALE/
AS, PD0) latches the address signals internally.
Latched addresses can be brought out to Port E, F
or G. The PSD drives the ADIO data bus only
when one of its internal resources is accessed and
READ Strobe (RD, CNTL1) is active. Should the
system address bus exceed sixteen bits, Ports A,
B, C, or F may be used as additional address in-
puts.
Figure 19. An Example of a Typical Multiplexed Bus Interface
Note:1. AD[15:8] is for 16-bit MCU
49/100
PSD4256G6V
PSD Interface to a Non-Multiplexed, 16-bit Bus
Figure 20 shows an example of a system using an
MCU with a 16-bit, non-multiplexed bus and a
PSD4256G6V. The address bus is connected to
the ADIO Port, and the data bus is connected to
Ports F and G. Ports F and G are in tri-state mode
when the PSD is not accessed by the MCU.
Should the system address bus exceed sixteen
bit, Ports A, B, or C may be used for additional ad-
dress inputs.
Figure 20. An Example of a Typical Non-Multiplexed Bus Interface
Note:1. D[15:8] is for 16-bit MCU
PSD4256G6V
Data Byte Enable Reference for a 16-bit Bus
MCUs have different data byte orientations. Table
35 to Table 38 show how the PSD4256G6V inter-
prets byte/word operations in different bus WRITE
configurations. Even-byte refers to locations with
address A0 equal to 0, and odd byte as locations
with A0 equal to 1.
Table 35. 16-Bit Data Bus with BHE
16-bit MCU Bus Interface Examples
Figure 21, page 51 to Figure 26, page 57 show ex-
amples of the basic connections between the
PSD4256G6V and some popular MCUs. The
PSD4256G6V Control input pins are labeled as to
the MCU function for which they are configured.
The MCU bus interface is specified using PSDsoft.
The Voltage Standby (VSTBY, PE6) line should be
held at Ground if not in use.
Table 36. 16-Bit Data Bus with WRH and WRL
Table 37. 16-Bit Data Bus with SIZ0, A0
(Motorola MCU)
Table 38. 16-Bit Data Bus with LDS, UDS
(Motorola MCU)
