PSD4235G2V-90U ,FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (3.3V SUPPLY)TABLE OF CONTENTSSummary Description . . . . . . 5In-System Programming (ISP) via JTAG . ..
PSD4235G2V-90U ,FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (3.3V SUPPLY)Absolute Maximum Ratings .68Table. Operating Conditions . . . . . . 69Table. DC Charact ..
PSD4235G2V-90U ,FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (3.3V SUPPLY)applications that includes configurable■ High Endurance:memories, PLD logic and I/O:– 100,000 Erase ..
PSD4256G6V ,FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUSBlock Diagram (Figure 4.) . . . . 15PSD ARCHITECTURAL OVERVIEW . . 16Memory . . ..
PSD501B1-C-70J ,Low Cost Field Programmable Microcontroller PeripheralsFEATURES SUMMARY
PSD4235G2V-90U
FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (3.3V SUPPLY)
1/89
PRELIMINARY DATADecember 2001
PSD4235G2VFlash In-System Programmable (ISP) Peripherals
For 16-bit MCUs (3.3V Supply)
FEATURES SUMMARYPSD provides an integrated solution to 16-bit MCU
based applications that includes configurable
memories, PLD logic and I/O: Dual Bank Flash Memories 4 Mbit of Primary Flash Memory (8 uniform
sectors, 32K x 16) 256 Kbit Secondary Flash Memory with 4
sectors Concurrent operation: read from one memory
while erasing and writing the other 64 Kbit SRAM (Battery Backed) PLD with macrocells Over 3000 Gates of PLD: CPLD and DPLD CPLD with 16 Output Macrocells (OMCs) and
24 Input Macrocells (IMCs) DPLD – user defined internal chip select de-
coding Seven l/O Ports with 52 I/O pins 52 individually configurable I/O port pins that
can be used for the following functions: MCU I/Os
–PLD I/Os Latched MCU address output Special function l/Os l/O ports may be configured as open-drain
outputs In-System Programming (ISP) with JTAG Built-in JTAG compliant serial port allows full-
chip In-System Programmability Efficient manufacturing allow easy product
testing and programming Use low cost FlashLINK cable with PC Page Register Internal page register that can be used to ex-
pand the microcontroller address space by a
factor of 256 Programmable power management High Endurance: 100,000 Erase/Write Cycles of Flash Memory 1,000 EraseWrite Cycles of PLD 15 Year Data Retention Single Supply Voltage 3.3V ±10% Memory Speed 90ns Flash memory and SRAM access time
Figure 1. Packages
PSD4235G2V
TABLE OF CONTENTS
Summary Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5In-System Programming (ISP) via JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
In-Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PSDsoft Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
PSD Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
MCU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
ISP via JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
In-System Programming (ISP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
In-Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Development System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PSD Register Description and Address Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Detailed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Reading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Erasing Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Memory Select Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
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PSD4235G2VMemory ID Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Decode PLD (DPLD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Ports A, B and C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Port D – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Port E – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Port F – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Port G – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59PLD Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Power On Reset, Warm Reset and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Programming In-Circuit using the JTAG Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
AC/DC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65Table. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Table. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table. CPLD Combinatorial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table. CPLD Macrocell Synchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table. CPLD Macrocell Asynchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table. Input Macrocell Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Table. Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Table. Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Table. Port F Peripheral Data Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Table. Port F Peripheral Data Mode Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table. Reset (Reset) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table. VSTBYON Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table. Program, Write and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table. ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Table. Power-down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
PSD4235G2V
Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85Table. TQFP80 - 80 lead Plastic Quad Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table. Pin Assignments – TQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
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PSD4235G2V
SUMMARY DESCRIPTIONThe PSD family of memory systems for microcon-
trollers (MCUs) brings In-System-Programmability
(ISP) to Flash memory and programmable logic.
The result is a simple and flexible solution for em-
bedded designs. PSD devices combine many of
the peripheral functions found in MCU based ap-
plications.
PSD devices integrate an optimized Macrocell log-
ic architecture. The Macrocell was created to ad-
dress the unique requirements of embedded
system designs. It allows direct connection be-
tween the system address/data bus, and the inter-
nal PSD registers, to simplify communication
between the MCU and other supporting devices.
Table 1. Pin NamesThe PSD family offers two methods to program the
PSD Flash memory while the PSD is soldered to
the circuit board: In-System Programming (ISP)
via JTAG, and In-Application Programming (IAP).
In-System Programming (ISP) via JTAGAn IEEE 1149.1 compliant JTAG In-System Pro-
gramming (ISP) interface is included on the PSD
enabling the entire device (Flash memories, PLD,
configuration) to be rapidly programmed while sol-
dered to the circuit board. This requires no MCU
participation, which means the PSD can be pro-
grammed anytime, even when completely blank.
The innovative JTAG interface to Flash memories
is an industry first, solving key problems faced by
designers and manufacturing houses, such as:
Figure 2. Logic Diagram
First time programming. How do I get firmware
into the Flash memory the very first time JTAG is
the answer. Program the blank PSD with no MCU
involvement.
Inventory build-up of pre-programmed devic-
es. How do I maintain an accurate count of pre-
programmed Flash memory and PLD devices
based on customer demand How many and what
version JTAG is the answer. Build your hardware
with blank PSDs soldered directly to the board and
then custom program just before they are shipped
to the customer. No more labels on chips, and no
more wasted inventory.
Expensive sockets. How do I eliminate the need
for expensive and unreliable sockets JTAG is the
answer. Solder the PSD directly to the circuit
board. Program first time and subsequent times
with JTAG. No need to handle devices and bend
the fragile leads.
PSD4235G2V
In-Application Programming (IAP)Two independent Flash memory arrays are includ-
ed so that the MCU can execute code from one
while erasing and programming the other. Robust
product firmware updates in the filed are possible
over any communication channel (CAN, Ethernet,
UART, J1850, etc) using this unique architecture.
Designers are relieved of these problems:
Simultaneous read and write to Flash memo-
ry. How can the MCU program the same memory
from which it executing code It cannot. The PSD
allows the MCU to operate the two Flash memory
blocks concurrently, reading code from one while
erasing and programming the other during IAP.
Complex memory mapping. How can I map
these two memories efficiently A programmable
Decode PLD (DPLD) is embedded in the PSD.
The concurrent PSD memories can be mapped
anywhere in MCU address space, segment by
segment with extermely high address resolution.
As an option, the secondary Flash memory can be
swapped out of the system memory map when
IAP is complete. A built-in page register breaks the
MCU address limit.
Separate Program and Data space. How can I
write to Flash memory while it resides in Program
space during field firmware updates My
80C51XA will not allow it. The PSD provides
means to reclassify Flash memory as Data space
during IAP, then back to Program space when
complete.
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PSD4235G2V
PSDsoft ExpressPSDsoft Express, a software development tool
from ST, guides you through the design process
step-by-step making it possible to complete an
embedded MCU design capable of ISP/IAP in just
hours. Select your MCU and PSDsoft Express
takes you through the remainder of the design with
point and click entry, covering PSD selection, pin
definitions, programmable logic inputs and outpus,
MCU memory map definition, ANSI-C code gener-
ation for your MCU, and merging your MCU firm-
ware with the PSD design. When complete, two
different device programmers are supported di-
rectly from PSDsoft Express: FlashLINK (JTAG)
and PSDpro.
Figure 4. PSD Block DiagramNote: Additional address lines can be brought in to the device via Port A, B, C, D or F.
PSD4235G2V
PSD ARCHITECTURAL OVERVIEWPSD devices contain several major functional
blocks. Figure 4 shows the architecture of the PSD
device family. The functions of each block are de-
scribed briefly in the following sections. Many of
the blocks perform multiple functions and are user
configurable.
MemoryEach of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discus-
sion can be found in the section entitled “Memory
Blocks“ on page 20.
The 4 Mbit primary Flash memory is the main
memory of the PSD. It is divided into 8 equally-
sized sectors that are individually selectable.
The 256 Kbit secondary Flash memory is divided
into 4 equally-sized sectors. Each sector is individ-
ually selectable.
The 64 Kbit SRAM is intended for use as a
scratch-pad memory or as an extension to the
MCU SRAM. If an external battery is connected to
the PSD’s Voltage Stand-by (VSTBY, PE6) signal,
data is retained in the event of power failure.
Each memory block can be located in a different
address space as defined by the user. The access
times for all memory types includes the address
latching and DPLD decoding time.
PLDsThe device contains two PLD blocks, the Decode
PLD (DPLD) and the Complex PLD (CPLD), as
shown in Table 2, each optimized for a different
function. The functional partitioning of the PLDs
reduces power consumption, optimizes cost/per-
formance, and eases design entry.
The DPLD is used to decode addresses and to
generate Sector Select signals for the PSD inter-
nal memory and registers. The DPLD has combi-
natorial outputs, while the CPLD can implement
more general user-defined logic functions. The
CPLD has 16 Output Macrocells (OMC) and 8
combinatorial outputs. The PSD also has 24 Input
Macrocells (IMC) that can be configured as inputs
to the PLDs. The PLDs receive their inputs from
the PLD Input Bus and are differentiated by their
output destinations, number of product terms, and
Macrocells.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo bit in PMMR0 and other bits in
PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD propaga-
tion time when not in the Turbo mode.
I/O PortsThe PSD has 52 I/O pins divided among seven
ports (Port A, B, C, D, E, F and G). Each I/O pin
can be individually configured for different func-
tions. Ports can be configured as standard MCU I/
O ports, PLD I/O, or latched address outputs for
MCUs using multiplexed address/data buses
The JTAG pins can be enabled on Port E for In-
System Programming (ISP).
Table 2. PLD I/O
MCU Bus InterfaceThe PSD easily interfaces easily with most 16-bit
MCUs, either with multiplexed or non-multiplexed
address/data buses. The device is configured to
respond to the MCU’s control pins, which are also
used as inputs to the PLDs.
ISP via JTAG PortIn-System Programming (ISP) can be performed
through the JTAG signals on Port E. This serial in-
terface allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port E. Table 3 indicates the
JTAG pin assignments.
In-System Programming (ISP)Using the JTAG signals on Port E, the entire PSD
device (memory, logic, configuration) can be pro-
grammed or erased without the use of the MCU.
Table 3. JTAG SIgnals on Port E
In-Application Programming (IAP)The primary Flash memory can also be pro-
grammed, or re-programmed, in-system by the
MCU executing the programming algorithms out of
the secondary Flash memory, or SRAM. The sec-
ondary Flash memory can be programmed the
same way by executing out of the primary Flash
memory. Table 4 indicates which programming
methods can program different functional blocks
of the PSD.
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PSD4235G2V
Page RegisterThe 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or in-
ternal memory and I/O. The Page Register can
also be used to change the address mapping of
the Flash memory blocks into different memory
spaces for IAP.
Power Management Unit (PMU)The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The Turbo bit in PMMR0 can be
reset to 0 and the CPLD latches its outputs and
goes to Stand-by mode until the next transition on
its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. See the section enti-
tled “Power Management” on page 59 for more de-
tails.
Table 4. Methods of Programming Different Functional Blocks of the PSD
PSD4235G2V
DEVELOPMENT SYSTEMThe PSD family is supported by PSDsoft Express,
a Windows-based software development tool
(Windows-95, Windows-98, Windows-2000, Win-
dows-NT). A PSD design is quickly and easily pro-
duced in a point and click environment. The
designer does not need to enter Hardware De-
scription Language (HDL) equations, unless de-
sired, to define PSD pin functions and memory
map information. The general design flow is
shown in Figure 5. PSDsoft Express is available
from our web site (the address is given on the back
page of this data sheet) or other distribution chan-
nels.
PSDsoft Express directly supports two low cost
device programmers form ST: PSDpro and
FlashLINK (JTAG). Both of these programmers
may be purchased through your local distributor/
representative, or directly from our web site using
a credit card. The PSD is also supported by thid
party device programmers. See our web site for
the current list.
11/89
PSD4235G2V
PIN DESCRIPTIONTable 5 describes the signal names and signal
functions of the PSD. Those that have multiple
names or functions are defined using PSDsoft Ex-
press.
Table 5. Pin Description (for the TQFP package)
PSD4235G2V
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PSD4235G2V
PSD4235G2V
PSD REGISTER DESCRIPTION AND ADDRESS OFFSETSTable 6 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al-
located by the user to the internal PSD registers.
Table 6 provides brief descriptions of the registers
in CSIOP space. The following sections give a
more detailed description.
Table 6. Register Address OffsetNote:1. Other registers that are not part of the I/O ports.
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REGISTER BIT DEFINITIONAll the registers of the PSD are included here, for
reference. Detailed descriptions of these registers
can be found in the following sections.
Table 7. Data-In Registers – Ports A, B, C, D, E, F, GNote: Bit Definitions (Read-only registers):
Read Port pin status when Port is in MCU I/O input mode.
Table 8. Data-Out Registers – Ports A, B, C, D, E, F, GNote: Bit Definitions:
Latched data for output to Port pin when pin is configured in MCU I/O output mode.
Table 9. Direction Registers – Ports A, B, C, D, E, F, GNote: Bit Definitions:
Port pin 0 = Port pin is configured in Input mode (default).
Port pin 1 = Port pin is configured in Output mode.
Table 10. Control Registers – Ports E, F, GNote: Bit Definitions:
Port pin 0 = Port pin is configured in MCU I/O mode (default).
Port pin 1 = Port pin is configured in Latched Address Out mode.
Table 11. Drive Registers – Ports A, B, D, E, GNote: Bit Definitions:
Port pin 0 = Port pin is configured for CMOS Output driver (default).
Port pin 1 = Port pin is configured for Open Drain output driver.
Table 12. Drive Registers – Ports C, FNote: Bit Definitions:
Port pin 0 = Port pin is configured for CMOS Output driver (default).
Port pin
1 = Port pin is configured in Slew Rate mode.
PSD4235G2V
Table 13. Enable-Out Registers – Ports A, B, C, F
Note: Bit Definitions (Read-only registers):
Port pin 0 = Port pin is in tri-state driver (default).
Port pin 1 = Port pin is enabled.
Table 14. Input Macrocells – Ports A, B, C
Note: Bit Definitions (Read-only registers):
Read Input Macrocell (IMC7-IMC0) status on Ports A, B and C.
Table 15. Output Macrocells A Register
Note: Bit Definitions:
Write Register: Load MCellA7-MCellA0 with 0 or 1.
Read Register: Read MCellA7-MCellA0 output status.
Table 16. Output Macrocells B Register
Note: Bit Definitions:
Write Register: Load MCellB7-MCellB0 with 0 or 1.
Read Register: Read MCellB7-MCellB0 output status.
Table 17. Mask Macrocells A Register
Note: Bit Definitions:
McellA_Prot 0 = Allow MCellA flip-flop to be loaded by MCU (default).
McellA_Prot 1 = Prevent MCellA flip-flop from being loaded by MCU.
Table 18. Mask Macrocells B Register
Note: Bit Definitions:
McellB_Prot 0 = Allow MCellB flip-flop to be loaded by MCU (default).
McellB_Prot 1 = Prevent MCellB flip-flop from being loaded by MCU.
Table 19. Flash Memory Protection Register
Note: Bit Definitions (Read-only register):
Sec_Prot 1 = Primary Flash memory Sector is write protected.
Sec_Prot 0 = Primary Flash memory Sector is not write protected.
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Table 20. Flash Boot Protection Register
Note: Bit Definitions:
Sec_Prot 1 = Secondary Flash memory Sector is write protected.
Sec_Prot 0 = Secondary Flash memory Sector is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
Security_Bit 1 = Security Bit in device has been set.
Table 21. JTAG Enable Register
Note: Bit Definitions:
JTAGEnable 1 = JTAG Port is enabled.
JTAGEnable 0 = JTAG Port is disabled.
Table 22. Page Register
Note: Bit Definitions:
Configure Page input to PLD. Default is PGR7-PGR0=0.
PSD4235G2V
Table 23. PMMR0 Register
Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not clear the registers.
Note: Bit Definitions:
APD Enable 0 = Automatic Power-down (APD) is disabled.
1 = Automatic Power-down (APD) is enabled.
PLD Turbo 0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
PLD Array CLK 0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off.
1 = CLKIN to the PLD AND array is disconnected, saving power.
PLD MCells CLK 0 = CLKIN to the PLD Macrocells is connected.
1 = CLKIN to the PLD Macrocells is disconnected, saving power.
Table 24. PMMR2 Register
Note: For Bit 4, Bit 3, Bit 2: See Table 34 for the signals that are blocked on pins CNTL0-CNTL2.
Note: Bit Definitions:
PLD Array Addr 0 = Address A7-A0 are connected to the PLD array.
1 = Address A7-A0 are blocked from the PLD array, saving power.
(Note: in XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4)
PLD Array CNTL20 = CNTL2 input to the PLD AND array is connected.
1 = CNTL2 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL10 = CNTL1 input to the PLD AND array is connected.
1 = CNTL1 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL00 = CNTL0 input to the PLD AND array is connected.
1 = CNTL0 input to the PLD AND array is disconnected, saving power.
PLD Array ALE 0 = ALE input to the PLD AND array is connected.
1 = ALE input to the PLD AND array is disconnected, saving power.
PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected.
1 = WRH/DBE input to the PLD AND array is disconnected, saving power.
Table 25. VM Register
Note: On reset, Bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft Express. Bit0 and Bit7 are always cleared on
reset. Bit0-Bit4 are active only when the device is configured in Philips 80C51XA mode.
Note: Bit Definitions:
SR_code 0 = PSEN cannot access SRAM in 80C51XA modes.
1 = PSEN can access SRAM in 80C51XA modes.
Boot_code 0 = PSEN cannot access Secondary NVM in 80C51XA modes.
1 = PSEN can access Secondary NVM in 80C51XA modes.
FL_code 0 = PSEN cannot access Primary Flash memory in 80C51XA modes.
1 = PSEN can access Primary Flash memory in 80C51XA modes.
Boot_data 0 = RD cannot access Secondary NVM in 80C51XA modes.
1 = RD can access Secondary NVM in 80C51XA modes.
FL_data 0 = RD cannot access Primary Flash memory in 80C51XA modes.
1 = RD can access Primary Flash memory in 80C51XA modes.
Peripheral mode 0 = Peripheral mode of Port F is disabled.
1 = Peripheral mode of Port F is enabled.
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Table 26. Memory_ID0 Register
Note: Bit Definitions:
F_size[3:0] 0h = There is no Primary Flash memory
1h = Primary Flash memory size is 256 Kbit
2h = Primary Flash memory size is 512 Kbit
3h = Primary Flash memory size is 1 Mbit
4h = Primary Flash memory size is 2 Mbit
5h = Primary Flash memory size is 4 Mbit
6h = Primary Flash memory size is 8 Mbit
S_size[3:0] 0h = There is no SRAM
1h = SRAM size is 16 Kbit
2h = SRAM size is 32 Kbit
3h = SRAM size is 64 Kbit
4h = SRAM size is 128 Kbit
5h = SRAM size is 256 Kbit
Table 27. Memory_ID1 Register
Note: Bit Definitions:
B_size[3:0] 0h = There is no Secondary NVM
1h = Secondary NVM size is 128 Kbit
2h = Secondary NVM size is 256 Kbit
3h = Secondary NVM size is 512 Kbit
B_type[1:0] 0h = Secondary NVM is Flash memory
1h = Secondary NVM is EEPROM
PSD4235G2V
DETAILED OPERATION
As shown in Figure 4, the PSD consists of six ma-
jor types of functional blocks: Memory Blocks PLD Blocks MCU Bus Interface I/O Ports Power Management Unit (PMU) JTAG-ISP Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
Memory Blocks
The PSD has the following memory blocks: Primary Flash memory Secondary Flash memory
–SRAM
The Memory Select signals for these blocks origi-
nate from the Decode PLD (DPLD) and are user-
defined in PSDsoft Express.
Table 28 sumamarizes the sizes and organisa-
tions of the memory blocks.
Table 28. Memory Block Size and Organization
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Primary Flash Memory and Secondary Flash
memory Description. The primary Flash memo-
ry is divided evenly into 8 sectors. The secondary
Flash memory is divided evenly into 4 sectors.
Each sector of either memory block can be sepa-
rately protected from Program and Erase cycles.
Flash memory may be erased on a sector-by-sec-
tor basis, and programmed word-by-word. Flash
sector erasure may be suspended while data is
read from other sectors of the block and then re-
sumed after reading.
During a Program or Erase cycle in Flash memory,
the status can be output on the Ready/Busy pin
(PE4). This pin is set up using PSDsoft Express.
Memory Block Select Signals. The DPLD gen-
erates the Select signals for all the internal memo-
ry blocks (see the section entitled “PLDs”, on page
31). Each of the sectors of the primary Flash mem-
ory has a Select signal (FS0-FS7) which can con-
tain up to three product terms. Each of the sectors
of the secondary Flash memory has a Select sig-
nal (CSBOOT0-CSBOOT3) which can contain up
to three product terms. Having three product terms
for each Select signal allows a given sector to be
mapped in different areas of system memory.
When using a MCU with separate Program and
Data space (80C51XA), these flexible Select sig-
nals allow dynamic re-mapping of sectors from
one memory space to the other before and after
IAP. The SRAM block has a single Select signal
(RS0).
Ready/Busy (PE4). This signal can be used to
output the Ready/Busy status of the PSD. The out-
put is a 0 (Busy) when a Flash memory block is be-
ing written to, or when a Flash memory block is
being erased. The output is a 1 (Ready) when no
Write or Erase cycle is in progress.
Memory Operation. The primary Flash memory
and secondary Flash memory are addressed
through the MCU Bus Interface. The MCU can ac-
cess these memories in one of two ways: The MCU can execute a typical bus Write or
Read operation just as it would if accessing a
RAM or ROM device using standard bus cycles. The MCU can execute a specific instruction that
consists of several Write and Read operations.
This involves writing specific data patterns to
special addresses within the Flash memory to
invoke an embedded algorithm. These
instructions are summarized in Table 29.
Typically, the MCU can read Flash memory using
Read operations, just as it would read a ROM de-
vice. However, Flash memory can only be erased
and programmed using specific instructions. For
example, the MCU cannot write a single byte di-
rectly to Flash memory as one would write a byte
to RAM. To program a word into Flash memory,
the MCU must execute a Program instruction, then
test the status of the Programming event. This sta-
tus test is achieved by a Read operation or polling
Ready/Busy (PE4).
Flash memory can also be read by using special
instructions to retrieve particular Flash device in-
formation (sector protect status and ID).
PSD4235G2V
Table 29. Instructions
Note:1. All bus cycles are write bus cycles, except the ones with the “Read” label All values are in hexadecimal:
X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses
RA = Address of the memory location to be read
RD = Data read from location RA during the Read cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0).
PA is an even address for PSD in word programming mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be
erased, or verified, must be Active (High). Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft Express. Only address bits A11-A0 are used in instruction decoding. No Unlock or instruction cycles are required when the device is in the Read mode The Reset instruction is required to return to the Read mode after reading the Flash ID, or after reading the Sector Protection Status,
or if the Error Flag (DQ5/DQ13) bit goes High. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80 μs. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1,A0)=(1,0) The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass
mode.
11. The system may perform Read and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is
intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status
of the primary Flash memory.
14. All write bus cycles in an instruction are byte write to an even address (XA4Ah or X554h). A Flash memory Program bus cycle writes
a word to an even address.
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PSD4235G2V
Instructions
An instruction consists of a sequence of specific
operations. Each received byte is sequentially de-
coded by the PSD and not executed as a standard
Write operation. The instruction is executed when
the correct number of bytes are properly received
and the time between two consecutive bytes is
shorter than the time-out period. Some instruc-
tions are structured to include Read operations af-
ter the initial Write operations.
The instruction must be followed exactly. Any in-
valid combination of instruction bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into Read
mode (Flash memory is read like a ROM device).
The PSD supports the instructions summarized in
Table 29: Erase memory by chip or sector Suspend or resume sector erase Program a Word Reset to Read mode Read primary Flash Identifier value Read Sector Protection Status Bypass
These instructions are detailed in Table 29. For ef-
ficient decoding of the instructions, the first two
bytes of an instruction are the coded cycles and
are followed by an instruction byte or confirmation
byte. The coded cycles consist of writing the data
AAh to address XAAAh during the first cycle and
data 55h to address X554h during the second cy-
cle (unless the Bypass instruction feature is used,
as described later). Address signals A15-A12 are
Don’t Care during the instruction Write cycles.
However, the appropriate Sector Select signal
(FS0-FS7, or CSBOOT0-CSBOOT3) must be se-
lected.
The primary and secondary Flash memories have
the same instruction set (except for Read Primary
Flash Identifier). The Sector Select signals deter-
mine which Flash memory is to receive and exe-
cute the instruction. The primary Flash memory is
selected if any one of its Sector Select signals
(FS0-FS7) is High, and the secondary Flash mem-
ory is selected if any one of its Sector Select sig-
nals (CSBOOT0-CSBOOT3) is High.
Power-up Condition. The PSD internal logic is
reset upon Power-up to the Read mode. Sector
Select (FS0-FS7 and CSBOOT0-CSBOOT3)
must be held Low, and Write Strobe (WR/WRL,
CNTL0) High, during Power-up for maximum se-
curity of the data contents and to remove the pos-
sibility of data being written on the first edge of
Write Strobe (WR/WRL, CNTL0). Any Write cycle
initiation is locked when VCC is below VLKO.
Reading Flash Memory
Under typical conditions, the MCU may read the
primary Flash memory, or secondary Flash mem-
ory, using Read operations just as it would a ROM
or RAM device. Alternately, the MCU may use
Read operations to obtain status information
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these memory blocks. The
following sections describe these Read functions.
Read Memory Contents. Primary Flash memory
and secondary Flash memory are placed in the
Read mode after Power-up, chip reset, or a Reset
Flash instruction (see Table 29). The MCU can
read the memory contents of the primary Flash
memory, or the secondary Flash memory by using
Read operations any time the Read operation is
not part of an instruction.
Read Primary Flash Identifier. The primary
Flash memory identifier is read with an instruction
composed of 4 operations: 3 specific Write opera-
tions and a Read operation (see Table 29). The
identifier for the primary Flash memory is E8h. The
secondary Flash memory does not support this in-
struction.
Read Memory Sector Protection Status. The
Flash memory Sector Protection Status is read
with an instruction composed of four operations:
three specific Write operations and a Read opera-
tion (see Table 29). The Read operation produces
01h if the Flash memory sector is protected, or 00h
if the sector is not protected.
The sector protection status for all NVM blocks
(primary Flash memory, or secondary Flash mem-
ory) can be read by the MCU accessing the Flash
Protection and Flash Boot Protection registers in
PSD I/O space. See the section entitled “Flash
Memory Sector Protect”, on page 27, for register
definitions.
Reading the Erase/Program Status Bits. The
PSD provides several status bits to be used by the
MCU to confirm the completion of an Erase or Pro-
gram cycle of Flash memory. These status bits
minimize the time that the MCU spends perform-
ing these tasks and are defined in Table 30. The
status byte resides in an even location, and can be
read as many times as needed. Also note that
DQ15-DQ8 is an even byte for Motorola MCUs
with a 16-bit data bus.
For Flash memory, the MCU can perform a Read
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algorithm. See the section entitled
“Programming Flash Memory”, on page 25, for de-
tails.
PSD4235G2V
Table 30. Status Bits
Table 31. Status Bits for Motorola
Note:1. X = Not guaranteed value, can be read either 1 or 0. DQ15-DQ0 represent the Data Bus bits, D15-D0. FS0-FS7/CSBOOT0-CSBOOT3 are active High.
Data Polling (DQ7) – DQ15 for Motorola.
When erasing or programming in Flash memory,
the Data Polling (DQ7/DQ15) bit outputs the com-
plement of the bit being entered for programming/
writing on the DQ7/DQ15 bit. Once the Program
instruction or the Write operation is completed, the
true logic value is read on the Data Polling (DQ7/
DQ15) bit (in a Read operation). Data Polling is effective after the fourth Write
pulse (for a Program instruction) or after the
sixth Write pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memory sector being erased. During an Erase cycle, the Data Polling (DQ7/
DQ15) bit outputs a 0. After completion of the
cycle, the Data Polling (DQ7/DQ15) bit outputs
the last bit programmed (it is a 1 after erasing). If the location to be programmed is in a
protected Flash memory sector, the instruction
is ignored. If all the Flash memory sectors to be erased are
protected, the Data Polling (DQ7/DQ15) bit is
reset to 0 for about 100 μs, and then returns to
the value from the previously addressed
location. No erasure is performed.
Toggle Flag (DQ6) – DQ14 for Motorola. The
PSD offers another way for determining when the
Flash memory Program cycle is completed. During
the internal Write operation and when either FS0-
FS7 or CSBOOT0-CSBOOT3 is true, the Toggle
Flag (DQ6/DQ14) bit toggles from 0 to 1 and 1 to
0 on subsequent attempts to read any word of the
memory.
When the internal cycle is complete, the toggling
stops and the data read on the Data Bus D0-D7 is
the value from the addressed memory location.
The device is now accessible for a new Read or
Write operation. The cycle is finished when two
successive Reads yield the same output data. The Toggle Flag (DQ6/DQ14) bit is effective
after the fourth Write pulse (for a Program
instruction) or after the sixth Write pulse (for an
Erase instruction). If the location to be programmed belongs to a
protected Flash memory sector, the instruction
is ignored. If all the Flash memory sectors selected for
erasure are protected, the Toggle Flag (DQ6/
DQ14) bit toggles to 0 for about 100 μs and then
returns to the value from the previously
addressed location.
Error Flag (DQ5) – DQ13 for Motorola. During
a normal Program or Erase cycle, the Error Flag
(DQ5/DQ13) bit is reset to 0. This bit is set to 1
when there is a failure during a Flash memory Pro-
gram, Sector Erase, or Bulk Erase cycle.
In the case of Flash memory programming, the Er-
ror Flag (DQ5/DQ13) bit indicates the attempt to
program a Flash memory bit, or bits, from the pro-
grammed state, 0, to the erased state, 1, which is
not a valid operation. The Error Flag (DQ5/DQ13)
bit may also indicate a Time-out condition while at-
tempting to program a word.
In case of an error in a Flash memory Sector Erase
or Word Program cycle, the Flash memory sector
in which the error occurred or to which the pro-
grammed location belongs must no longer be
used. Other Flash memory sectors may still be
used. The Error Flag (DQ5/DQ13) bit is reset after
a Reset instruction. A Reset instruction is required
after detecting an error on the Error Flag (DQ5/
DQ13) bit.
Erase Time-out Flag (DQ3) – DQ11 for Motoro-
la. The Erase Time-out Flag (DQ3/DQ11) bit re-
flects the time-out period allowed between two
consecutive Sector Erase instructions. The Erase
Time-out Flag (DQ3/DQ11) bit is reset to 0 after a
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PSD4235G2V
Sector Erase cycle for a period of 100 μs + 20%
unless an additional Sector Erase instruction is de-
coded. After this period, or when the additional
Sector Erase instruction is decoded, the Erase
Time-out Flag (DQ3/DQ11) bit is set to 1.
Programming Flash Memory
Flash memory must be erased prior to being pro-
grammed. The MCU may erase Flash memory all
at once or by-sector. Although erasing Flash mem-
ory occurs on a sector or device basis, program-
ming Flash memory occurs on a word basis.
The primary and secondary Flash memories re-
quire the MCU to send an instruction to program a
word or to erase sectors (see Table 29).
Once the MCU issues a Flash memory Program or
Erase instruction, it must check the status bits for
completion. The embedded algorithms that are in-
voked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or Ready/Busy (PE4) signal.
Data Polling. Polling on the Data Polling (DQ7/
DQ15) bit is a method of checking whether a Pro-
gram or Erase cycle is in progress or has complet-
ed. Figure 6 shows the Data Polling algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the word to be pro-
grammed in Flash memory to check the status.
The Data Polling (DQ7/DQ15) bit becomes the
complement of the corresponding bit of the original
data word to be programmed. The MCU continues
to poll this location, comparing data and monitor-
ing the Error Flag (DQ5/DQ13) bit. When the Data
Polling (DQ7/DQ15) bit matches the correspond-
ing bit of the original data, and the Error Flag
(DQ5/DQ13) bit remains 0, the embedded algo-
rithm is complete. If the Error Flag (DQ5/DQ13) bit
is 1, the MCU should test the Data Polling (DQ7/
DQ15) bit again since the Data Polling (DQ7/
DQ15) bit may have changed simultaneously with
the Error Flag (DQ5/DQ13) bit (see Figure 6).
The Error Flag (DQ5/DQ13) bit is set if either an in-
ternal time-out occurred while the embedded algo-
rithm attempted to program the location or if the
MCU attempted to program a 1 to a bit that was not
erased (not erased is logic 0).
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
word that was written to the Flash memory with the
word that was intended to be written.
When using the Data Polling method during an
Erase cycle, Figure 6 still applies. However, the
Data Polling (DQ7/DQ15) bit is 0 until the Erase
cycle is complete. A 1 on the Error Flag (DQ5/
DQ13) bit indicates a time-out condition on the
Erase cycle, a 0 indicates no error. The MCU can
read any even location within the sector being
erased to get the Data Polling (DQ7/DQ15) bit and
the Error Flag (DQ5/DQ13) bit.
PSDsoft Express generates ANSI C code func-
tions that implement these Data Polling algo-
rithms.
Figure 6. Data Polling Flowchart
Data Toggle. Checking the Toggle Flag (DQ6/
DQ14) bit is another method of determining wheth-
er a Program or Erase cycle is in progress or has
completed. Figure 7 shows the Data Toggle algo-
rithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location to be programmed in
Flash memory to check the status. The Toggle
Flag (DQ6/DQ14) bit toggles each time the MCU
PSD4235G2V
reads this location until the embedded algorithm is
complete. The MCU continues to read this loca-
tion, checking the Toggle Flag (DQ6/DQ14) bit
and monitoring the Error Flag (DQ5/DQ13) bit.
When the Toggle Flag (DQ6/DQ14) bit stops tog-
gling (two consecutive reads yield the same val-
ue), and the Error Flag (DQ5/DQ13) bit remains 0,
the embedded algorithm is complete. If the Error
Flag (DQ5/DQ13) bit is 1, the MCU should test the
Toggle Flag (DQ6/DQ14) bit again, since the Tog-
gle Flag (DQ6/DQ14) bit may have changed simul-
taneously with the Error Flag (DQ5/DQ13) bit (see
Figure 7).
Figure 7. Data Toggle Flowchart
The Error Flag (DQ5/DQ13) bit is set if either an in-
ternal time-out occurred while the embedded algo-
rithm attempted to program, or if the MCU
attempted to program a 1 to a bit that was not
erased (not erased is logic 0).
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
word that was written to Flash memory with the
word that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 7 still applies. the Toggle Flag
(DQ6/DQ14) bit toggles until the Erase cycle is
complete. A 1 on the Error Flag (DQ5/DQ13) bit in-
dicates a time-out condition on the Erase cycle, a
0 indicates no error. The MCU can read any even
location within the sector being erased to get the
Toggle Flag (DQ6/DQ14) bit and the Error Flag
(DQ5/DQ13) bit.
PSDsoft Express generates ANSI C code func-
tions which implement these Data Toggling algo-
rithms.
Unlock Bypass. The Unlock Bypass instruction
allows the system to program words to the Flash
memories faster than using the standard Program
instruction. The Unlock Bypass mode is entered
by first initiating two Unlock cycles. This is followed
by a third Write cycle containing the Unlock By-
pass command, 20h (as shown in Table 29). The
Flash memory then enters the Unlock Bypass
mode.
A two-cycle Unlock Bypass Program instruction is
all that is required to program in this mode. The
first cycle in this instruction contains the Unlock
Bypass Program command, A0h. The second cy-
cle contains the program address and data. Addi-
tional data is programmed in the same manner.
This mode dispense with the initial two Unlock cy-
cles required in the standard Program instruction,
resulting in faster total programming time.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset in-
structions are valid.
To exit the Unlock Bypass mode, the system must
issue the two-cycle Unlock Bypass Reset instruc-
tion. The first cycle must contain the data 90h; the
second cycle the data 00h. Addresses are Don’t
Care for both cycles. The Flash memory then re-
turns to Read mode.
Erasing Flash Memory
Flash Bulk Erase. The Flash Bulk Erase instruc-
tion uses six Write operations followed by a Read
operation of the status register, as described in
Table 29. If any byte of the Bulk Erase instruction
is wrong, the Bulk Erase instruction aborts and the
device is reset to the Read Memory mode.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag (DQ5/DQ13)
bit, the Toggle Flag (DQ6/DQ14) bit, and the Data
Polling (DQ7/DQ15) bit, as detailed in the section
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PSD4235G2V
entitled “Programming Flash Memory”, on page
25. The Error Flag (DQ5/DQ13) bit returns a 1 if
there has been an Erase Failure (maximum num-
ber of Erase cycles have been executed).
It is not necessary to program the memory with
00h because the PSD automatically does this be-
fore erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.
Flash Sector Erase. The Sector Erase instruc-
tion uses six Write operations, as described in Ta-
ble 29. Additional Flash Sector Erase confirm
commands and Flash memory sector addresses
can be written subsequently to erase other Flash
memory sectors in parallel, without further coded
cycles, if the additional commands are transmitted
in a shorter time than the time-out period of about
100 μs. The input of a new Sector Erase command
restarts the time-out period.
The status of the internal timer can be monitored
through the level of the Erase Time-out Flag (DQ3/
DQ11) bit. If the Erase Time-out Flag (DQ3/DQ11)
bit is 0, the Sector Erase instruction has been re-
ceived and the time-out period is counting. If the
Erase Time-out Flag (DQ3/DQ11) bit is 1, the
time-out period has expired and the PSD is busy
erasing the Flash memory sector(s). Before and
during Erase time-out, any instruction other than
Suspend Sector Erase and Resume Sector Erase,
abort the cycle that is currently in progress, and re-
set the device to Read mode. It is not necessary to
program the Flash memory sector with 00h as the
PSD does this automatically before erasing.
During a Sector Erase, the memory status may be
checked by reading the Error Flag (DQ5/DQ13)
bit, the Toggle Flag (DQ6/DQ14) bit, and the Data
Polling (DQ7/DQ15) bit, as detailed in the section
entitled “Programming Flash Memory”, on page
During execution of the Erase cycle, the Flash
memory accepts only Reset and Suspend Sector
Erase instructions. Erasure of one Flash memory
sector may be suspended, in order to read data
from another Flash memory sector, and then re-
sumed.
Suspend Sector Erase. When a Sector Erase
cycle is in progress, the Suspend Sector Erase in-
struction can be used to suspend the cycle by writ-
ing 0B0h to any even address when an
appropriate Sector Select (FS0-FS7 or
CSBOOT0-CSBOOT3) is High. (See Table 29).
This allows reading of data from another Flash
memory sector after the Erase cycle has been
suspended. Suspend Sector Erase is accepted
only during the Flash Sector Erase instruction ex-
ecution and defaults to Read mode. A Suspend
Sector Erase instruction executed during an Erase
time-out period, in addition to suspending the
Erase cycle, terminates the time out period.
The Toggle Flag (DQ6/DQ14) bit stops toggling
when the PSD internal logic is suspended. The
status of this bit must be monitored at an address
within the Flash memory sector being erased. The
Toggle Flag (DQ6/DQ14) bit stops toggling be-
tween 0.1 μs and 15 μs after the Suspend Sector
Erase instruction has been executed. The PSD is
then automatically set to Read mode.
If an Suspend Sector Erase instruction was exe-
cuted, the following rules apply: Attempting to read from a Flash memory sector
that was being erased outputs invalid data. Reading from a Flash memory sector that was
not being erased is valid. The Flash memory cannot be programmed, and
only responds to Resume Sector Erase and Re-
set instructions (Read is an operation and is al-
lowed).If a Reset instruction is received, data in the
Flash memory sector that was being erased is
invalid.
Resume Sector Erase. If a Suspend Sector
Erase instruction was previously executed, the
Erase cycle may be resumed with this instruction.
The Resume Sector Erase instruction consists of
writing 030h to any even address while an appro-
priate Sector Select (FS0-FS7 or CSBOOT0-
CSBOOT3) is High. (See Table 29.)
Flash Memory Sector Protect
Each sector of Primary or Secondary Flash mem-
ory can be separately protected against Program
and Erase cycles. Sector Protection provides ad-
ditional data security because it disables all Pro-
gram or Erase cycles. This mode can be activated
(or deactivated) through the JTAG-ISP Port or a
Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft Express program. This auto-
matically protects selected sectors when the de-
vice is programmed through the JTAG Port or a
Device Programmer. Flash memory sectors can
be unprotected to allow updating of their contents
using the JTAG Port or a Device Programmer. The
MCU can read (but cannot change) the sector pro-
tection bits.
Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a read of the protected data.
This allows a guarantee of the retention of the Pro-
tection status.
The sector protection status can be read by the
MCU through the Flash memory protection and
Secondary Flash memory protection registers (in
PSD4235G2V
the CSIOP block) or use the Read Sector Protec-
tion instruction. See Table 19 to Table 20.
Reset
The Reset instruction consists of one Write cycle
(see Table 29). It can also be optionally preceded
by the standard two write decoding cycles (writing
AAh to AAAh, and 55h to 554h).
The Reset instruction must be executed after: Reading the Flash Protection Status or Flash ID An Error condition has occurred (and the device
has set the Error Flag (DQ5/DQ13) bit to 1) dur-
ing a Flash memory Program or Erase cycle.
The Reset instruction immediately puts the Flash
memory back into normal Read mode. However, if
there is an error condition (with the Error Flag
(DQ5/DQ13) bit set to 1) the Flash memory will re-
turn to the Read mode in 25 μs after the Reset in-
struction is issued.
The Reset instruction is ignored when it is issued
during a Program or Bulk Erase cycle of the Flash
memory. The Reset instruction aborts any on-go-
ing Sector Erase cycle, and returns the Flash
memory to the normal Read mode in 25 μs.
Reset (RESET) Pin. A pulse on the Reset (RE-
SET) pin aborts any cycle that is in progress, and
resets the Flash memory to the Read mode. When
the reset occurs during a Program or Erase cycle,
the Flash memory takes up to 25 μs to return to
the Read mode. It is recommended that the Reset
(RESET) pulse (except for Power On Reset, as
described on page 62) be at least 25 μs so that the
Flash memory is always ready for the MCU to
fetch the bootstrap instructions after the Reset cy-
cle is complete.
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to three product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to the Voltage Stand-by (VSTBY, PE6) line. If you
have an external battery connected to the PSD,
the contents of the SRAM are retained in the event
of a power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at V or greater. If the supply voltage falls below the
battery voltage, an internal power switch-over to
the battery occurs.
PE7 can be configured as an output that indicates
when power is being drawn from the external bat-
tery. This Battery-on Indicator (VBATON, PE7)
signal is High when the supply voltage falls below
the battery voltage and the battery on Voltage
Stand-by (VSTBY, PE6) is supplying power to the
internal SRAM.
SRAM Select (RS0), Voltage Stand-by (VSTBY,
PE6) and Battery-on Indicator (VBATON, PE7)
are all configured using PSDsoft Express.
Memory Select Signals
The Primary Flash Memory Sector Select (FS0-
FS7), Secondary Flash Memory Sector Select
(CSBOOT0-CSBOOT3) and SRAM Select (RS0)
signals are all outputs of the DPLD. They are de-
fined using PSDsoft Express. The following rules
apply to the equations for these signals: Primary Flash memory and secondary Flash
memory Sector Select signals must not be larg-
er than the physical sector size. Any primary Flash memory sector must not be
mapped in the same memory space as another
Flash memory sector. A secondary Flash memory sector must not be
mapped in the same memory space as another
secondary Flash memory sector. SRAM, I/O, and Peripheral I/O spaces must not
overlap. A secondary Flash memory sector may overlap
a primary Flash memory sector. In case of over-
lap, priority is given to the secondary Flash
memory sector. SRAM, I/O, and Peripheral I/O spaces may
overlap any other memory sector. Priority is giv-
en to the SRAM, I/O, or Peripheral I/O.
Figure 8. Priority Level of Memory and I/O
Components
Example. FS0 is valid when the address is in the
range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to
87FFh. Any address in the range of RS0 always
accesses the SRAM. Any address in the range of
CSBOOT0 greater than 87FFh (and less than
9FFFh) automatically addresses secondary Flash
memory segment 0. Any address greater than
9FFFh accesses the primary Flash memory seg-
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PSD4235G2V
ment 0. You can see that half of the primary Flash
memory segment 0 and one-fourth of secondary
Flash memory segment 0 cannot be accessed in
this example. Also note that an equation that de-
fined FS1 to anywhere in the range of 8000h to
BFFFh would not be valid.
Figure 8 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not overlap. Level 1 has the highest priority and
level 3 has the lowest.
Memory Select Configuration for MCUs with
Separate Program and Data Spaces. The
80C51XA and compatible family of MCUs, can be
configured to have separate address spaces for
Program memory (selected using Program Select
Enable (PSEN, CNTL2)) and Data memory (se-
lected using Read Strobe (RD, CNTL1)). Any of
the memories within the PSD can reside in either
space or both spaces. This is controlled through
manipulation of the VM register that resides in the
CSIOP space.
The VM register is set using PSDsoft Express to
have an initial value. It can subsequently be
changed by the MCU so that memory mapping
can be changed on-the-fly.
For example, you may wish to have SRAM and pri-
mary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the secondary
Flash memory and primary Flash memory. This is
easily done with the VM register by using PSDsoft
Express to configure it for Boot-up and having the
MCU change it when desired.
Table 25 describes the VM Register.
Separate Space Modes. Program space is sep-
arated from Data space. For example, Program
Select Enable (PSEN, CNTL2) is used to access
the program code from the primary Flash memory,
while Read Strobe (RD, CNTL1) is used to access
data from the secondary Flash memory, SRAM
and I/O Port blocks. This configuration requires
the VM register to be set to 0Ch (see Figure 9).
Combined Space Modes. The Program and
Data spaces are combined into one memory
space that allows the primary Flash memory, sec-
ondary Flash memory, and SRAM to be accessed
by either Program Select Enable (PSEN, CNTL2)
or Read Strobe (RD, CNTL1). For example, to
configure the primary Flash memory in Combined
space, bits 2 and 4 of the VM register are set to 1
(see Figure 10).
80C51XA Memory Map Example. See the Ap-
plication Notes for examples.
PSD4235G2V
Page Register
The 8-bit Page Register increases the addressing
capability of the MCU by a factor of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0-
PGR7) are inputs to the DPLD decoder and can be
included in the Sector Select (FS0-FS7,
CSBOOT0-CSBOOT3), and SRAM Select (RS0)
equations.
If memory paging is not needed, or if not all eight
page register bits are needed for memory paging,
these bits may be used in the CPLD for general
logic. See Application Note AN1154.
Table 22 and Figure 11 show the Page Register.
The eight flip-flops in the register are connected to
the internal data bus (D0-D7). The MCU can write
to or read from the Page Register. The Page Reg-
ister can be accessed at address location CSIOP
+ E0h.
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PSD4235G2V
Memory ID Registers
The 8-bit read-only Memory Status Registers are
included in the CSIOP space. The user can deter-
mine the memory configuration of the PSD device
by reading the Memory ID0 and Memory ID1 reg-
isters. The content of the registers is defined as
shown in Table 26 and Table 27.
PLDs
The PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
using PSDsoft Express, the logic is programmed
into the device and available upon Power-up.
Table 32. DPLD and CPLD Inputs
Note:1. The address inputs are A19-A4 in 80C51XA mode.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in the following sections. Figure
12 shows the configuration of the PLDs.
The DPLD performs address decoding for internal
components, such as memory, registers, and I/O
ports Select signals.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0-
ECS2) signals.
The AND Array is used to form product terms.
These product terms are specified using PSDsoft
Express. An Input Bus consisting of 82 signals is
connected to the PLDs. The signals are shown in
Table 32.
The Turbo Bit in PSD. The PLDs in the
PSD4235G2V can minimize power consumption
by switching to standby when inputs remain un-
changed for an extended time of about 70 ns. Re-
setting the Turbo bit to 0 (Bit 3 of the PMMR0
register) automatically places the PLDs into stand-
by if no inputs are changing. Turning the Turbo
mode off increases propagation delays while re-
ducing power consumption. See the section enti-
tled “Power Management”, on page 59, on how to
set the Turbo bit.
Additionally, five bits are available in the PMMR2
register to block MCU control signals from entering
the PLDs. This reduces power consumption and
can be used only when these MCU control signals
are not used in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
PSD4235G2V
Figure 12. PLD Diagram
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PSD4235G2V
DECODE PLD (DPLD)
The DPLD, shown in Figure 13, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals: 8 Sector Select (FS0-FS7) signals for the
primary Flash memory (three product terms
each) 4 Sector Select (CSBOOT0-CSBOOT3) signals
for the secondary Flash memory (three product
terms each) 1 internal SRAM Select (RS0) signal (three
product terms) 1 internal CSIOP Select (PSD Configuration
Register) signal 1 JTAG Select signal (enables JTAG-ISP on
Port E) 2 internal Peripheral Select signals
(Peripheral I/O mode).
Figure 13. DPLD Logic Array
Note:1. The address inputs are A19-A4 when in 80C51XA mode Additional address lines can be brought ino the PSD via Port A, B, C, D, or F.
PSD4235G2V
COMPLEX PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate eight External Chip Se-
lect (ECS0-ECS7), routed to Port C or Port F.
Although External Chip Select (ECS0-ECS7) can
be produced by any Output Macrocell (OMC),
these eight External Chip Select (ECS0-ECS7) on
Port C or Port F do not consume any Output Mac-
rocells (OMC).
As shown in Figure 12, the CPLD has the following
blocks: 24 Input Macrocells (IMC) 16 Output Macrocells (OMC) Product Term Allocator AND Array capable of generating up to 196
product terms Four I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
35/89
PSD4235G2V
Output Macrocell (OMC). Eight of the Output
Macrocells (OMC) are connected to Ports A pins
and are named as McellA0-McellA7. The other
eight Macrocells are connected to Ports B pins
and are named as McellB0-McellB7.
The Output Macrocell (OMC) architecture is
shown in Figure 15. As shown in the figure, there
are native product terms available from the AND
Array, and borrowed product terms available (if
unused) from other Output Macrocells (OMC). The
polarity of the product term is controlled by the
XOR gate. The Output Macrocell (OMC) can im-
plement either sequential logic, using the flip-flop
element, or combinatorial logic. The multiplexer
selects between the sequential or combinatorial
logic outputs. The multiplexer output can drive a
port pin and has a feedback path to the AND Array
inputs.
The flip-flop in the Output Macrocell (OMC) block
can be configured as a D, T, JK, or SR type in the
PSDsoft Express program. The flip-flop’s clock,
preset, and clear inputs may be driven from a
product term of the AND Array. Alternatively, the
external CLKIN (PD1) signal can be used for the
clock input to the flip-flop. The flip-flop is clocked
on the rising edge of CLKIN (PD1). The preset and
clear are active High inputs. Each clear input can
use up to two product terms.
Table 33. Output Macrocell Port and Data Bit Assignments
PSD4235G2V
Product Term Allocator. The CPLD has a Prod-
uct Term Allocator. PSDsoft Express, uses the
Product Term Allocator to borrow and place prod-
uct terms from one Macrocell to another. The fol-
lowing list summarizes how product terms are
allocated: McellA0-McellA7 all have three native product
terms and may borrow up to six more McellB0-McellB3 all have four native product
terms and may borrow up to five more McellB4-McellB7 all have four native product
terms and may borrow up to six more.
Each Macrocell may only borrow product terms
from certain other Macrocells. Product terms al-
ready in use by one Macrocell are not available for
another Macrocell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required, which consume other Output Macro-
cells (OMC). If external product terms are used,
extra delay is added for the equation that required
the extra product terms. This is called product term
expansion. PSDsoft Express performs this expan-
sion as needed.
Loading and Reading the Output Macrocells
(OMC). The Output Macrocells (OMC) block oc-
cupies a memory location in the MCU address
space, as defined by the CSIOP (see the section
entitled “I/O Ports”, on page 50). The flip-flops in
each of the 16 Output Macrocells (OMC) can be
loaded from the data bus by a MCU. Loading the
Output Macrocells (OMC) with data from the MCU
takes priority over internal functions. As such, the
preset, clear, and clock inputs to the flip-flop can
be overridden by the MCU. The ability to load the
flip-flops and read them back is useful in such ap-
plications as loadable counters and shift registers,
mailboxes, and handshaking protocols.
Data is loaded to the Output Macrocells (OMC) on
the trailing edge of Write Strobe (WR/WRL,
CNTL0).
The OMC Mask Register. There is one Mask
Register for each of the two groups of eight Output
Macrocells (OMC). The Mask Registers can be
used to block the loading of data to individual Out-
put Macrocells (OMC). The default value for the
Mask Registers is 00h, which allows loading of the
Output Macrocells (OMC). When a given bit in a
Mask Register is set to a 1, the MCU is blocked
from writing to the associated Output Macrocells
37/89
PSD4235G2V
(OMC). For example, suppose McellA0-McellA3
are being used for a state machine. You would not
want a MCU write to McellA to overwrite the state
machine registers. Therefore, you would want to
load the Mask Register for McellA (Mask Macro-
cell A) with the value 0Fh.
The Output Enable of the OMC. The Output
Macrocells (OMC) can be connected to an I/O port
pin as a PLD output. The output enable of each
port pin driver is controlled by a single product
term from the AND Array, ORed with the Direction
Register output. The pin is enabled upon Power-
up if no output enable equation is defined and if
the pin is declared as a PLD output in PSDsoft Ex-
press.
If the Output Macrocell (OMC) output is declared
as an internal node and not as a port pin output in
the PSDabel file, then the port pin can be used for
other I/O functions. The internal node feedback
can be routed as an input to the AND Array.
Input Macrocells (IMC). The CPLD has 24 Input
Macrocells (IMC), one for each pin on Ports A, B,
and C. The architecture of the Input Macrocells
(IMC) is shown in Figure 16. The Input Macrocells
(IMC) are individually configurable, and can be
used as a latch, register, or to pass incoming Port
signals prior to driving them onto the PLD input
bus. The outputs of the Input Macrocells (IMC) can
be read by the MCU through the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND Array or the
MCU Address Strobe (ALE/AS). Each product
term output is used to latch or clock four Input
Macrocells (IMC). Port inputs 3-0 can be con-
trolled by one product term and 7-4 by another.
Configurations for the Input Macrocells (IMC) are
specified by PSDsoft Express (see Application
Note AN1171). Outputs of the Input Macrocells
(IMC) can be read by the MCU via the IMC buffer.
See the section entitled “I/O Ports”, on page 50.
Input Macrocells (IMC) can use Address Strobe
(ALE/AS, PD0) to latch address bits higher than
A15. Any latched addresses are routed to the
PLDs as inputs.
Input Macrocells (IMC) are particularly useful with
handshaking communication applications where
two processors pass data back and forth through
a common mailbox. Figure 18 shows a typical con-
figuration where the Master MCU writes to the Port
A Data Out Register. This, in turn, can be read by
the Slave MCU via the activation of the “Slave-
Read” output enable product term.
The Slave can also write to the Port A Input Mac-
rocells (IMC) and the Master can then read the In-
put Macrocells (IMC) directly.
Note that the “Slave-Read” and “Slave-Wr” signals
are product terms that are derived from the Slave
MCU inputs Read Strobe (RD, CNTL1), Write
Strobe (WR/WRL, CNTL0), and Slave_CS.
PSD4235G2V
External Chip Select. The CPLD also provides
eight External Chip Select (ECS0-ECS7) outputs
that can be used to select external devices. Each
External Chip Select (ECS0-ECS7) consists of
one product term that can be configured active
High or Low.
The output enable of the pin is controlled by either
the output enable product term or the Direction
Register. (See Figure 17.)
39/89
PSD4235G2V
Figure 18. Handshaking Communication Using Input Macrocells
PSD4235G2V
MCU BUS INTERFACE
The “no-glue logic” MCU Bus Interface block can
be directly connected to most popular MCUs and
their control signals. Key 16-bit MCUs, with their
bus types and control signals, are shown in Table
34. The MCU interface type is specified using the
PSDsoft Express.
PSD Interface to a Multiplexed Bus. Figure 19
shows an example of a system using a MCU with
a 16-bit multiplexed bus and a PSD4235G2V. The
ADIO port on the PSD is connected directly to the
MCU address/data bus. Address Strobe (ALE/AS,
PD0) latches the address signals internally.
Latched addresses can be brought out to Port E, F
or G. The PSD drives the ADIO data bus only
when one of its internal resources is accessed and
Read Strobe (RD, CNTL1) is active. Should the
system address bus exceed sixteen bits, Ports A,
B, C, or F may be used as additional address in-
puts.
PSD Interface to a Non-Multiplexed 8-Bit Bus.
Figure 20 shows an example of a system using a
MCU with a 16-bit non-multiplexed bus and a
PSD4235G2V. The address bus is connected to
the ADIO Port, and the data bus is connected to
Ports F and G. Ports F and G are in tri-state mode
when the PSD is not accessed by the MCU.
Should the system address bus exceed sixteen
bits, Ports A, B, or C may be used for additional
address inputs.
Table 34. MCUs and their Control Signals
Note:1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PD3-PD0, PF3-PF0) can be configured for other I/O func-
tions. ALE/AS input is optional for MCUs with a non-multiplexed bus This configuration is for MC68HC812A4_EC at 5 MHz, 3 V only.
41/89
PSD4235G2V
PSD4235G2V
Data Byte Enable Reference. MCUs have differ-
ent data byte orientations. Table 35 to Table 38
show how the PSD4235G2V interprets byte/word
operations in different bus write configurations.
Even-byte refers to locations with address A0
equal to 0, and odd byte as locations with A0 equal
to 1.
Table 35. 16-Bit Data Bus with BHE
MCU Bus Interface Examples. Figure 21 to Fig-
ure 26 show examples of the basic connections
between the PSD4235G2V and some popular
MCUs. The PSD4235G2V Control input pins are
labeled as to the MCU function for which they are
configured. The MCU bus interface is specified us-
ing PSDsoft Express. The Voltage Stand-by (VST-
BY, PE6) line should be held at Ground if not in
use.
Table 36. 16-Bit Data Bus with WRH and WRL
Table 37. 16-Bit Data Bus with SIZ0, A0
(Motorola MCU)
Table 38. 16-Bit Data Bus with LDS, UDS
(Motorola MCU)
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PSD4235G2V
80C196 and 80C186. In Figure 21, the Intel
80C196 MCU, which has a 16-bit multiplexed ad-
dress/data bus, is shown connected to a
PSD4235G2V. The Read Strobe (RD, CNTL1),
and Write Strobe (WR/WRL, CNTL0) signals are
connected to the CNTL pins. When BHE is not
used, the PSD can be configured to receive WRL
and Write Enable High-byte (WRH/DBE, PD3)
from the MCU. Higher address inputs (A16-A19)
can be routed to Ports A, B, or C as input ot the
PLD.
The AMD 80186 family has the same bus connec-
tion to the PSD as the 80C196.
PSD4235G2V
MC683xx and MC68HC16. Figure 22 shows a
MC68331 with a 16-bit non-multiplexed data bus
and 24-bit address bus. The data bus from the
MC68331 is connected to Port F (D0-D7) and Port
G (D8-D15). The SIZ0 and A0 inputs determine
the high/low byte selection. The R/W, DS and SIZ0
signals are connected to the CNTL0-CNTL2 pins.
The MC68HC16, and other members of the
MC683xx family, has the same bus connection to
the PSD as the MC68331 shown in Figure 22.
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PSD4235G2V
Figure 23. Interfacing the PSD with an 80C51XA-G3
80C51XA. The Philips 80C51XA MCU has a 16-
bit multiplexed bus with burst cycles. Address bits
(A3-A1) are not multiplexed, while (A19-A4) are
multiplexed with data bits (D15-D0).
The PSD4235G2V supports the 80C51XA burst
mode. The WRH signal is connected to PD3, and
WHL is connected to CNTL0. The RD and PSEN
signals are connected to the CNTL1 and CNTL2
pins. Figure 23 shows the schematic diagram.
The 80C51XA improves bus throughput and per-
formance by issuing burst cycles to fetch codes
from memory. In burst cycles, address A19-A4 are
latched internally by the PSD, while the 80C51XA
drives the A3-A1 signals to fetch sequentially up to
16 bytes of code. The PSD access time is then
measured from address A3-A1 valid to data in val-
id. The PSD bus timing requirement in a burst cy-
cle is identical to the normal bus cycle, except the
address setup and hold time with respect to Ad-
dress Strobe (ALE/AS, PD0) is not required.
