PSD4235G290UI ,Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs (5V Supply)Features Summary . 1Figure 1. Package . . . . . . . 1Summary Description . . . ..
PSD4235G290UI ,Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs (5V Supply)Block Diagram . . . . . 15PSD Architectural Overview 16Memory . . . . . . 16PLDs ..
PSD4235G2V-90U ,FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (3.3V SUPPLY)TABLE OF CONTENTSSummary Description . . . . . . 5In-System Programming (ISP) via JTAG . ..
PSD4235G2V-90U ,FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (3.3V SUPPLY)Absolute Maximum Ratings .68Table. Operating Conditions . . . . . . 69Table. DC Charact ..
PSD4235G2V-90U ,FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (3.3V SUPPLY)applications that includes configurable■ High Endurance:memories, PLD logic and I/O:– 100,000 Erase ..
PSD4256G6V ,FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUSBlock Diagram (Figure 4.) . . . . 15PSD ARCHITECTURAL OVERVIEW . . 16Memory . . ..
QK006RH4 , Alternistor Triacs (6 A to 40 A)
QK006VH4 , Alternistor Triacs (6 A to 40 A)
QK008DH4 , Alternistor Triacs (6 A to 40 A)
QK008L5 , Triacs (0.8 A to 35 A)
QK008LH4 , Alternistor Triacs (6 A to 40 A)
QK008N5 , Triacs (0.8 A to 35 A)
PSD4235G2-70U-PSD4235G290UI
Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs (5V Supply)
1/100March 2004
PSD4235G2Flash In-System Programmable (ISP)
for 16-bit MCUs (5V Supply)
FEATURES SUMMARY DUAL BANK FLASH MEMORIES 4 Mbit of Primary Flash Memory (8
uniform sectors, 32K x 16) 256 Kbit Secondary Flash Memory with 4
sectors Concurrent operation: read from one
memory while erasing and writing the
other 64 Kbit SRAM (BATTERY BACKED) PLD WITH MACROCELLS Over 3000 Gates of PLD: CPLD and
DPLD CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs) DPLD - user defined internal chip select
decoding SEVEN L/O PORTS WITH 52 I/O PINS 52 individually configurable I/O port pins
that can be used for the following
functions: MCU I/Os
–PLD I/Os Latched MCU address output Special function l/Os l/O ports may be configured as open-drain
outputs IN-SYSTEM PROGRAMMING (ISP) WITH
JTAG Built-in JTAG compliant serial port allows
full-chip In-System Programmability Efficient manufacturing allow easy
product testing and programming Use low cost FlashLINK cable with PC PAGE REGISTER Internal page register that can be used to
expand the microcontroller address space
by a factor of 256 PROGRAMMABLE POWER MANAGEMENT
PSD4235G2
TABLE OF CONTENTS
Features Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Summary Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9First time programming.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Inventory build-up of pre-programmed devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Expensive sockets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
In-Application Programming (IAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Simultaneous READ and WRITE to Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Complex memory mapping.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Separate Program and Data space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
PSDsoft Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 1. Pin Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 3. TQFP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 2. Pin Description (for the TQFP package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 4. PSD Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
PSD Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
ISP via JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Table 3. PLD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 4. JTAG SIgnals on Port E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
In-Application Programming (IAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 5. Methods of Programming Different Functional Blocks of the PSD . . . . . . . . . . . . . . . . .17
Development System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Figure 5. PSDsoft Express Development Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PSD Register Description and Address Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Table 6. Register Address Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Table 7. Data-In Registers - Ports A, B, C, D, E, F, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3/100
PSD4235G2Table 8. Data-Out Registers - Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 9. Direction Registers - Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 10. Control Registers - Ports E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 11. Drive Registers - Ports A, B, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 12. Drive Registers - Ports C, F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 13. Enable-Out Registers - Ports A, B, C, F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 14. Input Macrocells - Ports A, B, C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 15. Output Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 16. Output Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 17. Mask Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 18. Mask Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 19. Flash Memory Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 20. Flash Boot Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 21. JTAG Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 22. Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 23. PMMR0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 24. PMMR2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 25. VM Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 26. Memory_ID0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 27. Memory_ID1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Detailed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Table 28. Memory Block Size and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . .26Memory Block Select Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Ready/Busy (PE4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Memory Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Table 29. Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Power-up Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Reading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Read Primary Flash Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Reading the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Table 30. Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 31. Status Bits for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Data Polling (DQ7) - DQ15 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Toggle Flag (DQ6) - DQ14 for Motorola. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Error Flag (DQ5) - DQ13 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Erase Time-out Flag (DQ3) - DQ11 for Motorola. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
PSD4235G2Figure 6. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Figure 7. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Flash Memory Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Reset (RESET) Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MEMORY SELECT SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Memory Select Configuration for MCUs with Separate Program and Data Spaces . . . . . . . .35Figure 8. Priority Level of Memory and I/O Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Separate Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Combined Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
80C51XA Memory Map Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Figure 9. 8031 Memory Modules - Separate Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 10.8031 Memory Modules - Combined Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37Figure 11.Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
MEMORY ID REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38Table 32. DPLD and CPLD Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 12.PLD Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Decode PLD (DPLD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40Figure 13.DPLD Logic Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Figure 14.Macrocell and I/O Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42Table 33. Output Macrocell Port and Data Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5/100
PSD4235G2
Loading and Reading the Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43Figure 15.CPLD Output Macrocell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45Figure 16.Input Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46Figure 17.External Chip Select Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 18.Handshaking Communication Using Input Macrocells . . . . . . . . . . . . . . . . . . . . . . . . . .46
MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47Table 34. MCUs and their Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
PSD Interface to a Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48Figure 19.An Example of a Typical 16-bit Multiplexed Bus Interface . . . . . . . . . . . . . . . . . . . . . . .48
PSD Interface to a Non-Multiplexed 8-bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49Figure 20.An Example of a Typical 16-bit Non-Multiplexed Bus Interface . . . . . . . . . . . . . . . . . . .49
Data Byte Enable Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50Table 35. 16-bit Data Bus with BHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
MCU Bus Interface Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50Table 36. 16-bit Data Bus with WRH and WRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 37. 16-bit Data Bus with SIZ0, A0 (Motorola MCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 38. 16-bit Data Bus with LDS, UDS (Motorola MCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
80C196 and 80C186. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51Figure 21.Interfacing the PSD with an 80C196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
MC683xx and MC68HC16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52Figure 22.Interfacing the PSD with an MC68331 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
80C51XA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53Figure 23.Interfacing the PSD with an 80C51XA-G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
H8/300. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54Figure 24.Interfacing the PSD with an H83/2350 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
MMC2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
C16x Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55Figure 25.Interfacing the PSD with an MMC2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 26.Interfacing the PSD with a C167CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Port Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58Figure 27.General I/O Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60Table 39. Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 40. Port Operating Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 41. I/O Port Latched Address Output Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
PSD4235G2
Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Peripheral I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62Figure 28.Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
MCU Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63Table 42. Port Configuration Registers (PCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64Drive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 43. Port Pin Direction Control, Output Enable P.T. Not Defined . . . . . . . . . . . . . . . . . . . . . .64
Table 44. Port Pin Direction Control, Output Enable P.T. Defined . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 45. Port Direction Assignment Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 46. Drive Register Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Mask Macrocell Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65Table 47. Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Ports A, B and C - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66Figure 29.Port A, B and C Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Port D - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67Figure 30.Port D Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Port E - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Port F - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Port G - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68Figure 31.Port E, F and G Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Power-down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71Table 48. Effect of Power-down Mode on Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Figure 32.APD Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table 49. PSD Timing and Stand-by Current during Power-down Mode . . . . . . . . . . . . . . . . . . . .71
Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SRAM Stand-by Mode (Battery Backup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72Figure 33.Enable Power-down Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73Table 50. APD Counter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7/100
PSD4235G2
POWER-ON RESET, WARM RESET AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Power-On RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
I/O Pin, Register and PLD Status at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Reset of Flash Memory Erase and Program Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74Table 51. Status During Power-On Reset, Warm Reset and Power-down Mode . . . . . . . . . . . . . .74
Figure 34.Reset (RESET) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . .75
Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
JTAG Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76Table 52. JTAG Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
AC/DC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77Figure 35.PLD ICC /Frequency Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Table 53. Example of PSD Typical Power Calculation at VCC = 5.0V (with Turbo Mode On). . . . .78
Table 54. Example of PSD Typical Power Calculation at VCC = 5.0V (with Turbo Mode Off). . . . .79
Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80Table 55. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
DC and AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81Table 56. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 57. AC Signal Letters for PLD Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 58. AC Signal Behavior Symbols for PLD Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 59. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 60. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Figure 36.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Figure 37.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Figure 38.Switching Waveforms - Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 61. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Figure 39.Input to Output Disable / Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 62. CPLD Combinatorial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 63. CPLD Macrocell Synchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 64. CPLD Macrocell Asynchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Figure 40.Synchronous Clock Mode Timing - PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Figure 41.Asynchronous RESET / Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Figure 42.Asynchronous Clock Mode Timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . .86
Figure 43.Input Macrocell Timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 65. Input Macrocell Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 66. Program, WRITE and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Figure 44.Peripheral I/O Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
PSD4235G2Figure 45.READ Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table 67. READ Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Figure 46.WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 68. WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Figure 47.Peripheral I/O Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Table 69. Port F Peripheral Data Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Table 70. Port F Peripheral Data Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Figure 48.Reset (RESET) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Table 71. Reset (RESET)Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Table 72. Power-down Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Table 73. VSTBYON Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Figure 49.ISC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Table 74. ISC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95Figure 50.TQFP80 - 80-lead Plastic Thin, Quad, Flat Package Outline . . . . . . . . . . . . . . . . . . . . .95
Table 75. TQFP80 - 80-lead Plastic Thin, Quad, Flat Package Mechanical Data. . . . . . . . . . . . . .96
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97Table 76. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
APPENDIX A.PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98Table 77. PSD4235G2 TQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99Table 78. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
9/100
PSD4235G2
SUMMARY DESCRIPTIONThe PSD family of memory systems for microcon-
trollers (MCUs) brings In-System-Programmability
(ISP) to Flash memory and programmable logic.
The result is a simple and flexible solution for em-
bedded designs. PSD devices combine many of
the peripheral functions found in MCU based ap-
plications.
PSD devices integrate an optimized Macrocell log-
ic architecture. The Macrocell was created to ad-
dress the unique requirements of embedded
system designs. It allows direct connection be-
tween the system address/data bus, and the inter-
nal PSD registers, to simplify communication
between the MCU and other supporting devices.
The PSD family offers two methods to program the
PSD Flash memory while the PSD is soldered to
the circuit board:
In-System Programming (ISP) via JTAGAn IEEE 1149.1 compliant JTAG In-System Pro-
gramming (ISP) interface is included on the PSD
enabling the entire device (Flash memories, PLD,
configuration) to be rapidly programmed while sol-
dered to the circuit board. This requires no MCU
participation, which means the PSD can be pro-
grammed anytime, even when completely blank.
The innovative JTAG interface to Flash memories
is an industry first, solving key problems faced by
designers and manufacturing houses, such as:
First time programming. How do I get firmware
into the Flash memory the very first time JTAG is
the answer. Program the blank PSD with no MCU
involvement.
Inventory build-up of pre-programmed devic-
es. How do I maintain an accurate count of pre-
programmed Flash memory and PLD devices
based on customer demand How many and what
version JTAG is the answer. Build your hardware
with blank PSDs soldered directly to the board and
then custom program just before they are shipped
to the customer. No more labels on chips, and no
more wasted inventory.
Expensive sockets. How do I eliminate the need
for expensive and unreliable sockets JTAG is the
answer. Solder the PSD directly to the circuit
board. Program first time and subsequent times
with JTAG. No need to handle devices and bend
the fragile leads.
In-Application Programming (IAP)Two independent Flash memory arrays are includ-
ed so that the MCU can execute code from one
while erasing and programming the other. Robust
product firmware updates in the filed are possible
over any communication channel (CAN, Ethernet,
UART, J1850, etc) using this unique architecture.
Designers are relieved of these problems:
Simultaneous READ and WRITE to Flash mem-
ory. How can the MCU program the same memo-
ry from which it executing code It cannot. The
PSD allows the MCU to operate the two Flash
memory blocks concurrently, reading code from
one while erasing and programming the other dur-
ing IAP.
Complex memory mapping. How can I map
these two memories efficiently A programmable
Decode PLD (DPLD) is embedded in the PSD.
The concurrent PSD memories can be mapped
anywhere in MCU address space, segment by
segment with extermely high address resolution.
As an option, the secondary Flash memory can be
swapped out of the system memory map when
IAP is complete. A built-in page register breaks the
MCU address limit.
Separate Program and Data space. How can I
write to Flash memory while it resides in Program
space during field firmware updates My
80C51XA will not allow it. The PSD provides
means to reclassify Flash memory as Data space
during IAP, then back to Program space when
complete.
PSDsoft ExpressPSDsoft Express, a software development tool
from ST, guides you through the design process
step-by-step making it possible to complete an
embedded MCU design capable of ISP/IAP in just
hours. Select your MCU and PSDsoft Express
takes you through the remainder of the design with
point and click entry, covering PSD selection, pin
definitions, programmable logic inputs and outpus,
MCU memory map definition, ANSI-C code gener-
ation for your MCU, and merging your MCU firm-
ware with the PSD design. When complete, two
different device programmers are supported di-
rectly from PSDsoft Express: FlashLINK (JTAG)
and PSDpro.
PSD4235G2 Table 1. Pin Names
11/100
PSD4235G2
PSD4235G2
PIN DESCRIPTION
Table 2. Pin Description (for the TQFP package)
13/100
PSD4235G2
PSD4235G2
15/100
PSD4235G2
PSD4235G2
PSD ARCHITECTURAL OVERVIEWPSD devices contain several major functional
blocks. Figure 4 shows the architecture of the PSD
device family. The functions of each block are de-
scribed briefly in the following sections. Many of
the blocks perform multiple functions and are user
configurable.
MemoryEach of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discus-
sion can be found in the section entitled “Memory
Blocks“ on page 25.
The 4 Mbit primary Flash memory is the main
memory of the PSD. It is divided into 8 equally-
sized sectors that are individually selectable.
The 256 Kbit secondary Flash memory is divided
into 4 equally-sized sectors. Each sector is individ-
ually selectable.
The 64 Kbit SRAM is intended for use as a
scratch-pad memory or as an extension to the
MCU SRAM. If an external battery is connected to
the PSD’s Voltage Stand-by (VSTBY, PE6) signal,
data is retained in the event of power failure.
Each memory block can be located in a different
address space as defined by the user. The access
times for all memory types includes the address
latching and DPLD decoding time.
PLDsThe device contains two PLD blocks, the Decode
PLD (DPLD) and the Complex PLD (CPLD), as
shown in Table 3, each optimized for a different
function. The functional partitioning of the PLDs
reduces power consumption, optimizes cost/per-
formance, and eases design entry.
The DPLD is used to decode addresses and to
generate Sector Select signals for the PSD inter-
nal memory and registers. The DPLD has combi-
natorial outputs, while the CPLD can implement
more general user-defined logic functions. The
CPLD has 16 Output Macrocells (OMC) and 8
combinatorial outputs. The PSD also has 24 Input
Macrocells (IMC) that can be configured as inputs
to the PLDs. The PLDs receive their inputs from
the PLD Input Bus and are differentiated by their
output destinations, number of product terms, and
Macrocells.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo Bit in PMMR0 and other bits in
PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD propaga-
tion time when not in the Turbo mode.
I/O PortsThe PSD has 52 I/O pins divided among seven
ports (Port A, B, C, D, E, F and G). Each I/O pin
can be individually configured for different func-
tions. Ports can be configured as standard MCU I/
O ports, PLD I/O, or latched address outputs for
MCUs using multiplexed address/data buses
The JTAG pins can be enabled on Port E for In-
System Programming (ISP).
MCU Bus InterfaceThe PSD easily interfaces easily with most 16-bit
MCUs, either with multiplexed or non-multiplexed
address/data buses. The device is configured to
respond to the MCU’s control pins, which are also
used as inputs to the PLDs.
ISP via JTAG PortIn-System Programming (ISP) can be performed
through the JTAG signals on Port E. This serial in-
terface allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port E. Table 4 indicates the
JTAG pin assignments.
Table 3. PLD I/O
Table 4. JTAG SIgnals on Port E
17/100
PSD4235G2
In-System Programming (ISP)Using the JTAG signals on Port E, the entire PSD
device (memory, logic, configuration) can be pro-
grammed or erased without the use of the MCU.
In-Application Programming (IAP)The primary Flash memory can also be pro-
grammed, or re-programmed, in-system by the
MCU executing the programming algorithms out of
the secondary Flash memory, or SRAM. The sec-
ondary Flash memory can be programmed the
same way by executing out of the primary Flash
memory. Table 5 indicates which programming
methods can program different functional blocks
of the PSD.
Page RegisterThe 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or in-
ternal memory and I/O. The Page Register can
also be used to change the address mapping of
the Flash memory blocks into different memory
spaces for IAP.
Power Management Unit (PMU)The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The Turbo Bit in PMMR0 can be
reset to ’0’ and the CPLD latches its outputs and
goes to Stand-by mode until the next transition on
its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. See the section enti-
tled “Power Management” on page 70 for more de-
tails.
Table 5. Methods of Programming Different Functional Blocks of the PSD
PSD4235G2
DEVELOPMENT SYSTEMThe PSD family is supported by PSDsoft Express,
a Windows-based software development tool
(Windows-95, Windows-98, Windows-2000, Win-
dows-NT). A PSD design is quickly and easily pro-
duced in a point and click environment. The
designer does not need to enter Hardware De-
scription Language (HDL) equations, unless de-
sired, to define PSD pin functions and memory
map information. The general design flow is
shown in Figure 5. PSDsoft Express is available
from our web site (the address is given on the back
page of this data sheet) or other distribution chan-
nels.
PSDsoft Express directly supports two low cost
device programmers form ST: PSDpro and
FlashLINK (JTAG). Both of these programmers
may be purchased through your local distributor/
representative, or directly from our web site using
a credit card. The PSD is also supported by thid
party device programmers. See our web site for
the current list.
19/100
PSD4235G2
PSD REGISTER DESCRIPTION AND ADDRESS OFFSETSTable 6 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al-
located by the user to the internal PSD registers.
Table 6 provides brief descriptions of the registers
in CSIOP space. The following sections give a
more detailed description.
Table 6. Register Address OffsetNote:1. Other registers that are not part of the I/O ports.
PSD4235G2
REGISTER BIT DEFINITIONAll the registers of the PSD are included here, for
reference. Detailed descriptions of these registers
can be found in the following sections.
Table 7. Data-In Registers - Ports A, B, C, D, E, F, GNote: Bit Definitions (Read-only registers):
Read Port pin status when Port is in MCU I/O input mode.
Table 8. Data-Out Registers - Ports A, B, C, D, E, F, GNote: Bit Definitions:
Latched data for output to Port pin when pin is configured in MCU I/O output mode.
Table 9. Direction Registers - Ports A, B, C, D, E, F, GNote: Bit Definitions:
Port pin 0 = Port pin is configured in Input mode (default).
Port pin 1 = Port pin is configured in Output mode.
Table 10. Control Registers - Ports E, F, GNote: Bit Definitions:
Port pin 0 = Port pin is configured in MCU I/O mode (default).
Port pin 1 = Port pin is configured in Latched Address Out mode.
Table 11. Drive Registers - Ports A, B, D, E, GNote: Bit Definitions:
Port pin 0 = Port pin is configured for CMOS Output driver (default).
Port pin 1 = Port pin is configured for Open Drain output driver.
Table 12. Drive Registers - Ports C, FNote: Bit Definitions:
Port pin 0 = Port pin is configured for CMOS Output driver (default).
Port pin
1 = Port pin is configured in Slew Rate mode.
21/100
PSD4235G2
Table 13. Enable-Out Registers - Ports A, B, C, F
Note: Bit Definitions (Read-only registers):
Port pin 0 = Port pin is in tri-state driver (default).
Port pin 1 = Port pin is enabled.
Table 14. Input Macrocells - Ports A, B, C
Note: Bit Definitions (Read-only registers):
Read Input Macrocell (IMC7-IMC0) status on Ports A, B and C.
Table 15. Output Macrocells A Register
Note: Bit Definitions:
Write Register: Load MCellA7-MCellA0 with 0 or 1.
Read Register: Read MCellA7-MCellA0 output status.
Table 16. Output Macrocells B Register
Note: Bit Definitions:
Write Register: Load MCellB7-MCellB0 with 0 or 1.
Read Register: Read MCellB7-MCellB0 output status.
Table 17. Mask Macrocells A Register
Note: Bit Definitions:
McellA_Prot 0 = Allow MCellA flip-flop to be loaded by MCU (default).
McellA_Prot 1 = Prevent MCellA flip-flop from being loaded by MCU.
Table 18. Mask Macrocells B Register
Note: Bit Definitions:
McellB_Prot 0 = Allow MCellB flip-flop to be loaded by MCU (default).
McellB_Prot 1 = Prevent MCellB flip-flop from being loaded by MCU.
Table 19. Flash Memory Protection Register
Note: Bit Definitions (Read-only register):
Sec_Prot 1 = Primary Flash memory Sector is write protected.
Sec_Prot 0 = Primary Flash memory Sector is not write protected.
PSD4235G2
Table 20. Flash Boot Protection Register
Note: Bit Definitions:
Sec_Prot 1 = Secondary Flash memory Sector is write protected.
Sec_Prot 0 = Secondary Flash memory Sector is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
Security_Bit 1 = Security Bit in device has been set.
Table 21. JTAG Enable Register
Note: Bit Definitions:
JTAGEnable 1 = JTAG Port is enabled.
JTAGEnable 0 = JTAG Port is disabled.
Table 22. Page Register
Note: Bit Definitions:
Configure Page input to PLD. Default is PGR7-PGR0=0.
23/100
PSD4235G2
Table 23. PMMR0 Register
Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not clear the registers.
Note: Bit Definitions:
APD Enable 0 = Automatic Power-down (APD) is disabled.
1 = Automatic Power-down (APD) is enabled.
PLD Turbo 0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
PLD Array CLK 0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off.
1 = CLKIN to the PLD AND array is disconnected, saving power.
PLD MCells CLK 0 = CLKIN to the PLD Macrocells is connected.
1 = CLKIN to the PLD Macrocells is disconnected, saving power.
Table 24. PMMR2 Register
Note: For Bit 4, Bit 3, Bit 2: See Table 34 for the signals that are blocked on pins CNTL0-CNTL2.
Note: Bit Definitions:
PLD Array Addr 0 = Address A7-A0 are connected to the PLD array.
1 = Address A7-A0 are blocked from the PLD array, saving power.
(Note: in XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4)
PLD Array CNTL20 = CNTL2 input to the PLD AND array is connected.
1 = CNTL2 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL10 = CNTL1 input to the PLD AND array is connected.
1 = CNTL1 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL00 = CNTL0 input to the PLD AND array is connected.
1 = CNTL0 input to the PLD AND array is disconnected, saving power.
PLD Array ALE 0 = ALE input to the PLD AND array is connected.
1 = ALE input to the PLD AND array is disconnected, saving power.
PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected.
1 = WRH/DBE input to the PLD AND array is disconnected, saving power.
Table 25. VM Register
Note: On reset, Bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft Express. Bit0 and Bit7 are always cleared on
reset. Bit0-Bit4 are active only when the device is configured in Philips 80C51XA mode.
Note: Bit Definitions:
SR_code 0 = PSEN cannot access SRAM in 80C51XA modes.
1 = PSEN can access SRAM in 80C51XA modes.
Boot_code 0 = PSEN cannot access Secondary NVM in 80C51XA modes.
1 = PSEN can access Secondary NVM in 80C51XA modes.
FL_code 0 = PSEN cannot access Primary Flash memory in 80C51XA modes.
1 = PSEN can access Primary Flash memory in 80C51XA modes.
Boot_data 0 = RD cannot access Secondary NVM in 80C51XA modes.
1 = RD can access Secondary NVM in 80C51XA modes.
FL_data 0 = RD cannot access Primary Flash memory in 80C51XA modes.
1 = RD can access Primary Flash memory in 80C51XA modes.
Peripheral mode 0 = Peripheral mode of Port F is disabled.
1 = Peripheral mode of Port F is enabled.
PSD4235G2
Table 26. Memory_ID0 Register
Note: Bit Definitions:
F_size[3:0] 0h = There is no Primary Flash memory
1h = Primary Flash memory size is 256 Kbit
2h = Primary Flash memory size is 512 Kbit
3h = Primary Flash memory size is 1 Mbit
4h = Primary Flash memory size is 2 Mbit
5h = Primary Flash memory size is 4 Mbit
6h = Primary Flash memory size is 8 Mbit
S_size[3:0] 0h = There is no SRAM
1h = SRAM size is 16 Kbit
2h = SRAM size is 32 Kbit
3h = SRAM size is 64 Kbit
4h = SRAM size is 128 Kbit
5h = SRAM size is 256 Kbit
Table 27. Memory_ID1 Register
Note: Bit Definitions:
B_size[3:0] 0h = There is no Secondary NVM
1h = Secondary NVM size is 128 Kbit
2h = Secondary NVM size is 256 Kbit
3h = Secondary NVM size is 512 Kbit
B_type[1:0] 0h = Secondary NVM is Flash memory
1h = Secondary NVM is EEPROM
25/100
PSD4235G2
DETAILED OPERATION
As shown in Figure 4, the PSD consists of six ma-
jor types of functional blocks: Memory Blocks PLD Blocks MCU Bus Interface I/O Ports Power Management Unit (PMU) JTAG-ISP Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
Memory Blocks
The PSD has the following memory blocks: Primary Flash memory Secondary Flash memory
–SRAM
The Memory Select signals for these blocks origi-
nate from the Decode PLD (DPLD) and are user-
defined in PSDsoft Express.
Table 28 sumamarizes the sizes and organisa-
tions of the memory blocks.
Table 28. Memory Block Size and Organization
PSD4235G2
Primary Flash Memory and Secondary Flash memory Description
The primary Flash memory is divided evenly into 8
sectors. The secondary Flash memory is divided
evenly into 4 sectors. Each sector of either memo-
ry block can be separately protected from Program
and Erase cycles.
Flash memory may be erased on a sector-by-sec-
tor basis, and programmed word-by-word. Flash
sector erasure may be suspended while data is
read from other sectors of the block and then re-
sumed after reading.
During a Program or Erase cycle in Flash memory,
the status can be output on the Ready/Busy pin
(PE4). This pin is set up using PSDsoft Express.
Memory Block Select Signals. The DPLD gen-
erates the Select signals for all the internal memo-
ry blocks (see the section entitled “PLDS”, on page
38). Each of the sectors of the primary Flash mem-
ory has a Select signal (FS0-FS7) which can con-
tain up to three product terms. Each of the sectors
of the secondary Flash memory has a Select sig-
nal (CSBOOT0-CSBOOT3) which can contain up
to three product terms. Having three product terms
for each Select signal allows a given sector to be
mapped in different areas of system memory.
When using a MCU with separate Program and
Data space (80C51XA), these flexible Select sig-
nals allow dynamic re-mapping of sectors from
one memory space to the other before and after
IAP. The SRAM block has a single Select signal
(RS0).
Ready/Busy (PE4). This signal can be used to
output the Ready/Busy status of the PSD. The out-
put is a ’0’ (Busy) when a Flash memory block is
being written to, or when a Flash memory block is
being erased. The output is a ’1’ (Ready) when no
WRITE or Erase cycle is in progress.
Memory Operation
The primary Flash memory and secondary Flash
memory are addressed through the MCU Bus In-
terface. The MCU can access these memories in
one of two ways: The MCU can execute a typical bus WRITE or
READ operation just as it would if accessing a
RAM or ROM device using standard bus
cycles. The MCU can execute a specific instruction
that consists of several WRITE and READ
operations. This involves writing specific data
patterns to special addresses within the Flash
memory to invoke an embedded algorithm.
These instructions are summarized in Table
Typically, the MCU can read Flash memory using
READ operations, just as it would read a ROM de-
vice. However, Flash memory can only be erased
and programmed using specific instructions. For
example, the MCU cannot write a single byte di-
rectly to Flash memory as one would write a byte
to RAM. To program a word into Flash memory,
the MCU must execute a Program instruction, then
test the status of the Programming event. This sta-
tus test is achieved by a READ operation or polling
Ready/Busy (PE4).
Flash memory can also be read by using special
instructions to retrieve particular Flash device in-
formation (sector protect status and ID).
27/100
PSD4235G2
Table 29. Instructions
Note:1. All bus cycles are WRITE bus cycles, except the ones with the “Read” label All values are in hexadecimal:
X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses
RA = Address of the memory location to be read
RD = Data read from location RA during the READ cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0).
PA is an even address for PSD in word programming mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be
erased, or verified, must be Active (High). Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft Express. Only address bits A11-A0 are used in instruction decoding. No Unlock or instruction cycles are required when the device is in the READ mode The Reset instruction is required to return to the READ mode after reading the Flash ID, or after reading the Sector Protection Sta-
tus, or if the Error Flag Bit (DQ5/DQ13) goes High. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1,A0)=(1,0) The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass
mode.
11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is
intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status
of the primary Flash memory.
14. All WRITE bus cycles in an instruction are byte WRITE to an even address (XA4Ah or X554h). A Flash memory Program bus cycle
writes a word to an even address.
PSD4235G2
INSTRUCTIONS
An instruction consists of a sequence of specific
operations. Each received byte is sequentially de-
coded by the PSD and not executed as a standard
WRITE operation. The instruction is executed
when the correct number of bytes are properly re-
ceived and the time between two consecutive
bytes is shorter than the time-out period. Some in-
structions are structured to include READ opera-
tions after the initial WRITE operations.
The instruction must be followed exactly. Any in-
valid combination of instruction bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into READ
mode (Flash memory is read like a ROM device).
The PSD supports the instructions summarized in
Table 29: Erase memory by chip or sector Suspend or resume sector erase Program a Word Reset to READ mode Read primary Flash Identifier value Read Sector Protection Status Bypass
These instructions are detailed in Table 29., page
27. For efficient decoding of the instructions, the
first two bytes of an instruction are the coded cy-
cles and are followed by an instruction byte or con-
firmation byte. The coded cycles consist of writing
the data AAh to address XAAAh during the first cy-
cle and data 55h to address X554h during the sec-
ond cycle (unless the Bypass instruction feature is
used, as described later). Address signals A15-
A12 are Don’t Care during the instruction WRITE
cycles. However, the appropriate Sector Select
signal (FS0-FS7, or CSBOOT0-CSBOOT3) must
be selected.
The primary and secondary Flash memories have
the same instruction set (except for Read Primary
Flash Identifier). The Sector Select signals deter-
mine which Flash memory is to receive and exe-
cute the instruction. The primary Flash memory is
selected if any one of its Sector Select signals
(FS0-FS7) is High, and the secondary Flash mem-
ory is selected if any one of its Sector Select sig-
nals (CSBOOT0-CSBOOT3) is High.
Power-up Condition
The PSD internal logic is reset upon Power-up to
the READ mode. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must be held Low, and
Write Strobe (WR/WRL, CNTL0) High, during
Power-up for maximum security of the data con-
tents and to remove the possibility of data being
written on the first edge of Write Strobe (WR/WRL,
CNTL0). Any WRITE cycle initiation is locked
when VCC is below VLKO.
Reading Flash Memory
Under typical conditions, the MCU may read the
primary Flash memory, or secondary Flash mem-
ory, using READ operations just as it would a
ROM or RAM device. Alternately, the MCU may
use READ operations to obtain status information
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these memory blocks. The
following sections describe these READ functions.
Read Memory Contents
Primary Flash memory and secondary Flash
memory are placed in the READ mode after Pow-
er-up, chip reset, or a Reset Flash instruction (see
Table 29). The MCU can read the memory con-
tents of the primary Flash memory, or the second-
ary Flash memory by using READ operations any
time the READ operation is not part of an instruc-
tion.
Read Primary Flash Identifier
The primary Flash memory identifier is read with
an instruction composed of 4 operations: 3 specific
WRITE operations and a READ operation (see Ta-
ble 29). The identifier for the primary Flash memo-
ry is E8h. The secondary Flash memory does not
support this instruction.
Read Memory Sector Protection Status
The Flash memory Sector Protection Status is
read with an instruction composed of four opera-
tions: three specific WRITE operations and a
READ operation (see Table 29). The READ oper-
ation produces 01h if the Flash memory sector is
protected, or 00h if the sector is not protected.
The sector protection status for all NVM blocks
(primary Flash memory, or secondary Flash mem-
ory) can be read by the MCU accessing the Flash
Protection and Flash Boot Protection registers in
PSD I/O space. See the section entitled “Flash
Memory Sector Protect”, on page 34, for register
definitions.
29/100
PSD4235G2
Reading the Erase/Program Status Bits
The PSD provides several status bits to be used
by the MCU to confirm the completion of an Erase
or Program cycle of Flash memory. These status
bits minimize the time that the MCU spends per-
forming these tasks and are defined in Table 30.
The status byte resides in an even location, and
can be read as many times as needed. Also note
that DQ15-DQ8 is an even byte for Motorola
MCUs with a 16-bit data bus.
For Flash memory, the MCU can perform a READ
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algorithm. See the section entitled
“PROGRAMMING FLASH MEMORY”, on page
31, for details.
Table 30. Status Bits
Table 31. Status Bits for Motorola
Note:1. X = Not guaranteed value, can be read either 1 or 0. DQ15-DQ0 represent the Data Bus bits, D15-D0. FS0-FS7/CSBOOT0-CSBOOT3 are active High.
PSD4235G2
Data Polling (DQ7) - DQ15 for Motorola
When erasing or programming in Flash memory,
the Data Polling Bit (DQ7/DQ15) outputs the com-
plement of the bit being entered for programming/
writing on the DQ7/DQ15 Bit. Once the Program
instruction or the WRITE operation is completed,
the true logic value is read on the Data Polling Bit
(DQ7/DQ15, in a READ operation). Data Polling is effective after the fourth WRITE
pulse (for a Program instruction) or after the
sixth WRITE pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memory sector being erased. During an Erase cycle, the Data Polling Bit
(DQ7/DQ15) outputs a '0.' After completion of
the cycle, the Data Polling Bit (DQ7/DQ15)
outputs the last bit programmed (it is a ’1’ after
erasing). If the location to be programmed is in a
protected Flash memory sector, the
instruction is ignored. If all the Flash memory sectors to be erased
are protected, the Data Polling Bit (DQ7/
DQ15) is reset to ’0’ for about 100µs, and then
returns to the value from the previously
addressed location. No erasure is performed.
Toggle Flag (DQ6) - DQ14 for Motorola
The PSD offers another way for determining when
the Flash memory Program cycle is completed.
During the internal WRITE operation and when ei-
ther FS0-FS7 or CSBOOT0-CSBOOT3 is true, the
Toggle Flag Bit (DQ6/DQ14) bit toggles from 0 to
’1’ and 1 to ’0’ on subsequent attempts to read any
word of the memory.
When the internal cycle is complete, the toggling
stops and the data read on the Data Bus D0-D7 is
the value from the addressed memory location.
The device is now accessible for a new READ or
WRITE operation. The cycle is finished when two
successive READs yield the same output data. The Toggle Flag Bit (DQ6/DQ14) is effective
after the fourth WRITE pulse (for a Program
instruction) or after the sixth WRITE pulse (for
an Erase instruction). If the location to be programmed belongs to a
protected Flash memory sector, the
instruction is ignored. If all the Flash memory sectors selected for
erasure are protected, the Toggle Flag Bit
(DQ6/DQ14) toggles to ’0’ for about 100µs
and then returns to the value from the
previously addressed location.
Error Flag (DQ5) - DQ13 for Motorola
During a normal Program or Erase cycle, the Error
Flag Bit (DQ5/DQ13) is reset to '0.' This bit is set
to ’1’ when there is a failure during a Flash memory
Program, Sector Erase, or Bulk Erase cycle.
In the case of Flash memory programming, the Er-
ror Flag Bit (DQ5/DQ13) indicates the attempt to
program a Flash memory bit, or bits, from the pro-
grammed state, 0, to the erased state, 1, which is
not a valid operation. The Error Flag Bit (DQ5/
DQ13) may also indicate a Time-out condition
while attempting to program a word.
In case of an error in a Flash memory Sector Erase
or Word Program cycle, the Flash memory sector
in which the error occurred or to which the pro-
grammed location belongs must no longer be
used. Other Flash memory sectors may still be
used. The Error Flag Bit (DQ5/DQ13) is reset after
a Reset instruction. A Reset instruction is required
after detecting an error on the Error Flag Bit (DQ5/
DQ13).
Erase Time-out Flag (DQ3) - DQ11 for Motorola
The Erase Time-out Flag Bit (DQ3/DQ11) reflects
the time-out period allowed between two consecu-
tive Sector Erase instructions. The Erase Time-out
Flag Bit (DQ3/DQ11) is reset to ’0’ after a Sector
Erase cycle for a period of 100µs + 20% unless an
additional Sector Erase instruction is decoded. Af-
ter this period, or when the additional Sector Erase
31/100
PSD4235G2
PROGRAMMING FLASH MEMORY
Flash memory must be erased prior to being pro-
grammed. The MCU may erase Flash memory all
at once or by-sector. Although erasing Flash mem-
ory occurs on a sector or device basis, program-
ming Flash memory occurs on a word basis.
The primary and secondary Flash memories re-
quire the MCU to send an instruction to program a
word or to erase sectors (see Table 29).
Once the MCU issues a Flash memory Program or
Erase instruction, it must check the status bits for
completion. The embedded algorithms that are in-
voked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or Ready/Busy (PE4) signal.
Data Polling
Polling on the Data Polling Bit (DQ7/DQ15) is a
method of checking whether a Program or Erase
cycle is in progress or has completed. Figure 6
shows the Data Polling algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the word to be pro-
grammed in Flash memory to check the status.
The Data Polling Bit (DQ7/DQ15) becomes the
complement of the corresponding bit of the original
data word to be programmed. The MCU continues
to poll this location, comparing data and monitor-
ing the Error Flag Bit (DQ5/DQ13). When the Data
Polling Bit (DQ7/DQ15) matches the correspond-
ing bit of the original data, and the Error Flag Bit
(DQ5/DQ13) remains 0, the embedded algorithm
is complete. If the Error Flag Bit (DQ5/DQ13) is 1,
the MCU should test the Data Polling Bit (DQ7/
DQ15) again since the Data Polling Bit (DQ7/
DQ15) may have changed simultaneously with the
Error Flag Bit (DQ5/DQ13, see Figure 6).
The Error Flag Bit (DQ5/DQ13) is set if either an
internal time-out occurred while the embedded al-
gorithm attempted to program the location or if the
MCU attempted to program a ’1’ to a bit that was
not erased (not erased is logic 0).
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
word that was written to the Flash memory with the
word that was intended to be written.
When using the Data Polling method during an
Erase cycle, Figure 6 still applies. However, the
Data Polling Bit (DQ7/DQ15) is 0 until the Erase
PSD4235G2
Data Toggle
Checking the Toggle Flag Bit (DQ6/DQ14) is an-
other method of determining whether a Program or
Erase cycle is in progress or has completed. Fig-
ure 7 shows the Data Toggle algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location to be programmed in
Flash memory to check the status. The Toggle
Flag Bit (DQ6/DQ14) toggles each time the MCU
reads this location until the embedded algorithm is
complete. The MCU continues to read this loca-
tion, checking the Toggle Flag Bit (DQ6/DQ14)
and monitoring the Error Flag Bit (DQ5/DQ13).
When the Toggle Flag Bit (DQ6/DQ14) stops tog-
gling (two consecutive READs yield the same val-
ue), and the Error Flag Bit (DQ5/DQ13) remains 0,
the embedded algorithm is complete. If the Error
Flag Bit (DQ5/DQ13) is 1, the MCU should test the
Toggle Flag Bit (DQ6/DQ14) again, since the Tog-
gle Flag Bit (DQ6/DQ14) may have changed si-
multaneously with the Error Flag Bit (DQ5/DQ13,
see Figure 7).
The Error Flag Bit (DQ5/DQ13) is set if either an
internal time-out occurred while the embedded al-
gorithm attempted to program, or if the MCU at-
tempted to program a ’1’ to a bit that was not
erased (not erased is logic 0).
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
word that was written to Flash memory with the
word that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 7 still applies. the Toggle Flag
Bit (DQ6/DQ14) toggles until the Erase cycle is
complete. A '1' on the Error Flag Bit (DQ5/DQ13)
indicates a time-out condition on the Erase cycle,
a ’0’ indicates no error. The MCU can read any
even location within the sector being erased to get
the Toggle Flag Bit (DQ6/DQ14) and the Error
Flag Bit (DQ5/DQ13).
PSDsoft Express generates ANSI C code func-
tions which implement these Data Toggling algo-
rithms.
Unlock Bypass
The Unlock Bypass instruction allows the system
to program words to the Flash memories faster
than using the standard Program instruction. The
Unlock Bypass mode is entered by first initiating
two Unlock cycles. This is followed by a third
WRITE cycle containing the Unlock Bypass com-
mand, 20h (as shown in Table 29). The Flash
memory then enters the Unlock Bypass mode.
A two-cycle Unlock Bypass Program instruction is
all that is required to program in this mode. The
33/100
PSD4235G2
ERASING FLASH MEMORY
Flash Bulk Erase
The Flash Bulk Erase instruction uses six WRITE
operations followed by a READ operation of the
status register, as described in Table 29. If any
byte of the Bulk Erase instruction is wrong, the
Bulk Erase instruction aborts and the device is re-
set to the Read Memory mode.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5/
DQ13), the Toggle Flag Bit (DQ6/DQ14), and the
Data Polling Bit (DQ7/DQ15), as detailed in the
section entitled “PROGRAMMING FLASH MEM-
ORY”, on page 31. The Error Flag Bit (DQ5/DQ13)
returns a ’1’ if there has been an Erase Failure
(maximum number of Erase cycles have been ex-
ecuted).
It is not necessary to program the memory with
00h because the PSD automatically does this be-
fore erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.
Flash Sector Erase. The Sector Erase instruc-
tion uses six WRITE operations, as described in
Table 29. Additional Flash Sector Erase confirm
commands and Flash memory sector addresses
can be written subsequently to erase other Flash
memory sectors in parallel, without further coded
cycles, if the additional commands are transmitted
in a shorter time than the time-out period of about
100µs. The input of a new Sector Erase command
restarts the time-out period.
The status of the internal timer can be monitored
through the level of the Erase Time-out Flag Bit
(DQ3/DQ11). If the Erase Time-out Flag Bit (DQ3/
DQ11) is 0, the Sector Erase instruction has been
received and the time-out period is counting. If the
Erase Time-out Flag Bit (DQ3/DQ11) is 1, the
time-out period has expired and the PSD is busy
erasing the Flash memory sector(s). Before and
during Erase time-out, any instruction other than
Suspend Sector Erase and Resume Sector Erase,
abort the cycle that is currently in progress, and re-
set the device to READ mode. It is not necessary
to program the Flash memory sector with 00h as
the PSD does this automatically before erasing.
During a Sector Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5/
DQ13), the Toggle Flag Bit (DQ6/DQ14), and the
Data Polling Bit (DQ7/DQ15), as detailed in the
section entitled “PROGRAMMING FLASH MEM-
ORY”, on page 31.
During execution of the Erase cycle, the Flash
memory accepts only Reset and Suspend Sector
Erase instructions. Erasure of one Flash memory
sector may be suspended, in order to read data
from another Flash memory sector, and then re-
sumed.
Suspend Sector Erase
When a Sector Erase cycle is in progress, the Sus-
pend Sector Erase instruction can be used to sus-
pend the cycle by writing 0B0h to any even
address when an appropriate Sector Select (FS0-
FS7 or CSBOOT0-CSBOOT3) is High. (See Table
29). This allows reading of data from another
Flash memory sector after the Erase cycle has
been suspended. Suspend Sector Erase is ac-
cepted only during the Flash Sector Erase instruc-
tion execution and defaults to READ mode. A
Suspend Sector Erase instruction executed during
an Erase time-out period, in addition to suspend-
ing the Erase cycle, terminates the time out period.
The Toggle Flag Bit (DQ6/DQ14) stops toggling
when the PSD internal logic is suspended. The
status of this bit must be monitored at an address
within the Flash memory sector being erased. The
Toggle Flag Bit (DQ6/DQ14) stops toggling be-
tween 0.1µs and 15µs after the Suspend Sector
Erase instruction has been executed. The PSD is
then automatically set to READ mode.
If an Suspend Sector Erase instruction was exe-
cuted, the following rules apply: Attempting to read from a Flash memory
sector that was being erased outputs invalid
data. Reading from a Flash memory sector that was
not being erased is valid. The Flash memory cannot be programmed,
and only responds to Resume Sector Erase
and Reset instructions (READ is an operation
and is allowed). If a Reset instruction is received, data in the
Flash memory sector that was being erased is
invalid.
Resume Sector Erase
If a Suspend Sector Erase instruction was previ-
ously executed, the Erase cycle may be resumed
with this instruction. The Resume Sector Erase in-
struction consists of writing 030h to any even ad-
dress while an appropriate Sector Select (FS0-
FS7 or CSBOOT0-CSBOOT3) is High. (See Table
29.)
PSD4235G2
SPECIFIC FEATURES
Flash Memory Sector Protect
Each sector of Primary or Secondary Flash mem-
ory can be separately protected against Program
and Erase cycles. Sector Protection provides ad-
ditional data security because it disables all Pro-
gram or Erase cycles. This mode can be activated
(or deactivated) through the JTAG-ISP Port or a
Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft Express program. This auto-
matically protects selected sectors when the de-
vice is programmed through the JTAG Port or a
Device Programmer. Flash memory sectors can
be unprotected to allow updating of their contents
using the JTAG Port or a Device Programmer. The
MCU can read (but cannot change) the sector pro-
tection bits.
Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a READ of the protected data.
This allows a guarantee of the retention of the Pro-
tection status.
The sector protection status can be read by the
MCU through the Flash memory protection and
Secondary Flash memory protection registers (in
the CSIOP block) or use the Read Sector Protec-
tion instruction. See Table 19 to Table 20.
RESET
The RESET instruction consists of one WRITE cy-
cle (see Table 29). It can also be optionally pre-
ceded by the standard two WRITE decoding
cycles (writing AAh to AAAh, and 55h to 554h).
The Reset instruction must be executed after: Reading the Flash Protection Status or Flash An Error condition has occurred (and the
device has set the Error Flag Bit (DQ5/DQ13)
to ’1’) during a Flash memory Program or
Erase cycle.
The Reset instruction immediately puts the Flash
memory back into normal READ mode. However,
if there is an error condition (with the Error Flag Bit
(DQ5/DQ13) set to ’1’) the Flash memory will re-
turn to the READ mode in 25 µs after the Reset in-
struction is issued.
The Reset instruction is ignored when it is issued
during a Program or Bulk Erase cycle of the Flash
memory. The Reset instruction aborts any on-go-
ing Sector Erase cycle, and returns the Flash
memory to the normal READ mode in 25 µs.
Reset (RESET) Pin
A pulse on the Reset (RESET) pin aborts any cy-
cle that is in progress, and resets the Flash mem-
ory to the READ mode. When the reset occurs
during a Program or Erase cycle, the Flash mem-
ory takes up to 25 µs to return to the READ mode.
It is recommended that the Reset (RESET) pulse
(except for Power On Reset, as described on page
74) be at least 25µs so that the Flash memory is
always ready for the MCU to fetch the bootstrap in-
structions after the Reset cycle is complete.
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to three product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to the Voltage Stand-by (VSTBY, PE6) line. If you
have an external battery connected to the PSD,
the contents of the SRAM are retained in the event
of a power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at 2V
or greater. If the supply voltage falls below the bat-
tery voltage, an internal power switch-over to the
battery occurs.
PE7 can be configured as an output that indicates
when power is being drawn from the external bat-
tery. This Battery-on Indicator (VBATON, PE7)
signal is High when the supply voltage falls below
the battery voltage and the battery on Voltage
Stand-by (VSTBY, PE6) is supplying power to the
internal SRAM.
SRAM Select (RS0), Voltage Stand-by (VSTBY,
PE6) and Battery-on Indicator (VBATON, PE7)
are all configured using PSDsoft Express.
35/100
PSD4235G2
MEMORY SELECT SIGNALS
The Primary Flash Memory Sector Select (FS0-
FS7), Secondary Flash Memory Sector Select
(CSBOOT0-CSBOOT3) and SRAM Select (RS0)
signals are all outputs of the DPLD. They are de-
fined using PSDsoft Express. The following rules
apply to the equations for these signals: Primary Flash memory and secondary Flash
memory Sector Select signals must not be
larger than the physical sector size. Any primary Flash memory sector must not be
mapped in the same memory space as
another Flash memory sector. A secondary Flash memory sector must not be
mapped in the same memory space as
another secondary Flash memory sector. SRAM, I/O, and Peripheral I/O spaces must
not overlap. A secondary Flash memory sector may
overlap a primary Flash memory sector. In
case of overlap, priority is given to the
secondary Flash memory sector. SRAM, I/O, and Peripheral I/O spaces may
overlap any other memory sector. Priority is
given to the SRAM, I/O, or Peripheral I/O.
Example
FS0 is valid when the address is in the range of
8000h to BFFFh, CSBOOT0 is valid from 8000h to
9FFFh, and RS0 is valid from 8000h to 87FFh.
Any address in the range of RS0 always accesses
the SRAM. Any address in the range of CSBOOT0
greater than 87FFh (and less than 9FFFh) auto-
matically addresses secondary Flash memory
segment 0. Any address greater than 9FFFh ac-
cesses the primary Flash memory segment 0. You
can see that half of the primary Flash memory seg-
ment 0 and one-fourth of secondary Flash memory
segment 0 cannot be accessed in this example.
Also note that an equation that defined FS1 to any-
where in the range of 8000h to BFFFh would not
be valid.
Figure 8 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not overlap. Level 1 has the highest priority and
level 3 has the lowest.
PSD4235G2
Separate Space Modes
Program space is separated from Data space. For
example, Program Select Enable (PSEN, CNTL2)
is used to access the program code from the pri-
mary Flash memory, while Read Strobe (RD,
CNTL1) is used to access data from the secondary
Flash memory, SRAM and I/O Port blocks. This
configuration requires the VM register to be set to
0Ch (see Figure 9).
Combined Space Modes
The Program and Data spaces are combined into
one memory space that allows the primary Flash
memory, secondary Flash memory, and SRAM to
be accessed by either Program Select Enable
(PSEN, CNTL2) or Read Strobe (RD, CNTL1). For
example, to configure the primary Flash memory
in Combined space, Bits 2 and 4 of the VM register
are set to ’1’ (see Figure 10).
80C51XA Memory Map Example
See the Application Notes for examples.
37/100
PSD4235G2
PAGE REGISTER
The 8-bit Page Register increases the addressing
capability of the MCU by a factor of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0-
PGR7) are inputs to the DPLD decoder and can be
included in the Sector Select (FS0-FS7,
CSBOOT0-CSBOOT3), and SRAM Select (RS0)
equations.
If memory paging is not needed, or if not all eight
page register bits are needed for memory paging,
these bits may be used in the CPLD for general
logic. See Application Note AN1154.
Table 22 and Figure 11 show the Page Register.
The eight flip-flops in the register are connected to
the internal data bus (D0-D7). The MCU can write
to or read from the Page Register. The Page Reg-
ister can be accessed at address location CSIOP
+ E0h.
The 8-bit Read-only Memory Status Registers are
included in the CSIOP space. The user can deter-
mine the memory configuration of the PSD device
by reading the Memory ID0 and Memory ID1 reg-
isters. The content of the registers is defined as
shown in Table 26 and Table 27.
PSD4235G2
PLDS
The PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
using PSDsoft Express, the logic is programmed
into the device and available upon Power-up.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in the following sections. Figure
12 shows the configuration of the PLDs.
The DPLD performs address decoding for internal
components, such as memory, registers, and I/O
ports Select signals.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0-
ECS2) signals.
The AND Array is used to form product terms.
These product terms are specified using PSDsoft
Express. An Input Bus consisting of 82 signals is
connected to the PLDs. The signals are shown in
Table 32.
The Turbo Bit in PSD
The PLDs in the PSD4235G2 can minimize power
consumption by switching to standby when inputs
remain unchanged for an extended time of about ns. Resetting the Turbo Bit to ’0’ (Bit 3 of the
PMMR0 register) automatically places the PLDs
into standby if no inputs are changing. Turning the
Turbo mode off increases propagation delays
while reducing power consumption. See the sec-
tion entitled “Power Management”, on page 70, on
how to set the Turbo Bit.
Additionally, five bits are available in the PMMR2
register to block MCU control signals from entering
the PLDs. This reduces power consumption and
can be used only when these MCU control signals
are not used in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
Table 32. DPLD and CPLD Inputs
Note:1. The address inputs are A19-A4 in 80C51XA mode.
39/100
PSD4235G2
PSD4235G2
DECODE PLD (DPLD)
The DPLD, shown in Figure 13, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals: 8 Sector Select (FS0-FS7) signals for the
primary Flash memory (three product terms
each) 4 Sector Select (CSBOOT0-CSBOOT3)
signals for the secondary Flash memory (three
product terms each) 1 internal SRAM Select (RS0) signal (three
product terms) 1 internal CSIOP Select (PSD Configuration
Register) signal 1 JTAG Select signal (enables JTAG-ISP on
Port E) 2 internal Peripheral Select signals
(Peripheral I/O mode).
41/100
PSD4235G2
COMPLEX PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate eight External Chip Se-
lect (ECS0-ECS7), routed to Port C or Port F.
Although External Chip Select (ECS0-ECS7) can
be produced by any Output Macrocell (OMC),
these eight External Chip Select (ECS0-ECS7) on
Port C or Port F do not consume any Output Mac-
rocells (OMC).
As shown in Figure 12, the CPLD has the following
blocks: 24 Input Macrocells (IMC) 16 Output Macrocells (OMC) Product Term Allocator AND Array capable of generating up to 196
product terms Four I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
PSD4235G2
Output Macrocell (OMC)
Eight of the Output Macrocells (OMC) are con-
nected to Ports A pins and are named as McellA0-
McellA7. The other eight Macrocells are connect-
ed to Ports B pins and are named as McellB0-
McellB7.
The Output Macrocell (OMC) architecture is
shown in Figure 15. As shown in the figure, there
are native product terms available from the AND
Array, and borrowed product terms available (if
unused) from other Output Macrocells (OMC). The
polarity of the product term is controlled by the
XOR gate. The Output Macrocell (OMC) can im-
plement either sequential logic, using the flip-flop
element, or combinatorial logic. The multiplexer
selects between the sequential or combinatorial
logic outputs. The multiplexer output can drive a
port pin and has a feedback path to the AND Array
inputs.
The flip-flop in the Output Macrocell (OMC) block
can be configured as a D, T, JK, or SR type in the
PSDsoft Express program. The flip-flop’s clock,
preset, and clear inputs may be driven from a
product term of the AND Array. Alternatively, the
external CLKIN (PD1) signal can be used for the
clock input to the flip-flop. The flip-flop is clocked
on the rising edge of CLKIN (PD1). The preset and
clear are active High inputs. Each clear input can
use up to two product terms.
Table 33. Output Macrocell Port and Data Bit Assignments
43/100
PSD4235G2
Product Term Allocator
The CPLD has a Product Term Allocator. PSDsoft
Express, uses the Product Term Allocator to bor-
row and place product terms from one Macrocell to
another. The following list summarizes how prod-
uct terms are allocated: McellA0-McellA7 all have three native product
terms and may borrow up to six more McellB0-McellB3 all have four native product
terms and may borrow up to five more McellB4-McellB7 all have four native product
terms and may borrow up to six more.
Each Macrocell may only borrow product terms
from certain other Macrocells. Product terms al-
ready in use by one Macrocell are not available for
another Macrocell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required, which consume other Output Macro-
cells (OMC). If external product terms are used,
extra delay is added for the equation that required
the extra product terms. This is called product term
expansion. PSDsoft Express performs this expan-
sion as needed.
Loading and Reading the Output Macrocells
(OMC)
The Output Macrocells (OMC) block occupies a
memory location in the MCU address space, as
defined by the CSIOP (see the section entitled “I/
O Ports”, on page 58). The flip-flops in each of the
16 Output Macrocells (OMC) can be loaded from
the data bus by a MCU. Loading the Output Mac-
rocells (OMC) with data from the MCU takes prior-
ity over internal functions. As such, the preset,
clear, and clock inputs to the flip-flop can be over-
ridden by the MCU. The ability to load the flip-flops
and read them back is useful in such applications
as loadable counters and shift registers, mailbox-
es, and handshaking protocols.
Data is loaded to the Output Macrocells (OMC) on
the trailing edge of Write Strobe (WR/WRL,
CNTL0).
The OMC Mask Register
There is one Mask Register for each of the two
groups of eight Output Macrocells (OMC). The
Mask Registers can be used to block the loading
of data to individual Output Macrocells (OMC).
The default value for the Mask Registers is 00h,
which allows loading of the Output Macrocells
(OMC). When a given bit in a Mask Register is set
to a '1,' the MCU is blocked from writing to the as-
sociated Output Macrocells (OMC). For example,
suppose McellA0-McellA3 are being used for a
state machine. You would not want an MCU
WRITE to McellA to overwrite the state machine
registers. Therefore, you would want to load the
Mask Register for McellA (Mask Macrocell A) with
the value 0Fh.
The Output Enable of the OMC
The Output Macrocells (OMC) can be connected
to an I/O port pin as a PLD output. The output en-
able of each port pin driver is controlled by a single
product term from the AND Array, ORed with the
Direction Register output. The pin is enabled upon
Power-up if no output enable equation is defined
and if the pin is declared as a PLD output in PSD-
soft Express.
If the Output Macrocell (OMC) output is declared
as an internal node and not as a port pin output in
the PSDabel file, then the port pin can be used for
other I/O functions. The internal node feedback
can be routed as an input to the AND Array.
PSD4235G2
45/100
PSD4235G2
Input Macrocells (IMC)
The CPLD has 24 Input Macrocells (IMC), one for
each pin on Ports A, B, and C. The architecture of
the Input Macrocells (IMC) is shown in Figure 16.
The Input Macrocells (IMC) are individually config-
urable, and can be used as a latch, register, or to
pass incoming Port signals prior to driving them
onto the PLD input bus. The outputs of the Input
Macrocells (IMC) can be read by the MCU through
the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND Array or the
MCU Address Strobe (ALE/AS). Each product
term output is used to latch or clock four Input
Macrocells (IMC). Port inputs 3-0 can be con-
trolled by one product term and 7-4 by another.
Configurations for the Input Macrocells (IMC) are
specified by PSDsoft Express (see Application
Note AN1171). Outputs of the Input Macrocells
(IMC) can be read by the MCU via the IMC buffer.
See the section entitled “I/O Ports”, on page 58.
Input Macrocells (IMC) can use Address Strobe
(ALE/AS, PD0) to latch address bits higher than
A15. Any latched addresses are routed to the
PLDs as inputs.
Input Macrocells (IMC) are particularly useful with
handshaking communication applications where
two processors pass data back and forth through
a common mailbox. Figure 18 shows a typical con-
figuration where the Master MCU writes to the Port
A Data Out Register. This, in turn, can be read by
the Slave MCU via the activation of the “Slave-
Read” output enable product term.
The Slave can also write to the Port A Input Mac-
rocells (IMC) and the Master can then read the In-
put Macrocells (IMC) directly.
Note that the “Slave-Read” and “Slave-Wr” signals
are product terms that are derived from the Slave
MCU inputs Read Strobe (RD, CNTL1), Write
Strobe (WR/WRL, CNTL0), and Slave_CS.
PSD4235G2
External Chip Select
The CPLD also provides eight External Chip Se-
lect (ECS0-ECS7) outputs that can be used to se-
lect external devices. Each External Chip Select
(ECS0-ECS7) consists of one product term that
can be configured active High or Low.
The output enable of the pin is controlled by either
the output enable product term or the Direction
Register. (See Figure 17.)
47/100
PSD4235G2
MCU BUS INTERFACE
The “no-glue logic” MCU Bus Interface block can
be directly connected to most popular MCUs and
their control signals. Key 16-bit MCUs, with their
bus types and control signals, are shown in Table
34. The MCU interface type is specified using the
PSDsoft Express.
Table 34. MCUs and their Control Signals
Note:1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PD3-PD0, PF3-PF0) can be configured for other I/O func-
tions. ALE/AS input is optional for MCUs with a non-multiplexed bus
PSD4235G2
PSD Interface to a Multiplexed Bus
Figure 19 shows an example of a system using a
MCU with a 16-bit multiplexed bus and a
PSD4235G2. The ADIO port on the PSD is con-
nected directly to the MCU address/data bus. Ad-
dress Strobe (ALE/AS, PD0) latches the address
signals internally. Latched addresses can be
brought out to Port E, F or G. The PSD drives the
ADIO data bus only when one of its internal re-
sources is accessed and Read Strobe (RD,
CNTL1) is active. Should the system address bus
exceed sixteen bits, Ports A, B, C, or F may be
used as additional address inputs.
49/100
PSD4235G2
PSD Interface to a Non-Multiplexed 8-bit Bus
Figure 20 shows an example of a system using a
MCU with a 16-bit non-multiplexed bus and a
PSD4235G2. The address bus is connected to the
ADIO Port, and the data bus is connected to Ports
F and G. Ports F and G are in tri-state mode when
the PSD is not accessed by the MCU. Should the
system address bus exceed sixteen bits, Ports A,
B, or C may be used for additional address inputs.
PSD4235G2
Data Byte Enable Reference
MCUs have different data byte orientations. Table
35 to Table 38 show how the PSD4235G2 inter-
prets byte/word operations in different bus write
configurations. Even-byte refers to locations with
address A0 equal to '0,' and odd byte as locations
with A0 equal to '1.'
Table 35. 16-bit Data Bus with BHE
MCU Bus Interface Examples
Figure 21 to Figure 26 show examples of the basic
connections between the PSD4235G2 and some
popular MCUs. The PSD4235G2 Control input
pins are labeled as to the MCU function for which
they are configured. The MCU bus interface is
specified using PSDsoft Express. The Voltage
Stand-by (VSTBY, PE6) line should be held at
Ground if not in use.
Table 36. 16-bit Data Bus with WRH and WRL
Table 37. 16-bit Data Bus with SIZ0, A0
(Motorola MCU)
Table 38. 16-bit Data Bus with LDS, UDS
(Motorola MCU)
