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PRTR5V0U2X
Ultra low capacitance double rail-to-rail ESD protection diode
Product profile1.1 General descriptionUltra low capacitance rail-to-rail ElectroStatic Discharge (ESD) protection diodeina small
SOT143B Surface-Mounted Device (SMD) plastic package designed to protect two
Hi-Speed data lines or high-frequency signal lines from the damage caused by ESD and
other transients.
PRTR5V0U2X incorporates two pairsof ultra low capacitance rail-to-rail diodesas wellas
an additional ESD protection diode to ensure signal line protection even if no supply
voltage is available.
1.2 Features ESD protection of two Hi-Speed data lines or high-frequency signal lines Ultra low input/output to ground capacitance: C(I/O-GND) =1pF ESD protection up to 8 kV IEC 61000-4-2, level4 (ESD) Very low clamping voltage due to an integrated additional ESD protection diode Very low reverse current Small SMD plastic package
1.3 Applications USB 2.0 ports Digital Video Interface (DVI) / High Definition Multimedia Interface (HDMI) interfaces Mobile and cordless phones Personal Digital Assistants (PDA) Digital cameras Wide Area Network (WAN) / Local Area Network (LAN) systems PCs, notebooks, printers and other PC peripherals
PRTR5V0U2X
Ultra low capacitance double rail-to-rail ESD protection diode
Rev. 02 — 14 January 2008 Product data sheet
NXP Semiconductors PRTR5V0U2X
Ultra low capacitance double rail-to-rail ESD protection diode
1.4 Quick reference data[1] Measured from pin 2 and 3 to ground.
[2] Measured from pin 4 to ground.
Pinning information Ordering information Marking[1] * = -: made in Hong Kong
* = p: made in Hong Kong
* = t: made in Malaysia
* = W: made in China
Table 1. Quick reference dataTamb =25 °C unless otherwise specified.
Per diodeVRWM reverse standoff voltage - - 5.5 V
C(I/O-GND) input/output to ground
capacitance=1 MHz;
V(I/O-GND) =0V
[1]- 1 1.5 pF
Csup supply pin to ground
capacitance=1 MHz;
VCC =0V
[2] -16 - pF
Table 2. Pinning GND ground I/O1 input/output1 I/O2 input/output2
4VCC supply voltage14
006aaa482
Table 3. Ordering informationPRTR5V0U2X - plastic surface-mounted package; 4 leads SOT143B
Table 4. Marking codesPRTR5V0U2X *R1
NXP Semiconductors PRTR5V0U2X
Ultra low capacitance double rail-to-rail ESD protection diode Limiting values
Table 5. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
Per deviceTamb ambient temperature −40 +85 °C
Tstg storage temperature −55 +125 °C
Table 6. ESD standards compliance
Per diodeIEC 61000-4-2; level4 (ESD) >8kV (contact)
NXP Semiconductors PRTR5V0U2X
Ultra low capacitance double rail-to-rail ESD protection diode Characteristics[1] Measured from pin2,3 and 4 to ground.
[2] Measured from pin 4 to ground.
[3] Measured from pin2 and3 to ground.
[4] Measured from pin2topin3.
Table 7. CharacteristicsTamb =25 °C unless otherwise specified.
Per diodeVRWM reverse standoff voltage - - 5.5 V reverse current VR =3V [1]- <1 100 nA
VBR breakdown voltage [2] 6- 9V
C(I/O-GND) input/output to ground
capacitance=1 MHz;
V(I/O-GND) =0V
[3]- 1 1.5 pF
C(I/O-I/O) input/output to input/output
capacitance=1 MHz;
V(I/O-I/O) =0V
[4]- 0.6 - pF
Csup supply pin to ground
capacitance=1 MHz;
VCC =0V
[2] -16 - pF forward voltage - 0.7 - V
NXP Semiconductors PRTR5V0U2X
Ultra low capacitance double rail-to-rail ESD protection diode
NXP Semiconductors PRTR5V0U2X
Ultra low capacitance double rail-to-rail ESD protection diode Application informationHandling data rates up to 480 Mbit/s, USB 2.0 interfaces require ESD protection devices
with an extremely low line capacitance in order to avoid signal distortion.
With a capacitance of only 1 pF, the PRTR5V0U2X offers IEC 61000-4-2, level4
compliant ESD protection.
The PRTR5V0U2X integrates two pairsof ultra low capacitance rail-to-rail ESD protection
diodes and an additional ESD protection diode.
The additional ESD protection diode connected between ground and VCC prevents
charging of the supply.
To achieve the maximum ESD protection level, no additional external capacitors are
required.
Circuit board layout and protection device placementCircuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended: Place the PRTR5V0U2X as close to the input terminal or connector as possible. The path length between the PRTR5V0U2X and the protected line should be
minimized. Keep parallel signal paths to a minimum. Avoid running protected conductors in parallel with unprotected conductors. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
ground loops. Minimize the length of the transient return path to ground. Avoid using shared transient return paths to a common ground point. Ground planes should be used whenever possible. For multilayer PCBs, use ground
vias.