PNX1502E/G ,Connected media processorThermal Characteristics.1-8.9 Audio Output Interface . . . . 1-37208.10 SPDIF I/O Interface . . ..
PNX3000HL/N3 ,Analog front end for digital video processors
PNX3000HL/N3 ,Analog front end for digital video processors
PNX3000HL/N3 ,Analog front end for digital video processors
PNX8511HW/B1 ,PNX8510; PNX8511; Analog companion chip
PNX8511HW/B1 ,PNX8510; PNX8511; Analog companion chip
PT4562C , 30-W 48-V Input Isolated DC/DC Converter
PT4661C , 30-A Dual Output Isolated DC/DC Converter
PT4661C , 30-A Dual Output Isolated DC/DC Converter
PT4800 , Thin Type Phototransistor
PT480F , Narrow Acceptance Phototransistor
PT4841A , 65-W TRIPLE OUTPUT ISOLATED DC/DC CONVERTER FOR DSL APPLICATIONS
PNX1500E-PNX1500E/G-PNX1501E-PNX1501E/G-PNX1502E-PNX1502E/G
Connected media processor
PNX15xx Series Data Book olume 1 of 1
Connected Media Processor
Rev. 2 — 1 December 2004
Philips Semiconductors PNX15xx Series
Volume 1 of 1 Connected Media Processor
Chapter 1: Integrated Circuit Data Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
2.1 Boundary Scan Notice. . . . . . . . . . . . . . . . . . . . .1-1
2.2 I/O Circuit Summary. . . . . . . . . . . . . . . . . . . . . . .1-1
2.3 Signal Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3
2.3.1 Power Pin List. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
2.3.2 Pin Reference Voltage. . . . . . . . . . . . . . . . . . . . 1-19
Parametric Characteristics . . . . . . . . . . . . . 1-19
3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . 1-19
3.2 Operating Range and Thermal Characteristics.1-
Power Supplies Sequence. . . . . . . . . . . . . . 1-20
Power Supply and Operating Speeds . . 1-21
Power Consumption. . . . . . . . . . . . . . . . . . . . 1-21
6.1 Leakage current Power Consumption . . . . . . 1-21
6.2 Standby Power Consumption. . . . . . . . . . . . . . 1-21
6.3 Typical Power Consumption for Typical
Applications1-21
6.4 Expected Maximum Currents. . . . . . . . . . . . . . 1-22
DC/AC I/O Characteristics . . . . . . . . . . . . . . 1-22
7.1 Input Crystal Specification . . . . . . . . . . . . . . . . 1-23
7.2 SSTL_2 type I/O Circuit. . . . . . . . . . . . . . . . . . . 1-23
7.3 BPX2T14MCP Type I/O Circuit . . . . . . . . . . . . 1-25
7.4 BPTS1CHP and BPTS1CP Type I/O Circuit. 1-26
7.5 BPTS3CHP Type I/O Circuit. . . . . . . . . . . . . . . 1-27
7.6 IPCHP and IPCP Type I/O Circuit. . . . . . . . . . 1-28
7.7 BPT3MCHDT5V and BPT3MCHT5V Type I/O
Circuit1-28
7.8 IIC3M4SDAT5V and IIC3M4SCLT5V type I/O
circuit1-29
7.9 PCIT5V type I/O circuit. . . . . . . . . . . . . . . . . . . .1-29
Timing Specification . . . . . . . . . . . . . . . . . . . .1-29
8.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-30
8.2 DDR DRAM Interface. . . . . . . . . . . . . . . . . . . . .1-30
8.3 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . .1-31
8.4 QVCP, LCD and FGPO Interfaces. . . . . . . . . .1-33
8.5 VIP and FGPI Interfaces . . . . . . . . . . . . . . . . . .1-34
8.6 10/100 LAN In MII Mode . . . . . . . . . . . . . . . . . .1-34
8.7 10/100 LAN In RMII Mode. . . . . . . . . . . . . . . . .1-35
8.8 Audio Input Interface . . . . . . . . . . . . . . . . . . . . .1-36
8.9 Audio Output Interface. . . . . . . . . . . . . . . . . . . .1-37
8.10 SPDIF I/O Interface . . . . . . . . . . . . . . . . . . . . . .1-38
8.11 I2C I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . .1-39
8.12 GPIO Interface. . . . . . . . . . . . . . . . . . . . . . . . . . .1-40
8.13 JTAG Interface. . . . . . . . . . . . . . . . . . . . . . . . . . .1-41
Package Outline. . . . . . . . . . . . . . . . . . . . . . . . .1-42
10. Board Design Guidelines . . . . . . . . . . . . . . .1-4310.1 Power Supplies Decoupling . . . . . . . . . . . . . . .1-43
10.2 Analog Supplies. . . . . . . . . . . . . . . . . . . . . . . . . .1-44
10.2.1 The 3.3 V Analog Supply. . . . . . . . . . . . . . . . . .1-44
10.2.2 The 1.2-1.3-V Analog Supply . . . . . . . . . . . . . .1-44
10.3 DDR SDRAM interface. . . . . . . . . . . . . . . . . . . .1-45
10.3.1 Do DDR Devices Require Termination?. . . . .1-46
10.3.2 What if I really want to use termination for the
PNX1500?1-46
10.4 Package Handling, Soldering and Thermal
Properties1-46
11. Miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . . .1-47
12. Soft Errors Due to Radiation. . . . . . . . . . . .1-47
13. Ordering Information. . . . . . . . . . . . . . . . . . . .1-47
Chapter 2: Overview Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
1.1 PNX15xx Series Functional Overview . . . . . . .2-1
1.2 PNX15xx Series Features Summary . . . . . . . .2-3
PNX15xx Series Functional Block Diagram2-5
System Resources. . . . . . . . . . . . . . . . . . . . . . .2-6
3.1 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
3.2 System Booting. . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
3.3 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
3.4 Power Management. . . . . . . . . . . . . . . . . . . . . . .2-7
3.5 Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
3.6 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
System Memory . . . . . . . . . . . . . . . . . . . . . . . . .2-9
4.1 MMI - Main Memory Interface . . . . . . . . . . . . . .2-9
4.2 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
TM3260 VLIW Media Processor Core. . . 2-10
MPEG Decoding . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Image Processing. . . . . . . . . . . . . . . . . . . . . . .2-127.1 Pixel Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12
7.2 Video Input Processor . . . . . . . . . . . . . . . . . . . .2-14
7.3 Memory Based Scaler . . . . . . . . . . . . . . . . . . . .2-14
7.4 2D Drawing and DMA Engine. . . . . . . . . . . . . .2-15
7.5 Quality Video Composition Processor. . . . . . .2-15
7.5.1 External Video Improvement Post Processing .2-
Audio processing and Input/Output . . . .2-178.1 Audio Processing . . . . . . . . . . . . . . . . . . . . . . . .2-17
8.2 Audio Inputs and Outputs . . . . . . . . . . . . . . . . .2-17
General Purpose Interfaces. . . . . . . . . . . . .2-189.1 Video/Data Input Router . . . . . . . . . . . . . . . . . .2-18
9.2 Video/Data Output Router . . . . . . . . . . . . . . . . .2-19
9.3 Fast General Purpose Input . . . . . . . . . . . . . . .2-20
9.4 Fast General Purpose Output. . . . . . . . . . . . . .2-21
10. Peripheral Interface . . . . . . . . . . . . . . . . . . . . .2-2110.1 GPIO - General Purpose Software I/O and
able of Contents
Philips Semiconductors PNX15xx Series
Volume 1 of 1
10.1.2 timestamping. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
10.1.3 event sequence monitoring and signal generation
10.1.4 GPIO pin reset value . . . . . . . . . . . . . . . . . . . . . 2-23
10.2 IR Remote Control Receiver and Blaster. . . . 2-23
10.3 PCI-2.2 & XIO-16 Bus Interface Unit . . . . . . . 2-23
10.3.1 PCI Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
10.3.2 Simple Peripheral Capabilities (‘XIO-8/16’) . .2-24
10.3.3 IDE Drive Interface . . . . . . . . . . . . . . . . . . . . . . .2-26
10.4 10/100 Ethernet MAC. . . . . . . . . . . . . . . . . . . . .2-26
11. Endian Modes. . . . . . . . . . . . . . . . . . . . . . . . . . .2-26
12. System Debug . . . . . . . . . . . . . . . . . . . . . . . . . .2-27
Chapter 3: System On Chip Resources Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 System Memory Map . . . . . . . . . . . . . . . . . . . .3-1
2.1 The PCI View . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
2.2 The CPU View. . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
2.3 The DCS View Or The System View . . . . . . . .3-4
2.4 The Programmable DCS Apertures . . . . . . . . .3-5
2.4.1 DCS DRAM Aperture Control MMIO Registers3-6
2.5 Aperture Boundaries . . . . . . . . . . . . . . . . . . . . . .3-6 System Principles . . . . . . . . . . . . . . . . . . . . . . .3-7
3.1 Module ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
3.2 Powerdown bit. . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
3.3 System Module MMIO registers . . . . . . . . . . . .3-8 System Endian Mode . . . . . . . . . . . . . . . . . . . .3-8
4.1 System Endian Mode MMIO registers . . . . . . .3-9 System Semaphores . . . . . . . . . . . . . . . . . . . .3-9
5.1 Semaphore Specification . . . . . . . . . . . . . . . . . .3-9
5.2 Construction of a 12-bit ID . . . . . . . . . . . . . . . . .3-9
5.3 The Master Semaphore. . . . . . . . . . . . . . . . . . . 3-10
5.4 Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10
5.5 Semaphore MMIO Registers. . . . . . . . . . . . . . .3-11 System Related Information for TM32603-12
6.1 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12
6.2 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
6.3 System Parameters for TM3260 . . . . . . . . . . .3-15
6.3.1 TM3260 System Parameters MMIO Registers .3- Video Input and Output Routers . . . . . . . .3-16
7.1 MMIO Registers for the Input/Output Video/Data
Router3-17 Miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . . .3-26
8.1 Miscellaneous System MMIO registers. . . . . .3-27 System Registers Map Summary . . . . . . .3-29
10. Simplified Internal Bus Infrastructure . .3-30
11. MMIO Memory MAP . . . . . . . . . . . . . . . . . . . . .3-31
12. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-32
Chapter 4: Reset Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Functional Description . . . . . . . . . . . . . . . . . .4-1
2.1 RESET_IN_N or POR_IN_N? . . . . . . . . . . . . . .4-3
2.2 The watchdog Timer . . . . . . . . . . . . . . . . . . . . . .4-4
2.2.1 The Non Interrupt Mode . . . . . . . . . . . . . . . . . . .4-4
2.2.2 The Interrupt Mode. . . . . . . . . . . . . . . . . . . . . . . .4-5
2.3 The Software Reset. . . . . . . . . . . . . . . . . . . . . . .4-6
2.4 The External Software Reset . . . . . . . . . . . . . . .4-6 Timing Description. . . . . . . . . . . . . . . . . . . . . . .4-7
3.1 The Hardware Timing. . . . . . . . . . . . . . . . . . . . . .4-7
3.2 The Software Timing . . . . . . . . . . . . . . . . . . . . . .4-8 Register Definitions. . . . . . . . . . . . . . . . . . . . . .4-9 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-10
Chapter 5: The Clock Module Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 Functional Description . . . . . . . . . . . . . . . . . .5-1
2.1 The Modules and their Clocks . . . . . . . . . . . . . .5-4
2.2 Clock Sources for PNX15xx Series. . . . . . . . . .5-7
2.2.1 PLL Specification . . . . . . . . . . . . . . . . . . . . . . . . .5-8
2.2.2 The Clock Dividers. . . . . . . . . . . . . . . . . . . . . . . 5-10
2.2.3 The DDS Clocks. . . . . . . . . . . . . . . . . . . . . . . . . 5-11
2.2.4 DDS and PLL Assignment Summary . . . . . . . 5-11
2.2.5 External Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
2.3 Clock Control Logic . . . . . . . . . . . . . . . . . . . . . . 5-13
2.4 Bypass Clock Sources. . . . . . . . . . . . . . . . . . . . 5-14
2.5 Power-up and Reset sequence . . . . . . . . . . . . 5-15
2.6 Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
2.9 Clock Detection . . . . . . . . . . . . . . . . . . . . . . . . . .5-18
2.10 VDO Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-19
2.11 GPIO Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-20
2.11.1 Setting GPIO[14:12]/GCLOCK[2:0] as Clock
Outputs5-20
2.11.2 GPIO[6:4]/CLOCK[6:4] as Clock Outputs. . . .5-20
2.12 Clock Block Diagrams . . . . . . . . . . . . . . . . . . . .5-20
2.12.1 TM3260, DDR and QVCP clocks. . . . . . . . . . .5-21
2.12.2 Clock Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . .5-23
2.12.3 Internal PNX15xx Series Clock from Dividers5-24
2.12.4 GPIO Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-26
2.12.5 External Clocks . . . . . . . . . . . . . . . . . . . . . . . . . .5-27
2.12.6 SPDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-31
Registers Definition. . . . . . . . . . . . . . . . . . . . .5-31
Philips Semiconductors PNX15xx Series
Volume 1 of 1
Chapter 6: Boot Module Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 Functional Description . . . . . . . . . . . . . . . . . .6-1
2.1 The Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
2.2 Boot Module Operation . . . . . . . . . . . . . . . . . . . .6-4
2.2.1 MMIO Bus Interface. . . . . . . . . . . . . . . . . . . . . . .6-4
2.2.2 I2C Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4
2.2.3 Boot Control/State Machine . . . . . . . . . . . . . . . .6-5
2.3 The Boot Command Language . . . . . . . . . . . . .6-5 PNX15xx Series Boot Scripts Content. . .6-6
3.1 The Common Behavior . . . . . . . . . . . . . . . . . . . .6-6
3.1.1 Binary Sequence for the Common Boot Script6-9
3.2 The Specifics of the Boot From Flash Memory
Devices6-10
3.2.1 Binary Sequencefor the Sectionofthe Flash Boot
3.3 The Specifics of the Host-Assisted Mode. . . .6-12 The Boot From an I2C EEPROM . . . . . . . .6-14
4.1 External I2C Boot EEPROM Types. . . . . . . . .6-14
4.2 The Boot Commands and The Endian Mode.6-15
4.3 Details on I2C Operation . . . . . . . . . . . . . . . . . .6-15 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-16
Chapter 7: PCI-XIO Module Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 Functional Description . . . . . . . . . . . . . . . . . .7-2
2.1 Document title variable Block Level Diagram .7-3
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
3.1.1 NAND-Flash Interface Operation. . . . . . . . . . . .7-5
3.1.2 Motorola Style Interface . . . . . . . . . . . . . . . . . . 7-10
3.1.3 NOR Flash Interface . . . . . . . . . . . . . . . . . . . . . 7-11
3.1.4 IDE Description. . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
3.2 PCI Interrupt Enable Register . . . . . . . . . . . . . 7-17 Application Notes. . . . . . . . . . . . . . . . . . . . . . .7-18
4.1 DTL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
4.2 System Memory Bus Interface, the MTL Bus 7-18
4.3 XIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-19
4.3.1 Motorola Interface . . . . . . . . . . . . . . . . . . . . . . . .7-19
4.3.2 NAND-Flash Interface . . . . . . . . . . . . . . . . . . . .7-19
4.3.3 NOR Flash Interface. . . . . . . . . . . . . . . . . . . . . .7-19
4.3.4 IDE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20
4.4 PCI Endian Support . . . . . . . . . . . . . . . . . . . . . .7-20
4.5 General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20 Register Descriptions. . . . . . . . . . . . . . . . . . .7-20
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . .7-21
Chapter 8: General Purpose Input Output Pins Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 Functional Description . . . . . . . . . . . . . . . . . .8-2
2.1 GPIO: The Basic Pin Behavior. . . . . . . . . . . . . .8-2
2.1.1 GPIO Mode settings. . . . . . . . . . . . . . . . . . . . . . .8-4
2.1.2 GPIO Data Settings MMIO Registers. . . . . . . .8-4
2.1.3 GPIO Pin Status Reading . . . . . . . . . . . . . . . . . .8-6
2.2 GPIO: The Event Monitoring Mode. . . . . . . . . .8-6
2.2.1 Timestamp Reference clock. . . . . . . . . . . . . . . .8-7
2.2.2 Timestamp format. . . . . . . . . . . . . . . . . . . . . . . . .8-7
2.3 GPIO: The Signal Monitoring & Pattern
Generation Modes8-7
2.3.1 The Signal Monitoring Mode. . . . . . . . . . . . . . . .8-8
2.3.2 The Signal Pattern Generation Mode. . . . . . . 8-11
2.4 GPIO Error Behaviour . . . . . . . . . . . . . . . . . . . . 8-14
2.4.1 GPIO Frequency Restrictions. . . . . . . . . . . . . . 8-15
2.5 The GPIO Clock Pins. . . . . . . . . . . . . . . . . . . . . 8-17
2.6 GPIO Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
2.7 Timer Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
2.8 Wake-up Interrupt. . . . . . . . . . . . . . . . . . . . . . . . 8-18
2.9 External Watchdog. . . . . . . . . . . . . . . . . . . . . . . 8-18 IR Applications . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
3.1 Duty-cycle programming . . . . . . . . . . . . . . . . . .8-19
3.2 Spike Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . .8-20 MMIO Registers . . . . . . . . . . . . . . . . . . . . . . . . .8-21
4.1 GPIO Mode Control Registers . . . . . . . . . . . . .8-24
4.2 GPIO Data Control . . . . . . . . . . . . . . . . . . . . . . .8-26
4.3 Readable Internal PNX15xx Series Signals. .8-26
4.4 Sampling and Pattern Generation Control
Registers for the FIFO Queues8-27
4.5 Signal and Event Monitoring Control Registersfor
the Timestamp Units8-34
4.6 Timestamp Unit Registers . . . . . . . . . . . . . . . . .8-34
4.7 GPIO Time Counter . . . . . . . . . . . . . . . . . . . . . .8-34
4.8 GPIO TM3260 Timer Input Select . . . . . . . . . .8-35
4.9 GPIO Interrupt Status. . . . . . . . . . . . . . . . . . . . .8-35
4.10 Clock Out Select . . . . . . . . . . . . . . . . . . . . . . . . .8-36
4.11 GPIO Interrupt Registers for the FIFO Queues
(One for each FIFO Queue)8-37
4.12 GPIO Module Status Register for all 12
Timestamp Units8-38
4.13 GPIO POWERDOWN . . . . . . . . . . . . . . . . . . . .8-43
4.14 GPIO Module ID . . . . . . . . . . . . . . . . . . . . . . . . .8-43
4.15 GPIO IO_SEL Selection Values. . . . . . . . . . . .8-43
Chapter 9: DDR Controller
Philips Semiconductors PNX15xx Series
Volume 1 of 1
2.1 Start and Warm Start. . . . . . . . . . . . . . . . . . . . . .9-2
2.1.1 The Start Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2
2.1.2 Warm Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2
2.1.3 Observing Start State . . . . . . . . . . . . . . . . . . . . .9-3
2.2 Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
2.2.1 The First Level of Arbitration: Between the DMA
and the CPU9-3
2.2.2 Second Level of Arbitration. . . . . . . . . . . . . . . . .9-6
2.2.3 Dynamic Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . .9-6
2.2.4 Pre-Emption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
2.2.5 Back Log Buffer (BLB). . . . . . . . . . . . . . . . . . . . .9-9
2.2.6 PMAN (Hub) versus DDR Controller Interaction9-
2.3 Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
2.3.1 Memory Region Mapping Scheme . . . . . . . . . 9-10
2.3.2 DDR Memory Rank Locations . . . . . . . . . . . . . 9-12
2.4 Clock Programming . . . . . . . . . . . . . . . . . . . . . . 9-13
2.5 Power Management. . . . . . . . . . . . . . . . . . . . . . 9-13
2.5.1 Halting and Unhalting . . . . . . . . . . . . . . . . . . . . 9-14
2.5.2 MMIO Directed Halt . . . . . . . . . . . . . . . . . . . . . . 9-14
2.5.3 Auto Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
2.5.4 Observing Halt Mode. . . . . . . . . . . . . . . . . . . . . 9-15
2.5.5 Sequence of Actions . . . . . . . . . . . . . . . . . . . . . 9-16 Application Notes. . . . . . . . . . . . . . . . . . . . . . .9-16
3.1 Memory Configurations . . . . . . . . . . . . . . . . . . .9-16
3.2 Error Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . .9-17
3.3 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-17
3.4 Data Coherency. . . . . . . . . . . . . . . . . . . . . . . . . .9-18
3.5 Programming the Internal Arbiter. . . . . . . . . . .9-18
3.6 The DDR Controller and the DDR Memory
Devices9-20 Timing Diagrams and Tables. . . . . . . . . . . .9-20
4.0.1 Tcas Timing Parameter . . . . . . . . . . . . . . . . . . .9-21
4.1 Trrd and Trc Timing Parameters . . . . . . . . . . .9-21
4.2 Trfc Timing Parameter . . . . . . . . . . . . . . . . . . . .9-21
4.3 Twr Timing Parameter . . . . . . . . . . . . . . . . . . . .9-22
4.4 Tras Timing Parameter . . . . . . . . . . . . . . . . . . .9-22
4.5 Trp Timing Parameter . . . . . . . . . . . . . . . . . . . .9-22
4.6 Trcd_rd Timing Parameter. . . . . . . . . . . . . . . . .9-23
4.7 Trcd_wr Timing Parameter . . . . . . . . . . . . . . . .9-23 Register Descriptions. . . . . . . . . . . . . . . . . . .9-23
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . .9-24
5.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . .9-25 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-32
Chapter 10: LCD Controller Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
1.1 LCD Controller Features. . . . . . . . . . . . . . . . . . 10-1 Functional Description . . . . . . . . . . . . . . . . . 10-1
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
2.2 Power Sequencing. . . . . . . . . . . . . . . . . . . . . . . 10-2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
3.2 Power Sequencing State Machine . . . . . . . . . 10-3
3.2.1 IDLE state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-4
3.2.2 DCEN state . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-4
3.2.3 BLEN state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5
3.2.4 PEPED state . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5
3.3 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5
3.4 Gating Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5 Register Descriptions. . . . . . . . . . . . . . . . . . .10-6
4.1 LCD MMIO Registers . . . . . . . . . . . . . . . . . . . . .10-7
Chapter 11: QVCP Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 Functional Description . . . . . . . . . . . . . . . . . 11-4
2.1 QVCP Block Diagram . . . . . . . . . . . . . . . . . . . . 11-4
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
2.3 Layer Resources and Functions . . . . . . . . . . . 11-6
2.3.1 Memory Access Control (DMA CTRL) . . . . . . 11-6
2.3.2 Pixel Formatter Unit (PFU) . . . . . . . . . . . . . . . . 11-7
2.3.3 Chroma Key and Undither (CKEY/UDTH) Unit11-
2.3.4 Chroma Upsample Filter (CUPS) . . . . . . . . . 11-11
2.3.5 Linear Interpolator (LINT) . . . . . . . . . . . . . . . . 11-11
2.3.6 Video/Graphics Contrast Brightness Matrix
(VCBM)11-11
2.3.7 Layer and Fetch Control . . . . . . . . . . . . . . . . . 11-12
2.4 Pool Resources and Functions . . . . . . . . . . . 11-13
2.4.1 CLUT (Color Look Up Table) . . . . . . . . . . . . . 11-13
2.4.2 DCTI (Digital Chroma/Color Transient
2.4.3 HSRU (Horizontal Sample Rate Upconverter).11-
2.4.4 HIST (Histogram Modification) Unit. . . . . . . .11-14
2.4.5 LSHR (Luminance/Luma Sharpening) Unit .11-14
2.4.6 Color Features (CFTR) Unit . . . . . . . . . . . . . .11-14
2.4.7 PLAN (Semi Planar DMA) Unit. . . . . . . . . . . .11-15
2.5 Screen Timing Generator . . . . . . . . . . . . . . . .11-15
2.6 Mixer Structure . . . . . . . . . . . . . . . . . . . . . . . . .11-16
2.6.1 Key Generation . . . . . . . . . . . . . . . . . . . . . . . . .11-18
2.6.2 Alpha Blending. . . . . . . . . . . . . . . . . . . . . . . . . .11-19
2.7 Output Pipeline Structure. . . . . . . . . . . . . . . . .11-19
2.7.1 Supported Output Formats . . . . . . . . . . . . . . .11-20
2.7.2 Layer Selection . . . . . . . . . . . . . . . . . . . . . . . . .11-20
2.7.3 Chrominance Downsampling (CDNS). . . . . .11-20
2.7.4 Gamma Correction and Noise Shaping (GNSH&
ONSH)11-20
2.7.5 Output Interface Modes . . . . . . . . . . . . . . . . . .11-21
2.7.6 Auxiliary Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .11-22
