PM8800ATR ,Integrated IEEE 802.3af compliant PoE-PD interface and PWM controller with support of external sourceElectrical characteristic . . . . . . 104 Device description and operation . . . . . 145 P ..
PM8834 ,4 A dual low side MOSFET driverfeatures TTL/CMOS-compatible thresholds.PWM input signal for Driver 1 featuring TTL/CMOS-compatible ..
PM8841 ,Single channel low-side gate driverblock diagram,1B7+9&&89/289/2B7+287/HYHO,1VKLIWHU*1'$0 2/13 DocID027119 Rev 1PM8841 Pin connec ..
PM9313-HC ,Sierra, Inc - ENHANCED TT1™ SWITCH FABRIC
PMB2100 ,GSM LO1 VCOSpecification, Version 1.1, 2001-07-30PMB 2100GSM LO1 VCOWireless ComponentsNever s t op thinking.E ..
PMB2205S ,Quadrature Phase Modulatorcharacteristics.Terms of delivery and rights to change design reserved.For questions on technology, ..
PSD311-B-15U ,Low cost field programmable microcontroller peripherals, 150nsapplications.PSD3XXR SRAM-less version of the PSD3XX. If you don’t require the 16 Kb SRAM orneed a ..
PSD311-B-70J ,Low Cost Field Programmable Microcontroller PeripheralsApplications .67 ZPSD Background 6TM7.1 Integrated Power Management Operation...78 Operating Modes ..
PSD311B-70J ,PSD3XX/ZPSD3XX FAMILY LOW COST MICROCONTROLLER PERIPHERALSApplications .67 ZPSD Background 6TM7.1 Integrated Power Management Operation...78 Operating Modes ..
PSD311-B-70U ,Low Cost Field Programmable Microcontroller PeripheralsFeatures ........44 PSD3XX Family Feature Summary .55 Partial Listing of Microcontrollers Supported ..
PSD311-B-90JI ,Programmable system device, 14 PLD inputs, EPROM=256K, SRAM=16K, bus width x8, 5V, 90nsPSD3XX ZPSD3XX ZPSD3XXVPSD3XXR ZPSD3XXR ZPSD3XXRVLow Cost Field Programmable Microcontroller Periph ..
PSD311B-90JI ,PSD3XX/ZPSD3XX FAMILY LOW COST MICROCONTROLLER PERIPHERALSFeatures ........44 PSD3XX Family Feature Summary .55 Partial Listing of Microcontrollers Supported ..
PM8800A-PM8800ATR
Integrated IEEE 802.3af compliant PoE-PD interface and PWM controller with support of external source
February 2008 Rev 2 1/35
PM8800AIntegrated IEEE 802.3af compliant PoE-PD interface
and PWM controller with support of external source
Features IEEE 802.3af compliant PD interface Works with power supplied from Ethernet LAN
cables or from local auxiliary sources Integrated 100 V, 0.5 Ω, 800 mA hot-swap
MOSFET Integrated signature resistor Programmable in-rush current limit Programmable classification current Programmable DC current limit up to 800 mA High voltage start-up bias regulator Thermal shutdown protection Current mode pulse width modulator Programmable oscillator frequency Programmable soft-start Power good indication 80 % maximum duty cycle with internal slope
compensation Supports both isolated and non-isolated
Applications. HTSSOP16 package
Applications VoIP phones, WLAN access points Security cameras PoE powered device appliances High power (>12.95 W) powered devices
DescriptionThe PM8800A integrates a standard power over
Ethernet (PoE) interface and a current mode
PWM controller to simplify the design of the
power supply sections of all powered devices.
The PoE interface incorporates all the functions
required by the IEEE 802.3af including detection,
classification, under-voltage lockout (UVLO) and
in-rush current limitation.
PM8800A specifically targets PD with extended
power requirement with respect to the limit
imposed by the 802.3af standard, embedding a
hot-swap MOSFET capable of sustaining twice
the current of the 802.3af standard with a
programmable DC current limit.
The integrated switching regulator has been
designed to work with power either form the
Ethernet cable connection or from an external
power source such as AC adapter.
The DC-DC section of the PM8800A features a
programmable oscillator frequency , soft-start,
slope compensation and embeds a voltage output
error amplifier allowing use in both isolated and
non isolated configuration.
Table 1. Device summary
Contents PM8800A2/35
Contents Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 41.1 Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 62.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PD interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.1 Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 Under voltage lock-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4 In rush current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5 Continuos current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.6 HV regulator startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7 Power good indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PWM section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1 Error amplifier and loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 Oscillator and sync capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4 PWM comparator / slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.5 Current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.6 Leading edge blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PM8800A Contents 3/35
Auxiliary sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328.1 HTSSOP16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Typical application circuit and block diagram PM8800A
4/35 Typical application circuit and block diagram
1.1 Application circuits
Figure 1. Simplified application schematic for powered devicesing PM8800A in isolated
configuration
Figure 2. Simplified application schematic for powered device using PM8800A in non-isolated
buck configuration
PM8800A Typical application circuit and block diagram
5/35
1.2 Block diagram
Figure 3. Block diagram of the PoE PD interface
Figure 4. Block diagram of the current mode PWM controller
Pins description and connection diagrams PM8800A
6/35 Pins description and connection diagrams
Figure 5. Pins connection (top view)
2.1 Pin descriptions
Table 2. Pin description
PM8800A Pins description and connection diagrams
7/35
Table 2. Pin description (continued)
Pins description and connection diagrams PM8800A
8/35
2.2 Thermal data
Table 3. Thermal data Package mounted on 4 layers 35 micron demoboard
PM8800A Electrical specifications
9/35
3 Electrical specifications
3.1 Absolute maximum ratings
Note: Absolute maximum ratings are limits beyond which damage to the device may occur.
Table 4. Absolute maximum ratings
Electrical specifications PM8800A
10/35
3.2 Electrical characteristic
Table 5. Electrical characteristics - interface section
(VIN = 48 V, VCC = open, TA = 25 °C unless otherwise specified).
PM8800A Electrical specifications
11/35
Table 5. Electrical characteristics - interface section (continued)
(VIN = 48 V, VCC = open, TA = 25 °C unless otherwise specified).
Electrical specifications PM8800A
12/35
Table 6. Electrical characteristics - SMPS section
(VIN = 48 V, VCC = open, TA = 25 °C unless otherwise specified).
PM8800A Electrical specifications
13/35
Note: 1 These values applies over the full operating temperarure range. Device thermal limitations could limit useful operating range.
3The VCC regulator is intended for internal use only as bias supply of PM8800A; any
additional external VCC current has to be limited within the specified max current limit.
Table 6. Electrical characteristics - SMPS section
(VIN = 48 V, VCC = open, TA = 25 °C unless otherwise specified).
Device description and operation PM8800A
14/35 Device description and operation
The PM8800A is a monolithic device embedding an IEEE 802.3af compliant PD interface
together with a current mode pulse width modulator to be used in all power over Ethernet
powered devices.
In addition to the standard.3af features, PM8800A anticipates some features of the forth-
coming.3at standard, specifically targeting appliances or systems requiring higher power
with respect to the 12.95 W allowed by standard PSE.
The PD interface integrates the 24.5 kΩ signature resistor used in detection and disabled
during the rest of operating modes. Classification is done through an external resistor
detached when classification is over, in order to save power.
The PM8800A integrates standard compliant UVLO thresholds to determine normal operat-
ing mode (UVLO rising) or recognize disconnection (UVLO falling).
A graphical representation of the voltage thresholds and hysteresis during all the operating
phases is depicted in the following figure:
Figure 6. State diagram of the PM8800A interface depending on the input voltage
For input voltages in the range 1.5 to 11.5 V, PM8800A exposes a 24.5 kΩ resistance. After
detection is over, the internal resistor is disabled and the external classification resistor is
presented. When classification is over, the external resistor is disconnected and the
PM8800A wait for the input voltage to overpass the UVLO voltage.
The hot-swap MOSFET is specifically designed to have a low R DSon to contain the conduc-
tion losses and sustain up to 800 mA. A constant dissipated power method is used to limit
the current in the in-rush phase. The integrated in-rush current limit controls in a safe man-
ner the current flowing through the MOSFET, shortening the duration of the hot-swap event
itself. Designers have the possibility to further limit the current in the in-rush by acting on the
proper programming resistor.
Designers have the possibility to set the limit of the current through the interface during nor-
mal operation. For non standard application, this limit exceeds the 350 mA foreseen by the
802.3af and can reach up to 800 mA.
PM8800A Device description and operation
15/35
PM8800A can work with power either from PoE networks or from auxiliary sources - like AC
adapters -. Alternative sources are present in PoE appliances where devices can work also
outside the context of the PoE networks or to ensure normal operation even if PoE becomes
unavailable. PM8800A limits the number of external components to handle the coexistence
of both PoE and auxiliary supplies.
External sources can be connected so to exploit the in-rush current limitation provided by
the MOSFET or enabling the PWM section, bypassing the interface section.
A state-of-the-art current mode pulse with modulator is embedded in the PM8800A to sup-
port low side single ended isolated and non isolated topologies. A high gain bandwidth prod-
uct error amplifier is embedded for non isolated configuration.
PM8800A has a 80 % maximum duty cycle, featuring embedded slope compensation.
The PWM switching frequency of PM8800A is programmable with an appropriate resistor
and it is also capable of working with an external clock reference.
PD interface PM8800A
16/35
5 PD interface
5.1 Detection
In power over Ethernet systems, the PSE senses the connection to detect whether an IEEE
802.3af compatible device is plugged to the cable termination by applying a small voltage
(2.7 to 10 V) on the Ethernet cable and measuring in two successive steps the equivalent
resistance. During this phase, the Powered Device must present a resistance between
23.75 kΩ and 26.25 kΩ
PM8800A integrates a 24.5 kΩ signature resistor to simplify the design of PoE powered
Device appliances and to reduce the overall component count.
Signature resistor is in series to a pass transistor (see Figure 7) used to disconnect the
resistor itself upon completion of the detection phase.
The value of the integrated detection resistance has been selected taking into account also
the diode bridges typical voltage drop.
During detection, most of the circuits inside the PM8800A are disabled to minimize the
offset current.
Figure 7. PM8800A: reference schematic of the integrated 24.5 kΩ and resistor
disable logic
PM8800A PD interface
17/35
5.2 Classification
Classification process in the IEEE 802.3af standard is optional for the powered device. This
feature allows PSE to plan and allocate the available power to the appliances connected to
the PoE network. IEEE 802.3af specification groups the need for power of the PD in 5
classes, one is reserved for future use. After successful detection, the PSE sets a constant
voltage between 15.5 V and 20.5 V for a maximum duration of 75 ms and senses the current
flowing through the cable to determine the PD's class.
The relevant thresholds in PM8800A are 11.5 V and 23 V, with a turn off hysteresis of 1.4 V.
To support the classification function, an equivalent programmable constant current
generator has been implemented. The following figure depicts a principle schematic of the
classification circuit. Just after the detection phase has been successfully completed, the
voltage of the RCLASS pin is set to the 1.4 V voltage reference and a pass transistor
connects the VIN pin to RCLASS pin.
Figure 8. PM8800A: reference schematic of the PoE classification logic
Classification resistor can be detached by three main causes: An auxiliary power source (front or rear) has been connected (see Section 7), The device is in thermal protection The classification has been successfully completed.
Designers can set the current by changing the value of the external resistor according to the
following table.
PD interface PM8800A
18/35
5.3 Under voltage lock-out
After the classification is completed, the PSE raises the voltage to provide the Power
Devices with the negotiated power. During the transition from low to operating voltage, the
internal UVLO is released and the hot-swap MOSFET is activated initiating the in-rush
sequence.
The IEEE 802.3af standard sets a maximum turn-on voltage (42 V) and the minimum turn-
off voltage (30 V) for the PDs and indicates normal voltage drops across the Ethernet cable.
The PM8800A implements the UVLO mechanism by setting 2 internal thresholds on the
voltage across the VIN-VSS pins; one is to activate the hot-swap (VUVLO_R), while the other
is to switch off the hot-swap MOSFET upon detection of a supply voltage drop (VUVLO_F)
from normal operating conditions.
No additional external components are required to comply with the IEEE 802.3af
requirements. Thermal protection alarm overrides the gate driving of the MOSFET
immediately switching off the MOSFET itself in case of device overheating. The hot-swap is
bypassed also in auxiliary source topology supplying directly the PWM and not requiring the
hot-swap to be active.
5.4 In rush current limit
Once the detection and classification phases have been successfully completed, the PSE
raises the voltage across the Ethernet cable. When the voltage difference between the VIN
and VSS is greater than the VUVLO_R threshold, the internal hot-swap MOSFET is switched
on and the DC-DC input capacitance is charged in a controlled way.
As depicted in the following figure, the current delivered by the hot-swap MOSFET during
inrush period is a function of the voltage drop between GND and VSS (hot-swap drain
source terminals). In more detail, the higher the voltage across the internal hot-swap, the
lower the current flowing trough it, so that the total dissipated power is almost constant
throughout the inrush phase, preventing the IC to reach the thermal protection limit.
The lower current limitation is internally set at 140 mA and takes action when the voltage
GND-VSS is above 30 V. The second limit is set at 250 mA when GND-VSS voltage is
between 30 V and 15 V. When the voltage falls below 15 V, the limit switches to the higher
Table 7. value of the external classification resistor for the different PD class of
power
