IC Phoenix
 
Home ›  PP22 > PHT6NQ10T,N-channel TrenchMOS standard level FET
PHT6NQ10T Fast Delivery,Good Price
Part Number:
If you need More Quantity or Better Price,Welcom Any inquiry.
We available via phone +865332716050 Email
Partno Mfg Dc Qty AvailableDescript
PHT6NQ10TNXPN/a35200avaiN-channel TrenchMOS standard level FET


PHT6NQ10T ,N-channel TrenchMOS standard level FETELECTRICAL CHARACTERISTICST= 25˚C unless otherwise specifiedjSYMBOL PARAMETER CONDITIONS MIN. TYP. ..
PHU108NQ03LT ,N-channel TrenchMOS(tm) logic level FET
PHU11NQ10T ,TrenchMOS(tm) standard level FET
PHU66NQ03LT ,PHP/PHU66NQ03LT; N-channel TrenchMOS(tm) logic level FET
PHU66NQ03LT ,PHP/PHU66NQ03LT; N-channel TrenchMOS(tm) logic level FET
PHU77NQ03T , N-channel TrenchMOS FET
PLSI1032-80LJ , High-Density Programmable Logic
PLSI1032-90LJ , High-Density Programmable Logic
PLSI1032-90LJ , High-Density Programmable Logic
PLT101 ,Transmitter module.{‘m‘m 4 - N E C ELECTRONICS INC 30E 1) " 13427535 C1l3ii!n8S'1 T " C-"ll-ert. 1:43-97- // ..
PLUS153BN ,Programmable logic arrays 18 ?42 ?10
PLUS153BN ,Programmable logic arrays 18 ?42 ?10


PHT6NQ10T
N-channel TrenchMOS standard level FET
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHT6NQ10T
FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology
• Low on-state resistance VDSS = 100 V
• Fast switching
• Low thermal resistance ID = 6.5 A
RDS(ON) ≤ 90 mΩ
GENERAL DESCRIPTION PINNING SOT223

N-channel enhancement mode PIN DESCRIPTION
field-effect transistorina plastic
envelope using ’trench’ 1 gate
technology. drain
Applications:-
Motor and relay drivers 3 source d.c.to d.c. converters drain (tab)
The PHT6NQ10Tis suppliedin the
SOT223 surface mounting
package.
LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDSS Drain-source voltage Tj = 25 ˚C to 150˚C - 100 V
VDGR Drain-gate voltage Tj = 25 ˚C to 150˚C; RGS = 20 kΩ - 100 V
VGS Gate-source voltage - ± 20 V Continuous drain current (dc) Tsp = 25 ˚C - 6.5 A
Tamb = 25 ˚C - 3 A Continuous drain current (dc) Tsp = 100 ˚C - 4.1 A
Tamb = 100 ˚C - 1.9 A
IDM Pulsed drain current - 26 A Total power dissipation Tsp = 25 ˚C - 8.3 W
Tamb = 25 ˚C - 1.8 W
Tj, Tstg Operating junction and - 65 150 ˚C
storage temperature
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

Rth j-sp Thermal resistance junction to surface mounted, FR4 12 15 K/W
solder point board th j-amb Thermal resistance junction to surface mounted, FR4 70 - K/W
ambient board 23
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHT6NQ10T
ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 100 - - V
voltage Tj = -55˚C 89 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 2 3 4 V
Tj = 150˚C 1.2 - - V
Tj = -55˚C - 6 V
RDS(ON) Drain-source on-state VGS = 10 V; ID = 3 A - 57 90 mΩ
resistance Tj = 150˚C - - 216 mΩ
IGSS Gate source leakage current VGS = ±10 V; VDS = 0 V - 10 100 nA
IDSS Zero gate voltage drain VDS = 100 V; VGS = 0 V; - 0.05 10 μA
current Tj = 150˚C - - 500 μA
Qg(tot) Total gate charge ID = 6 A; VDD = 80 V; VGS = 10 V - 21 - nC
Qgs Gate-source charge - 2.5 - nC
Qgd Gate-drain (Miller) charge - 8.2 - nC
td on Turn-on delay time VDD = 50 V; RD = 8.2 Ω;- 6 - ns Turn-on rise time VGS = 10 V; RG = 5.6 Ω -15 - ns
td off Turn-off delay time Resistive load - 20 - ns Turn-off fall time - 10 - ns Internal drain inductance Measured tab to centre of die - 2.5 - nH Internal source inductance Measured from source lead to source - 5 - nH
bond pad
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 633 - pF
Coss Output capacitance - 103 - pF
Crss Feedback capacitance - 61 - pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Continuous source current Tsp = 25 ˚C - - 5.5 A
(body diode)
ISM Pulsed source current (body - - 26 A
diode)
VSD Diode forward voltage IF = 6 A; VGS = 0 V - 0.8 1.2 V
trr Reverse recovery time IF = 6 A; -dIF/dt = 100 A/μs; - 55 - ns
Qrr Reverse recovery charge VGS = 0 V; VR = 25 V - 135 - nC
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHT6NQ10T
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tsp)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tsp); VGS ≥ 10 V
Fig.3. Safe operating area
Fig.4. Transient thermal impedance.
Zth j-sp = f(t); parameter D = tp/T
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS)
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
Normalised Power Derating, PD (%)
100 25 50 75 100 125 150
Solder Point temperature, Tsp (C)
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
Pulse width, tp (s)
Transient thermal impedance, Zth j-sp (K/W)
Normalised Current Derating, ID (%)
100 25 50 75 100 125 150
Solder Point temperature, Tsp (C) 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Drain-Source Voltage, VDS (V)
100 10 100 1000
Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
012 3456
Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHT6NQ10T
Fig.7. Typical transfer characteristics.
ID = f(VGS)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
Fig.9. Normalised drain-source on-state resistance.
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.12. Typical capacitances, Ciss, Coss, Crss. 234 56
Gate-source voltage, VGS (V)
Threshold Voltage, VGS(TO) (V)
-60 -40 -200 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
Drain current, ID (A)
Transconductance, gfs (S)
Drain current, ID (A)
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Gate-source voltage, VGS (V)
Normalised On-state Resistance
-60 -40 -200 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
0.1 1 10 100
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHT6NQ10T
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj2468 1012 1416 1820 2224 262830
Gate charge, QG (nC)
Gate-source voltage, VGS (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.91 1.1 1.2
Source-Drain Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHT6NQ10T
MECHANICAL DATA

Fig.15. SOT223 surface mounting package.
Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to Discrete Semiconductor Packages, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
Plastic surface mounted package; collector pad for good heat transfer; 4 leads SOT223
ic,good price


TEL:86-533-2716050      FAX:86-533-2716790
   

©2020 IC PHOENIX CO.,LIMITED