PHT6N06 ,TrenchMOS transistor Standard level FETLIMITING VALUES AND CHARACTERISTICST = -55 to 175˚C unless otherwise specifiedjSYMBOL PARAMETER CON ..
PHT6N06 ,TrenchMOS transistor Standard level FETGENERAL DESCRIPTION QUICK REFERENCE DATAN-channel enhancement mode SYMBOL PARAMETER MAX. UNITlogic ..
PHT6N06LT ,N-channel TrenchMOS logic level FET
PHT6N06LT ,N-channel TrenchMOS logic level FETLIMITING VALUESYMBOL PARAMETER CONDITIONS MIN. MAX. UNITV Electrostatic discharge capacitor Human b ..
PHT6N06T ,TrenchMOS transistor Standard level FETLIMITING VALUESYMBOL PARAMETER CONDITIONS MIN. MAX. UNITV Electrostatic discharge capacitor Human b ..
PHT6NQ10T ,N-channel TrenchMOS standard level FETELECTRICAL CHARACTERISTICST= 25˚C unless otherwise specifiedjSYMBOL PARAMETER CONDITIONS MIN. TYP. ..
PLSI1032-80LJ , High-Density Programmable Logic
PLSI1032-90LJ , High-Density Programmable Logic
PLSI1032-90LJ , High-Density Programmable Logic
PLT101 ,Transmitter module.{‘m‘m
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PLUS153BN ,Programmable logic arrays 18 ?42 ?10
PLUS153BN ,Programmable logic arrays 18 ?42 ?10
PHT6N06-PHT6N06T
TrenchMOS transistor Standard level FET
Philips Semiconductors Product specification
TrenchMOS transistor PHT6N06T
Standard level FET
GENERAL DESCRIPTION QUICK REFERENCE DATAN-channel enhancement mode
SYMBOL PARAMETER MAX. UNITlogic level field-effect power
transistorina plastic envelope VDS Drain-source voltage 55 V
suitable for surface mounting. ID Drain current (DC) Tsp = 25 ˚C 5.5 A
Using
’trench’ technology the Drain current (DC) Tamb = 25 ˚C 2.5 A
device features very low Ptot Total power dissipation 8.3 W
on-state resistance and has Tj Junction temperature 150 ˚C
integral zener diodes giving RDS(ON) Drain-source on-state 150 mΩ
ESDprotection.It isintendedfor resistance VGS = 10 V
usein DC-DC converters and
general purpose switching
applications.
PINNING - SOT223 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION gate drain source drain (tab)
LIMITING VALUESLimiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNITVDS Drain-source voltage - - 55 V
VDGR Drain-gate voltage RGS = 20 kΩ -55 V
±VGS Gate-source voltage - - 20 V Drain current (DC) Tsp = 25 ˚C - 5.5 A
Tamb = 25 ˚C - 2.5 A Drain current (DC) Tsp = 100 ˚C - 3.8 A
Tamb = 100 ˚C - 1.75 A
IDM Drain current (pulse peak value) Tsp = 25 ˚C - 22 A
Tamb = 25 ˚C - 10 A
Ptot Total power dissipation Tsp = 25 ˚C - 8.3 W
Tamb = 25 ˚C - 1.8 W
Tstg, Tj Storage & operating temperature - - 55 150 ˚C
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Electrostatic discharge capacitor Human body model - 2 kV
voltage (100 pF, 1.5 kΩ)
Philips Semiconductors Product specification
TrenchMOS transistor PHT6N06T
Standard level FET
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNITRth j-sp From junction to solder point Mounted on any PCB 12 15 K/W
Rth j-amb From junction to ambient Mounted on PCB of Fig.19 - 70 K/W
STATIC CHARACTERISTICSTj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITV(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA 55 - - V
voltage Tj = -55˚C 50 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 2.0 3.0 4.0 V
Tj = 150˚C 1.2 - - Vj = -55˚C - - 4.4 VDSS Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 μA
Tj = 150˚C - - 100 μA
IGSS Gate source leakage current VGS = ±10 V - 0.04 1 μA
Tj = 150˚C - - 10 μA
±V(BR)GSS Gate source breakdown voltage IG = ±1 mA 16 - - V DS(ON) Drain-source on-state VGS = 10 V; ID = 5 A - 120 150 mΩ
resistance Tj = 150˚C - - 277 mΩ
DYNAMIC CHARACTERISTICSmb = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITgfs Forward transconductance VDS = 25 V; ID = 5 A; Tj = 25˚C 0.5 2.5 - S
Qg(tot) Total gate charge ID = 5 A; VDD = 44 V; VGS = 10 V - 6 - nC
Qgs Gate-source charge - 1.5 - nC
Qgd Gate-drain (Miller) charge - 4 - nC
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 190 240 pF
Coss Output capacitance - 65 80 pFrss Feedback capacitance - 32 45 pF
td on Turn-on delay time VDD = 30 V; ID = 5 A; - 9 14 ns Turn-on rise time VGS = 10 V; RG = 10 Ω; - 28 42 ns
td off Turn-off delay time - 15 23 ns Turn-off fall time Tj = 25˚C - 8 12 ns
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICSTj = -55 to 175˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITIDR Continuous reverse drain Tsp = 25˚C - - 5.5 A
current
IDRM Pulsed reverse drain current Tsp = 25˚C - - 30 A
VSD Diode forward voltage IF = 2 A; VGS = 0 V - 0.85 1.1 V
trr Reverse recovery time IF = 2 A; -dIF/dt = 100 A/μs; - 43 - ns
Qrr Reverse recovery charge VGS = -10 V; VR = 30 V - 0.16 - μC
Philips Semiconductors Product specification
TrenchMOS transistor PHT6N06T
Standard level FET
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITWDSS Drain-source non-repetitive ID = 1.9 A; VDD ≤ 25 V; - - 15 mJ
unclamped inductive turn-off VGS = 10 V; RGS = 50 Ω; Tsp = 25 ˚C
energy
Philips Semiconductors Product specification
TrenchMOS transistor PHT6N06T
Standard level FETFig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tsp)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tsp); conditions: VGS ≥ 10 V
Fig.3. Safe operating area. Tsp = 25 ˚C
Fig.4. Transient thermal impedance.
Zth j-sp = f(t); parameter D = tp/T
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Fig.6. Typical on-state resistance, Tj = 25 ˚C. 20 40 60 80 100 120 140
Tmb / C
PD% Normalised Power Derating120
110
100
90
80
70
60
50
40
30
20
10
1E-07 1E-05 1E-03 1E-01 1E+01
t / s
Zth / (K/W)1E+02
3E+01
1E+01
3E+00
1E+00
3E-01
1E-01
3E-02
1E-02 20 40 60 80 100 120 140
Tmb / C
ID% Normalised Current Derating120
110
100
90
80
70
60
50
40
30
20
10 468 100ID/A
VDS/V
ID/A
110 55
RDS(ON) = VDS/ID
012 34567 89 10 110
ID/A
Philips Semiconductors Product specification
TrenchMOS transistor PHT6N06T
Standard level FETFig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Fig.9. Normalised drain-source on-state resistance.
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.12. Typical capacitances, Ciss, Coss, Crss.
ID/A
VGS/V
-100 -50 0 50 100 150 2000
Tj / C
123456 789 10
gfs/S
ID/A 01 23 451E-06
1E-05
1E-04
1E-03
1E-02
1E-01 Sub-Threshold Conduction
-100 -50 0 50 100 150 200
Tmb / degC
Rds(on) normalised to 25degCa
0.01 0.1 1 10 100
Ciss
Coss
Crss
VDS/V
Philips Semiconductors Product specification
TrenchMOS transistor PHT6N06T
Standard level FETFig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 5 A; parameter VDS
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tsp); conditions: ID = 1.9 A
Fig.16. Avalanche energy test circuit.
Fig.17. Switching test circuit. 1 2345670
VGS/V
QG/nC 40 60 80 100 120 140
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
WDSS% 0.2 0.4 0.6 0.8 1 1.2 1.40
IF/A
VSDS/V
T.U.T.
VDD
VGSDSS=0.5 ⋅LID⋅BVDSS /(BVDSS −VDD)
VDDVGS
