PHP36N03LT ,N-channel TrenchMOS logic level FETPHP36N03LTN-channel TrenchMOS logic level FETRev. 04 — 8 July 2010 Product data sheet1. Product pro ..
PHP36N06E ,PowerMOS transistor
PHP3N20E ,PowerMOS transistor
PHP3N50 ,PowerMOS transistor
PHP42N03LT ,TrenchMOS transistor Logic level FET
PHP45N03LT ,TrenchMOS transistor Logic level FET
PLS159AA ,Programmable logic sequencer 16 ?45 ?12
PLS159AA ,Programmable logic sequencer 16 ?45 ?12
PLS173A ,Programmable logic array 22 ?42 ?10
PLS173A ,Programmable logic array 22 ?42 ?10
PLSI1032-80LJ , High-Density Programmable Logic
PLSI1032-90LJ , High-Density Programmable Logic
PHP36N03LT
N-channel TrenchMOS logic level FET
PHP36N03LT
N-channel TrenchMOS logic level FET
Rev. 04 — 8 July 2010 Product data sheet Product profile
1.1 General descriptionLogic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits Simple gate drive required due to low
gate charge Suitable for logic level gate drive
sources
1.3 Applications DC-to-DC convertors Switched-mode power supplies
1.4 Quick reference data Table 1. Quick reference dataVDS drain-source
voltage≥25 °C; Tj≤ 175°C --30 V drain current Tmb =25°C; VGS =10V;
see Figure 1; see Figure 3
--43.4 A
Ptot total power
dissipation
Tmb=25 °C; see Figure 2 --57.6 W
Static characteristicsRDSon drain-source
on-state
resistance
VGS =10V; ID =25A; =25°C; see Figure 9;
see Figure 10 1417mΩ
Dynamic characteristicsQGD gate-drain charge VGS =10V; ID =36A;
VDS =15 V; Tj =25°C;
see Figure 11; see Figure 12
-2.9 -nC
NXP Semiconductors PHP36N03LT
N-channel TrenchMOS logic level FET Pinning information[1] It is not possible to make a connection to pin 2.
Ordering information
Table 2. Pinning information
Table 3. Ordering informationPHP36N03LT TO-220AB plastic single-ended package; heatsink mounted; 1 mounting
hole; 3-lead TO-220AB
SOT78
NXP Semiconductors PHP36N03LT
N-channel TrenchMOS logic level FET Limiting values
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage Tj≥25 °C; Tj≤ 175°C - 30 V
VDGR drain-gate voltage Tj≥25 °C; Tj≤ 175 °C; RGS =20kΩ -30 V
VGS gate-source voltage -20 20 V drain current VGS =10V; Tmb= 100 °C; see Figure 1 - 30.7 A
VGS =10V; Tmb =25°C; see Figure 1;
see Figure 3 43.4 A
IDM peak drain current pulsed; tp≤10 µs; Tmb =25°C;
see Figure 3 173.6 A
Ptot total power dissipation Tmb =25°C; see Figure 2 - 57.6 W
Tstg storage temperature -55 175 °C junction temperature -55 175 °C
Source-drain diode source current Tmb=25°C - 43.4 A
ISM peak source current pulsed; tp≤10 µs; Tmb=25°C - 173.6 A
NXP Semiconductors PHP36N03LT
N-channel TrenchMOS logic level FET Thermal characteristics
Table 5. Thermal characteristicsRth(j-mb) thermal resistance from junction to
mounting base
see Figure 4 --2.6 K/W
Rth(j-a) thermal resistance
from junction to
ambient
vertical in free air - 60 - K/W
NXP Semiconductors PHP36N03LT
N-channel TrenchMOS logic level FET Characteristics
Table 6. Characteristics
Static characteristicsV(BR)DSS drain-source
breakdown voltage =250 µA; VGS =0V; Tj= -55°C 27 - - V =250 µA; VGS =0V; Tj=25°C 30 --V
VGS(th) gate-source threshold
voltage =250 µA; VDS =VGS; Tj= 175 °C;
see Figure 7; see Figure 8
0.5 --V =250 µA; VDS =VGS; Tj =25°C;
see Figure 7; see Figure 8
11.5 2V =250 µA; VDS =VGS; Tj =-55 °C;
see Figure 7; see Figure 8
--2.2 V
IDSS drain leakage current VDS =24V; VGS =0V; Tj=25°C - 0.05 1 µA
VDS =24V; VGS =0V; Tj= 175°C - - 500 µA
IGSS gate leakage current VGS =20V; VDS =0V; Tj=25°C - 10 100 nA
VGS =-20 V; VDS =0V; Tj=25°C - 10 100 nA
RDSon drain-source on-state
resistance
VGS =10V; ID =25A; Tj =25°C;
see Figure 9; see Figure 10 1417mΩ
VGS =4.5 V; ID =12A; Tj =175 °C;
see Figure 9; see Figure 10 32.4 39.6 mΩ
VGS =3.5 V; ID= 5.2 A; Tj =25°C;
see Figure 9; see Figure 10 2240mΩ
VGS =4.5 V; ID =12A; Tj =25°C;
see Figure 9; see Figure 10 1822mΩ
Dynamic characteristicsQG(tot) total gate charge ID =36A; VDS =15V; VGS =10V; =25°C; see Figure 11; see Figure 12 18.5 - nC
QGS gate-source charge - 4.2 - nC
QGD gate-drain charge - 2.9 - nC
Ciss input capacitance VDS =25V; VGS=0 V; f=1 MHz; =25°C; see Figure 13 690 - pF
Coss output capacitance VDS =0V; VGS =0V; f=1MHz; =25°C; see Figure 13 160 - pF
Crss reverse transfer
capacitance
VDS =25V; VGS=0 V; f=1 MHz; =25°C; see Figure 13
-110 -pF
td(on) turn-on delay time VDS =15V; RL =0.6 Ω; VGS =10V;
RG(ext) =10 Ω; Tj =25°C -ns rise time - 10 - ns
td(off) turn-off delay time - 33 - ns fall time - 19 - ns
Source-drain diodeVSD source-drain voltage IS =25A; VGS =0V; Tj =25°C;
see Figure 14 0.97 1.2 V
NXP Semiconductors PHP36N03LT
N-channel TrenchMOS logic level FET
NXP Semiconductors PHP36N03LT
N-channel TrenchMOS logic level FET