PHP225 ,Dual P-channel intermediate level FETGeneral descriptionDual intermediate level P-channel enhancement mode Field-Effect Transistor (FET) ..
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PHP225
Dual P-channel intermediate level FET
Product profile1.1 General descriptionDual intermediate level P-channel enhancement mode Field-Effect Transistor (FET) in a
plastic package using vertical D-MOS technology. This product is designed and qualified
for use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits Low conduction losses due to low
on-state resistance Suitable for high frequency
applications due to fast switching
characteristics
1.3 Applications Motor and actuator drivers Power management Synchronized rectification
1.4 Quick reference data[1] Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 2 W at the same
time.
PHP225
Dual P-channel intermediate level FET
Rev. 04 — 17 March 2011 Product data sheet
Table 1. Quick reference dataVDS drain-source voltage Tj≥25 °C; Tj≤ 150°C ---30 V drain current Tsp≤80°C ---2.3 A
Ptot total power dissipation Tsp =80°C [1] --2 W
Static characteristicsRDSon drain-source on-state
resistance
VGS =-10 V; ID =-1A; =25°C 0.22 0.25 Ω
Dynamic characteristicsQGD gate-drain charge VGS =-10 V; ID =-2.3A;
VDS =-15 V; Tj =25°C -nC
NXP Semiconductors PHP225
Dual P-channel intermediate level FET Pinning information Ordering information
Table 2. Pinning information1S1 source1
SOT96-1 (SO8) G1 gate1
3S2 source2 G2 gate2
5D2 drain2
6D2 drain2
7D1 drain1
8D1 drain1
Table 3. Ordering informationPHP225 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
NXP Semiconductors PHP225
Dual P-channel intermediate level FET Limiting values[1] Pulse width and duty cycle limited by maximum junction temperature.
[2] Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with a thermal resistance from ambient to
tie-point of 90 K/W.
[3] Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 2 W at the same time.
[4] Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted on printed-circuit board with a thermal
resistance from ambient to tie-point of 90 K/W.
[5] Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with a thermal resistance from ambient to
tie-point of 27.5 K/W.
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage Tj≥25 °C; Tj≤ 150°C - -30 V
VGS gate-source voltage - - V
VGSO gate-source voltage open drain -20 20 V drain current Tsp≤80°C - -2.3 A
IDM peak drain current Tsp=25 °C; pulsed [1] --10 A
Ptot total power dissipation Tamb =25°C [2] -1 W
Tsp =80°C [3] -2 W
Tamb =25°C [4] -1.3 W
[5] -2 W
Tstg storage temperature -65 150 °C junction temperature - 150 °C
Source-drain diode source current Tsp≤80°C - -1.25 A
ISM peak source current Tsp=25 °C; pulsed [1] --5 A
NXP Semiconductors PHP225
Dual P-channel intermediate level FET Thermal characteristics
Table 5. Thermal characteristicsRth(j-sp) thermal resistance from junction to
solder point
see Figure 3 --35 K/W
NXP Semiconductors PHP225
Dual P-channel intermediate level FET Characteristics
Table 6. Characteristics
Static characteristicsV(BR)DSS drain-source breakdown
voltage= -10 µA; VGS =0V; Tj=25°C -30 --V
VGS(th) gate-source threshold
voltage =-1 mA; VDS =VGS; Tj =25°C -1 - -2.8 V
IDSS drain leakage current VDS =-24 V; VGS =0V; Tj=25°C - - -100 nA
IGSS gate leakage current VGS =20V; VDS =0V; Tj=25°C - - 100 nA
VGS =-20 V; VDS =0V; Tj=25°C - - 100 nA
RDSon drain-source on-state
resistance
VGS =-10 V; ID =-1 A; Tj=25°C - 0.22 0.25 Ω
VGS =-4.5V; ID =-0.5A; Tj=25°C - 0.33 0.4 Ω
IDSon on-state drain current VDS =-1V; VGS= -10V -2.3 --A
VDS =-5V; VGS= -4.5V -1 --A
Dynamic characteristicsQG(tot) total gate charge ID =-2.3A; VDS =-15 V; VGS =-10V; =25°C 1025nC
QGS gate-source charge - 1 - nC
QGD gate-drain charge - 3 - nC
Ciss input capacitance VDS =-20 V; VGS=0 V; f=1 MHz; =25°C 250 - pF
Coss output capacitance - 140 - pF
Crss reverse transfer
capacitance
-50 - pF
gfs transfer conductance VDS =-20 V; ID =-1A; Tj=25°C 12- S
toff turn-off time VDS =-20 V; VGS =-10 V; RG(ext) =4.7Ω; =20 Ω; Tj =25°C; ID =-1A 50 140 ns
ton turn-on time - 20 80 ns
Source-drain diodeVSD source-drain voltage IS= -1.25 A; VGS =0V; Tj=25°C ---1.6 V
trr reverse recovery time IS= -1.25 A; dIS/dt= 100 A/µs;
VGS =0V; VDS =25 V; Tj =25°C 150 200 ns
NXP Semiconductors PHP225
Dual P-channel intermediate level FET
