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PHN210T
Dual N-channel TrenchMOS intermediate level FET
Product profile1.1 General descriptionDual intermediate level N-channel enhancement mode Field-Effect Transistor (FET) in a
plastic package using TrenchMOS technology. This product is designed and qualified for
use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits Suitable for high frequency
applications due to fast switching
characteristics Suitable for logic level gate drive
sources Suitable for low gate drive sources
1.3 Applications DC-to-DC converters Logic level translators Motor and relay drivers
1.4 Quick reference data[1] Surface mounted on FR4 board, t ≤ 10 sec.
[2] Surface mounted on FR4, t ≤ 10 sec.
PHN210T
Dual N-channel TrenchMOS intermediate level FET
Rev. 02 — 15 December 2010 Product data sheet
Table 1. Quick reference dataVDS drain-source
voltage≥25 °C; Tj≤ 150 °C;
Repetitive peak drain-source
voltage
--30 V drain current Tsp=25 °C; Single device [1] --3.4 A
Ptot total power
dissipation
Tsp =25°C [2] --2 W
Static characteristicsRDSon drain-source
on-state
resistance
VGS =4.5 V; ID =1A; =25°C
-120 200 mΩ
VGS =10V; ID =2.2A; =25°C
-80 100 mΩ
Dynamic characteristicsQGD gate-drain charge VGS =10V; ID =2.3A;
VDS =15 V; Tj =25°C
-0.7 -nC
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET Pinning information Ordering information
Table 2. Pinning information
Table 3. Ordering informationPHN210T SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET Limiting values[1] Surface mounted on FR4 board, t ≤ 10 sec.
[2] Surface mounted on FR4, t ≤ 10 sec.
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage Continuous - 30 V≥25 °C; Tj≤ 150 °C; Repetitive peak
drain-source voltage
-30 V
VDGR drain-gate voltage RGS =20kΩ -30 V
VGS gate-source voltage -20 20 V drain current Tsp=70 °C; Dual device [1] -1.9 A
Tsp=70 °C; Single device [1] -2.8 A
Tsp=25 °C; Dual device [1] -2.4 A
Tsp=25 °C; Single device [1] -3.4 A
IDM peak drain current Tsp=25 °C; pulsed - 14 A
Ptot total power dissipation Tsp =25°C [2] -2 W
Tstg storage temperature -65 150 °C junction temperature -65 150 °C
Source-drain diode source current Tsp =25°C - 2.2 A
ISM peak source current Tsp=25 °C; pulsed - 14 A
Avalanche ruggednessEDS(AL)S non-repetitive drain-source
avalanche energy
VGS =10V; Tj(init) =25°C; ID =3.4A;
VDD≤15 V; unclamped; RGS =50Ω; =0.2ms
-13 mJ
IAS non-repetitive avalanche
current
Vsup≤15 V; VGS =10 V; Tj(init) =25°C;
RGS =50 Ω; unclamped
-3.4 A
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FETNXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET Thermal characteristics
Table 5. Thermal characteristicsRth(j-a) thermal resistance
from junction to
ambient
Surface mounted; FR4 board - 150 - K/W
Surface mounted; FR4 board;
t ≤ 10 sec - 62.5 K/W
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET Characteristics
Table 6. Characteristics
Static characteristicsV(BR)DSS drain-source
breakdown voltage =10µA; VGS =0V; Tj=25°C 30 --V =10µA; VGS =0V; Tj= -55°C 27 - - V
VGS(th) gate-source threshold
voltage =1mA; VDS =VGS; Tj= -55°C --3.2 V =1mA; VDS =VGS; Tj= 150°C 0.4 - - V =1mA; VDS =VGS; Tj=25°C 122.8 V
IDSS drain leakage current VDS =24V; VGS =0V; Tj=25°C - 10 100 nA
VDS =24V; VGS =0V; Tj= 150°C - 0.6 10 µA
IGSS gate leakage current VGS =20V; VDS =0V; Tj=25°C - 10 100 nA
VGS =-20 V; VDS =0V; Tj=25°C - 10 100 nA
RDSon drain-source on-state
resistance
VGS =4.5 V; ID =1A; Tj=25°C - 120 200 mΩ
VGS =10V; ID =2.2 A; Tj= 150°C - - 170 mΩ
VGS =10V; ID =2.2 A; Tj=25°C - 80 100 mΩ
IDSon on-state drain current VDS =1V; VGS=10V 3.5 --A
VDS =5V; VGS= 4.5V 2 --A
Dynamic characteristicsQG(tot) total gate charge ID =2.3 A; VDS =15V; VGS =10V; =25°C -nC
QGS gate-source charge - 0.7 - nC
QGD gate-drain charge - 0.7 - nC
Ciss input capacitance VDS =20V; VGS=0 V; f=1 MHz; =25°C 250 - pF
Coss output capacitance - 88 - pF
Crss reverse transfer
capacitance
-54 -pF
td(on) turn-on delay time VDS =20V; RL =18 Ω; VGS =10V;
RG(ext) =6 Ω; Tj =25°C -ns rise time - 8 - ns
td(off) turn-off delay time - 21 - ns fall time - 15 - ns
gfs transfer conductance VDS =20V; ID= 2.2 A; Tj =25°C 2 4.5 - S internal drain
inductance
measured from drain lead to centre of
die; Tj =25°C
-2.5 -nH internal source
inductance
measured from source lead to source
bond pad; Tj =25°C -nH
Source-drain diodeVSD source-drain voltage IS= 1.25 A; VGS =0V; Tj=25°C - 0.82 1.2 V
trr reverse recovery time IS= 1.25 A; dIS/dt= -100 A/µs;
VGS =0V; VDS =25V; Tj =25°C
-69 -ns recovered charge - 55 - nC
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET
