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PHD97NQ03LT
N-channel TrenchMOS logic level FET
PHD97NQ03LT
N-channel TrenchMOS logic level FET
Rev. 01 — 24 March 2009 Product data sheet Product profile
1.1 General descriptionLogic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits Fast switching Lead-free packing Logic level threshold Low on-state resistance Suitable for high frequency
applications due to fast switching
characteristics
1.3 Applications Computer motherboard high
frequency DC-to-DC convertors Switched-mode power supplies Voltage regulators
1.4 Quick reference data Table 1. Quick referenceVDS drain-source voltage Tj≥25 °C; Tj≤ 175°C - - 25 V drain current Tmb =25°C; VGS =10V;
see Figure 1; see Figure 3
--75 A
Ptot total power
dissipation
Tmb=25 °C; see Figure 2 - - 107 W
Dynamic characteristicsQGD gate-drain charge VGS= 4.5 V; ID =25A;
VDS=12 V; see Figure 9;
see Figure 10
-1.9 -nC
Static characteristicsRDSon drain-source
on-state resistance
VGS =10V; ID =25A; =25 °C; see Figure 7;
see Figure 8
-5.3 6.3 mΩ
NXP Semiconductors PHD97NQ03LT
N-channel TrenchMOS logic level FET Pinning information Ordering information Limiting values
Table 2. Pinning information gate
SOT428
(SC-63; DPAK) drain source D mounting base; connected to
drain
Table 3. Ordering informationPHD97NQ03LT SC-63; DPAK plastic single-ended surface-mounted package (DPAK); 3 leads
(one lead cropped)
SOT428
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage Tj≥25 °C; Tj≤ 175°C - 25 V
VDGR drain-gate voltage Tj≥25 °C; Tj≤ 175 °C; RGS =20kΩ -25 V
VGS gate-source voltage -20 20 V drain current VGS =10V; Tmb= 100 °C; see Figure 1 -69 A
VGS =10V; Tmb =25°C; see Figure 1; see Figure 3 -75 A
IDM peak drain current tp≤10 µs; pulsed; Tmb =25°C; see Figure 3 -300 A
Ptot total power dissipation Tmb =25°C; see Figure 2 -107 W
Tstg storage temperature -55 175 °C junction temperature -55 175 °C
Source-drain diode source current Tmb =25°C - 75 A
ISM peak source current tp≤10 µs; pulsed; Tmb =25°C - 240 A
Avalanche ruggednessEDS(AL)S non-repetitive
drain-source avalanche
energy
VGS =10V; Tj(init) =25°C; ID =35A; Vsup≤25V;
unclamped; tp =0.1 ms; RGS =50Ω
-60 mJ
NXP Semiconductors PHD97NQ03LT
N-channel TrenchMOS logic level FET
NXP Semiconductors PHD97NQ03LT
N-channel TrenchMOS logic level FET Thermal characteristics[1] Mounted on a printed-circuit board; vertical in still air
Table 5. Thermal characteristicsRth(j-mb) thermal resistance from junction to
mounting base
see Figure 4 --1.4 K/W
Rth(j-a) thermal resistance from junction to
ambient
minimum footprint [1] -75 - K/W
NXP Semiconductors PHD97NQ03LT
N-channel TrenchMOS logic level FET CharacteristicsTable 6. Characteristics
Static characteristicsV(BR)DSS drain-source
breakdown voltage =250 µA; VGS =0V; Tj =25°C 25 - - V =250 µA; VGS =0V; Tj =-55°C 22 - - V
VGS(th) gate-source threshold
voltage =1mA; VDS = VGS; Tj =25°C;
see Figure 5; see Figure 6
1.3 1.7 2.15 V =1mA; VDS = VGS; Tj= 175 °C;
see Figure 5
0.7 - - V =1mA; VDS = VGS; Tj =-55 °C;
see Figure 5
--2.6 V
IDSS drain leakage current VDS =25V; VGS =0V; Tj=25°C --1 µA
IGSS gate leakage current VGS =16V; VDS =0V; Tj=25°C - - 100 nA
VGS =-16 V; VDS =0V; Tj=25°C - - 100 nA
RDSon drain-source on-state
resistance
VGS =10V; ID =25A; Tj= 175 °C;
see Figure 7; see Figure 8 10.1 12 mΩ
VGS =4.5 V; ID =25A; Tj =25°C;
see Figure 7; see Figure 8 10.6 mΩ
VGS =10V; ID =25A; Tj =25°C;
see Figure 7; see Figure 8
-5.3 6.3 mΩ
IDSS drain leakage current VDS =25V; VGS =0V; Tj= 175°C - - 100 µA gate resistance f=1 MHz - 1.5 - Ω
Dynamic characteristicsQG(tot) total gate charge ID =25A; VDS =12V; VGS =4.5V;
see Figure 9; see Figure 10
-11.7 - nC =0A; VDS =0V; VGS= 4.5V - 10.2 - nC
QGS gate-source charge ID =25A; VDS =12V; VGS =4.5V;
see Figure 9; see Figure 10
-6.2 - nC
QGS1 pre-threshold
gate-source charge
-3.4 - nC
QGS2 post-threshold
gate-source charge
-2.8 - nC
QGD gate-drain charge - 1.9 - nC
VGS(pl) gate-source plateau
voltage =25A; VDS =12V; see Figure 9; see
Figure 10
-3.1 - V
Ciss input capacitance VDS =12V; VGS=0 V; f=1 MHz; =25°C; see Figure 11 1570 - pF
VDS =0V; VGS =0V; f=1MHz; =25°C 1800 - pF
Coss output capacitance VDS =12V; VGS=0 V; f=1 MHz; =25°C; see Figure 11 380 - pF
Crss reverse transfer
capacitance 160 - pF
NXP Semiconductors PHD97NQ03LT
N-channel TrenchMOS logic level FETtd(on) turn-on delay time VDS =12V; RL =0.5 Ω; VGS =4.5V;
RG(ext) =5.6Ω
-18 - ns rise time - 33 - ns
td(off) turn-off delay time - 20 - ns fall time - 12 - ns
Source-drain diodeVSD source-drain voltage IS =25A; VGS =0V; Tj =25°C;
see Figure 12 0.87 1.2 V
trr reverse recovery time IS =20A; dIS/dt= -100 A/µs; VGS =0V;
VDS =30V
-38 - ns recovered charge - 14 - nC
Table 6. Characteristics …continued
