PHD71NQ03LT ,N-channel TrenchMOS logic level FETGeneral descriptionLogic level N-channel enhancement mode Field-Effect Transistor (FET) in a plasti ..
PHD71NQ03LT ,N-channel TrenchMOS logic level FETApplications DC-to-DC convertors Switched-mode power supplies1.4 Quick reference data Table 1. Qu ..
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PHD71NQ03LT
N-channel TrenchMOS logic level FET
PHD71NQ03LT
N-channel TrenchMOS logic level FET
Rev. 02 — 9 March 2010 Product data sheet Product profile
1.1 General descriptionLogic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits Simple gate drive required due to low
gate charge Suitable for logic level gate drive
sources
1.3 Applications DC-to-DC convertors Switched-mode power supplies
1.4 Quick reference data Table 1. Quick referenceVDS drain-source voltage Tj≥25 °C; Tj≤ 175°C - - 30 V drain current Tmb =25°C; VGS =10V;
see Figure 1 and 3
--75 A
Ptot total power dissipation Tmb=25 °C; see Figure 2 - - 120 W
Dynamic characteristicsQGD gate-drain charge VGS =5V; ID =50A;
VDS =15V; Tj =25°C;
see Figure 11
-4.6 -nC
Static characteristicsRDSon drain-source on-state
resistance
VGS =10V; ID =25A; =25 °C; see Figure 9 10 mΩ
NXP Semiconductors PHD71NQ03LT
N-channel TrenchMOS logic level FET Pinning information[1] It is not possible to make a connection to pin 2.
Ordering information Limiting values
Table 2. Pinning information gate
SOT428 (DPAK) drain [1] source D mounting base; connected to
drain
Table 3. Ordering informationPHD71NQ03LT DPAK plastic single-ended surface-mounted package (DPAK); 3 leads (one
lead cropped)
SOT428
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage Tj≥25 °C; Tj≤ 175°C - 30 V
VDGR drain-gate voltage Tj≥25 °C; Tj≤ 175 °C; RGS =20kΩ -30 V
VGS gate-source voltage -20 20 V drain current VGS =10V; Tmb= 100 °C; see Figure 1 -57.5 A
VGS =10V; Tmb =25°C; see Figure 1 and 3 -75 A
IDM peak drain current tp≤10 µs; pulsed; Tmb =25°C; see Figure 3 -240 A
Ptot total power dissipation Tmb =25°C; see Figure 2 -120 W
Tstg storage temperature -55 175 °C junction temperature -55 175 °C
VGSM peak gate-source
voltage
pulsed; δ =25%; tp≤50µs -25 25 V
Source-drain diode source current Tmb =25°C - 75 A
ISM peak source current tp≤10 µs; pulsed; Tmb =25°C - 57.7 A
NXP Semiconductors PHD71NQ03LT
N-channel TrenchMOS logic level FET
NXP Semiconductors PHD71NQ03LT
N-channel TrenchMOS logic level FET Thermal characteristics
Table 5. Thermal characteristicsRth(j-mb) thermal resistance from junction to
mounting base
see Figure 4 - - 1.25 K/W
Rth(j-a) thermal resistance from junction to
ambient
mounted on a printed-circuit
board; minimum footprint
-75 - K/W
NXP Semiconductors PHD71NQ03LT
N-channel TrenchMOS logic level FET CharacteristicsTable 6. Characteristics
Static characteristicsV(BR)DSS drain-source
breakdown voltage =250 µA; VGS =0V; Tj =-55°C 27 - - V =250 µA; VGS =0V; Tj =25°C 30 - - V
VGS(th) gate-source threshold
voltage =1mA; VDS = VGS; Tj= 175 °C; see Figure 8 0.6 - - V =1mA; VDS = VGS; Tj =-55 °C; see Figure 8 -- 2.9 V =1mA; VDS = VGS; Tj =25°C; see Figure 8 11.9 2.5 V
IDSS drain leakage current VDS =30V; VGS =0V; Tj=25°C - 0.05 1 µA
VDS =30V; VGS =0V; Tj =175°C - - 500 µA
IGSS gate leakage current VGS =20V; VDS =0V; Tj=25°C - 10 100 nA
VGS =-20 V; VDS =0V; Tj=25°C - 10 100 nA
RDSon drain-source on-state
resistance
VGS =5V; ID =25A; Tj= 175 °C; see Figure 9
and 10 21.6 27.4 mΩ
VGS =10V; ID =25A; Tj =25°C; see Figure 9 -8 10 mΩ
VGS =5V; ID =25A; Tj =25°C; see Figure 9
and 10
-12 15.2 mΩ
Dynamic characteristicsQG(tot) total gate charge ID =50A; VDS =15V; VGS =5V; Tj =25°C;
see Figure 11 13.2 - nC
QGS gate-source charge - 5.3 - nC
QGD gate-drain charge - 4.6 - nC
Ciss input capacitance VDS =25V; VGS=0 V; f=1 MHz; Tj =25°C;
see Figure 12 1220 - pF
Coss output capacitance - 330 - pF
Crss reverse transfer
capacitance 140 - pF
td(on) turn-on delay time VDS =15V; RL =0.6 Ω; VGS =4.5V;
RG(ext) =5.6 Ω; Tj =25°C; ID =25A
-15 - ns rise time - 150 - ns
td(off) turn-off delay time - 13.5 - ns fall time - 18 - ns
Source-drain diodeVSD source-drain voltage IS =25A; VGS =0V; Tj=25 °C; see Figure 13 -0.9 1.2 V
trr reverse recovery time IS =10A; dIS/dt= -100 A/µs; VGS =0V;
VDS =25V; Tj =25°C
-29 - ns recovered charge - 20 - nC
NXP Semiconductors PHD71NQ03LT
N-channel TrenchMOS logic level FETNXP Semiconductors PHD71NQ03LT
N-channel TrenchMOS logic level FET
